From nobody Mon Feb 9 09:42:48 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1565355399; cv=none; d=zoho.com; s=zohoarc; b=bUAQkbmRo7VeF2KsxS7tBCXA9KYiVH5jHu8RhBAXsr48ik8QfBstXgfSLcWbSKs08zdnIc97IcZNo6sY0Wkw1/8WyuNGlG0bcEsM5OFJN9W+0sAbLdB7b2iB+86sdM52Z/g2etP4YTe741eupyX70Aol2C96p06fQZndj2KfKp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565355399; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=nbVjMGh7fWtR0JQ/n5ZYlrsE9pPCsP96kSTtf6Ruhik=; b=an/SRajw3ZMCNSejLTjFuniHXradN0CxGXfd2kOeCPqKXS8jq5Ooi9r/w6bf6wS+v4IADyx43/48myb/CrNvEQEW7kUJcQ+DhM7zrng5CSCNX80VzTJceG+08tqx1KgD5neu+bjgAsE0bwNKF27f5sa+GAmxgGjBXeMuOxDheq4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1565355399216512.201417042759; Fri, 9 Aug 2019 05:56:39 -0700 (PDT) Received: from localhost ([::1]:59130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4Ri-00019C-Al for importer@patchew.org; Fri, 09 Aug 2019 08:56:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53015) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hw4K3-0002Gd-9M for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hw4Jz-0001Fa-UH for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:42 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:52591 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hw4Jz-00019X-9x for qemu-devel@nongnu.org; Fri, 09 Aug 2019 08:48:39 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BFC461A21C4; Fri, 9 Aug 2019 14:48:25 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 9F06D1A216D; Fri, 9 Aug 2019 14:48:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 9 Aug 2019 14:46:51 +0200 Message-Id: <1565354819-1495-19-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH for 4.2 v7 18/26] target/mips: Clean up handling of CP0 register 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Clean up handling of CP0 register 2. Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 7 ++++++ target/mips/translate.c | 64 ++++++++++++++++++++++++---------------------= ---- 2 files changed, 39 insertions(+), 32 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 597afa8..eebdc9f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -294,6 +294,13 @@ typedef struct mips_def_t mips_def_t; #define CP0_REG01__VPEOPT 7 /* CP0 Register 02 */ #define CP0_REG02__ENTRYLO0 0 +#define CP0_REG02__TCSTATUS 1 +#define CP0_REG02__TCBIND 2 +#define CP0_REG02__TCRESTART 3 +#define CP0_REG02__TCHALT 4 +#define CP0_REG02__TCCONTEXT 5 +#define CP0_REG02__TCSCHEDULE 6 +#define CP0_REG02__TCSCHEFBACK 7 /* CP0 Register 03 */ #define CP0_REG03__ENTRYLO1 0 #define CP0_REG03__GLOBALNUM 1 diff --git a/target/mips/translate.c b/target/mips/translate.c index dad32e9..3fb3757 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6929,7 +6929,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: { TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, @@ -6946,37 +6946,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) } register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcrestart(arg, cpu_env); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tchalt(arg, cpu_env); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tccontext(arg, cpu_env); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcschedule(arg, cpu_env); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcschefback(arg, cpu_env); register_name =3D "TCScheFBack"; @@ -7698,41 +7698,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: gen_helper_mtc0_entrylo0(cpu_env, arg); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); register_name =3D "TCScheFBack"; @@ -8449,41 +8449,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 0)); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcstatus(arg, cpu_env); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mfc0_tcbind(arg, cpu_env); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcrestart(arg, cpu_env); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tchalt(arg, cpu_env); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tccontext(arg, cpu_env); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcschedule(arg, cpu_env); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_dmfc0_tcschefback(arg, cpu_env); register_name =3D "TCScheFBack"; @@ -9170,41 +9170,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REGISTER_02: switch (sel) { - case 0: + case CP0_REG02__ENTRYLO0: gen_helper_dmtc0_entrylo0(cpu_env, arg); register_name =3D "EntryLo0"; break; - case 1: + case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcstatus(cpu_env, arg); register_name =3D "TCStatus"; break; - case 2: + case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcbind(cpu_env, arg); register_name =3D "TCBind"; break; - case 3: + case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcrestart(cpu_env, arg); register_name =3D "TCRestart"; break; - case 4: + case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tchalt(cpu_env, arg); register_name =3D "TCHalt"; break; - case 5: + case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tccontext(cpu_env, arg); register_name =3D "TCContext"; break; - case 6: + case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschedule(cpu_env, arg); register_name =3D "TCSchedule"; break; - case 7: + case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); gen_helper_mtc0_tcschefback(cpu_env, arg); register_name =3D "TCScheFBack"; --=20 2.7.4