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boundary="===============1829762541040913918==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============1829762541040913918== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516688063315851btcom_" --_000_156516688063315851btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Suggested-by: Richard Henderson Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 473b8e6..f6f4dd5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..95f2d20 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* Invert endianness for this page */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1 ? --_000_156516688063315851btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Notice new attribute, byte swap, and = force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c      | 11 ++++= +++++++
 include/exec/memattrs.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 473b8e6..f6f4dd5 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, ta= rget_ulong vaddr,
          */
         address |=3D TLB_RECHECK;
     }
+    if (attrs.byte_swap) {
+        address |=3D TLB_FORCE_SLOW;
+    }
     if (!memory_region_is_ram(section->mr) &&am= p;
         !memory_region_is_romd(section->m= r)) {
         /* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, C= PUIOTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUI= OTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..95f2d20 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
     unsigned int user:1;
     /* Requester ID (for MSI for example) */
     unsigned int requester_id:16;
+    /* Invert endianness for this page */
+    unsigned int byte_swap:1;
     /*
      * The following are target-specific page-table bi= ts.  These are not
      * related to actual memory transactions at all. &= nbsp;However, this structure
-- 
1.8.3.1

​

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