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boundary="===============4254821071505405456==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============4254821071505405456== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516681911114515btcom_" --_000_156516681911114515btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 170 +++++++++++++++++++++++++----------------------= ---- include/exec/memop.h | 6 ++ memory.c | 11 +--- 3 files changed, 90 insertions(+), 97 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6c83878..86d85cc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, = int size, static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr= , - MMUAccessType access_type, int size) + MMUAccessType access_type, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size= ), - iotlbentry->attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { @@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, size_memop(size= ), - iotlbentry->attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, - mmu_idx, iotlbentry->attrs, r, retaddr); + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1216,14 +1215,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, * access type. */ -static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endia= n) +static inline uint64_t handle_bswap(uint64_t val, MemOp op) { - if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { - switch (size) { - case 1: return val; - case 2: return bswap16(val); - case 4: return bswap32(val); - case 8: return bswap64(val); + if ((memop_big_endian(op) && NEED_BE_BSWAP) || + (!memop_big_endian(op) && NEED_LE_BSWAP)) { + switch (op & MO_SIZE) { + case MO_8: return val; + case MO_16: return bswap16(val); + case MO_32: return bswap32(val); + case MO_64: return bswap64(val); default: g_assert_not_reached(); } @@ -1246,7 +1246,7 @@ typedef uint64_t FullLoadHelper(CPUArchState *env, ta= rget_ulong addr, static inline uint64_t __attribute__((always_inline)) load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr, size_t size, bool big_endian, bool code_rea= d, + uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load) { uintptr_t mmu_idx =3D get_mmuidx(oi); @@ -1260,6 +1260,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, unsigned a_bits =3D get_alignment_bits(get_memop(oi)); void *haddr; uint64_t res; + size_t size =3D memop_size(op); /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1305,9 +1306,10 @@ load_helper(CPUArchState *env, target_ulong addr, TC= GMemOpIdx oi, } } + /* FIXME: io_readx ignores MO_BSWAP. */ res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, size); - return handle_bswap(res, size, big_endian); + mmu_idx, addr, retaddr, access_type, op); + return handle_bswap(res, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1324,7 +1326,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, r2 =3D full_load(env, addr2, oi, retaddr); shift =3D (addr & (size - 1)) * 8; - if (big_endian) { + if (memop_big_endian(op)) { /* Big-endian combine. */ res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); } else { @@ -1336,30 +1338,27 @@ load_helper(CPUArchState *env, target_ulong addr, T= CGMemOpIdx oi, do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); - switch (size) { - case 1: + switch (op) { + case MO_8: res =3D ldub_p(haddr); break; - case 2: - if (big_endian) { - res =3D lduw_be_p(haddr); - } else { - res =3D lduw_le_p(haddr); - } + case MO_BEUW: + res =3D lduw_be_p(haddr); break; - case 4: - if (big_endian) { - res =3D (uint32_t)ldl_be_p(haddr); - } else { - res =3D (uint32_t)ldl_le_p(haddr); - } + case MO_LEUW: + res =3D lduw_le_p(haddr); break; - case 8: - if (big_endian) { - res =3D ldq_be_p(haddr); - } else { - res =3D ldq_le_p(haddr); - } + case MO_BEUL: + res =3D (uint32_t)ldl_be_p(haddr); + break; + case MO_LEUL: + res =3D (uint32_t)ldl_le_p(haddr); + break; + case MO_BEQ: + res =3D ldq_be_p(haddr); + break; + case MO_LEQ: + res =3D ldq_le_p(haddr); break; default: g_assert_not_reached(); @@ -1381,8 +1380,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, false, - full_ldub_mmu); + return load_helper(env, addr, oi, retaddr, MO_8, false, full_ldub_mmu)= ; } tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, @@ -1394,7 +1392,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *en= v, target_ulong addr, static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } @@ -1407,7 +1405,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } @@ -1420,7 +1418,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } @@ -1433,7 +1431,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } @@ -1446,14 +1444,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *e= nv, target_ulong addr, uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); } @@ -1499,7 +1497,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env= , target_ulong addr, static inline void __attribute__((always_inline)) store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endi= an) + TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) { uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); @@ -1508,6 +1506,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, const size_t tlb_off =3D offsetof(CPUTLBEntry, addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); void *haddr; + size_t size =3D memop_size(op); /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1553,9 +1552,10 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, } } + /* FIXME: io_writex ignores MO_BSWAP. */ io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - handle_bswap(val, size, big_endian), - addr, retaddr, size); + handle_bswap(val, op), + addr, retaddr, op); return; } @@ -1591,7 +1591,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, */ for (i =3D 0; i < size; ++i) { uint8_t val8; - if (big_endian) { + if (memop_big_endian(op)) { /* Big-endian extract. */ val8 =3D val >> (((size - 1) * 8) - (i * 8)); } else { @@ -1605,30 +1605,27 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); - switch (size) { - case 1: + switch (op) { + case MO_8: stb_p(haddr, val); break; - case 2: - if (big_endian) { - stw_be_p(haddr, val); - } else { - stw_le_p(haddr, val); - } + case MO_BEUW: + stw_be_p(haddr, val); break; - case 4: - if (big_endian) { - stl_be_p(haddr, val); - } else { - stl_le_p(haddr, val); - } + case MO_LEUW: + stw_le_p(haddr, val); break; - case 8: - if (big_endian) { - stq_be_p(haddr, val); - } else { - stq_le_p(haddr, val); - } + case MO_BEUL: + stl_be_p(haddr, val); + break; + case MO_LEUL: + stl_le_p(haddr, val); + break; + case MO_BEQ: + stq_be_p(haddr, val); + break; + case MO_LEQ: + stq_le_p(haddr, val); break; default: g_assert_not_reached(); @@ -1639,43 +1636,43 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 1, false); + store_helper(env, addr, val, oi, retaddr, MO_8); } void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 2, false); + store_helper(env, addr, val, oi, retaddr, MO_LEUW); } void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 2, true); + store_helper(env, addr, val, oi, retaddr, MO_BEUW); } void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 4, false); + store_helper(env, addr, val, oi, retaddr, MO_LEUL); } void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 4, true); + store_helper(env, addr, val, oi, retaddr, MO_BEUL); } void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 8, false); + store_helper(env, addr, val, oi, retaddr, MO_LEQ); } void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 8, true); + store_helper(env, addr, val, oi, retaddr, MO_BEQ); } /* First set of helpers allows passing in of OI and RETADDR. This makes @@ -1740,8 +1737,7 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulon= g addr, uint64_t val, static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, true, - full_ldub_cmmu); + return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu)= ; } uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, @@ -1753,7 +1749,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEUW, true, full_le_lduw_cmmu); } @@ -1766,7 +1762,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEUW, true, full_be_lduw_cmmu); } @@ -1779,7 +1775,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEUL, true, full_le_ldul_cmmu); } @@ -1792,7 +1788,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEUL, true, full_be_ldul_cmmu); } @@ -1805,13 +1801,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *env, targ= et_ulong addr, uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEQ, true, helper_le_ldq_cmmu); } uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEQ, true, helper_be_ldq_cmmu); } diff --git a/include/exec/memop.h b/include/exec/memop.h index 47a5500..e6e03d9 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -129,4 +129,10 @@ static inline MemOp size_memop(unsigned size) #endif } +/* Big endianness from MemOp. */ +static inline bool memop_big_endian(MemOp op) +{ + return (op & MO_BSWAP) =3D=3D MO_BE; +} + #endif diff --git a/memory.c b/memory.c index 11db6ec..264c624 100644 --- a/memory.c +++ b/memory.c @@ -343,15 +343,6 @@ static void flatview_simplify(FlatView *view) } } -static bool memory_region_big_endian(MemoryRegion *mr) -{ -#ifdef TARGET_WORDS_BIGENDIAN - return mr->ops->endianness !=3D MO_LE; -#else - return mr->ops->endianness =3D=3D MO_BE; -#endif -} - static bool memory_region_wrong_endianness(MemoryRegion *mr) { #ifdef TARGET_WORDS_BIGENDIAN @@ -564,7 +555,7 @@ static MemTxResult access_with_adjusted_size(hwaddr add= r, /* FIXME: support unaligned access? */ access_size =3D MAX(MIN(size, access_size_max), access_size_min); access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); - if (memory_region_big_endian(mr)) { + if (memop_big_endian(mr->ops->endianness)) { for (i =3D 0; i < size; i +=3D access_size) { r |=3D access_fn(mr, addr + i, value, access_size, (size - access_size - i) * 8, access_mask, attrs); -- 1.8.3.1 ? --_000_156516681911114515btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c   | 170 ++++++&#= 43;++++++++++++++&#= 43;+++--------------------------
 include/exec/memop.h |   6 ++
 memory.c             |  11 &#= 43;---
 3 files changed, 90 insertions(+), 97 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..86d85cc 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulo= ng addr, int size,
 
 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlb= entry,
                    =       int mmu_idx, target_ulong addr, uintptr_t retaddr,
-                    = ;     MMUAccessType access_type, int size)
+                   &= nbsp;     MMUAccessType access_type, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, = CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_read(mr, mr_offset, &v= al, size_memop(size),
-                    = ;                iotlbentry->att= rs);
+    r =3D memory_region_dispatch_read(mr, mr_offset, &a= mp;val, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, access_type,
+        cpu_transaction_failed(cpu, physaddr,= addr, memop_size(op), access_type,
                    =             mmu_idx, iotlbentry->attrs, r,= retaddr);
     }
     if (locked) {
@@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CP= UIOTLBEntry *iotlbentry,
 
 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbent= ry,
                    =    int mmu_idx, uint64_t val, target_ulong addr,
-                    = ;  uintptr_t retaddr, int size)
+                   &= nbsp;  uintptr_t retaddr, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPU= IOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_write(mr, mr_offset, val, = size_memop(size),
-                    = ;                 iotlbentry->at= trs);
+    r =3D memory_region_dispatch_write(mr, mr_offset, v= al, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, MMU_DATA_STORE,
-                    = ;           mmu_idx, iotlbentry->attrs, r, reta= ddr);
+        cpu_transaction_failed(cpu, physaddr,= addr, memop_size(op),
+                   &= nbsp;           MMU_DATA_STORE, mmu_idx, iotlbentr= y->attrs, r,
+                   &= nbsp;           retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -1216,14 +1215,15 @@ static void *atomic_mmu_lookup(CPUArchStat= e *env, target_ulong addr,
  * access type.
  */
 
-static inline uint64_t handle_bswap(uint64_t val, int size, bool big_= endian)
+static inline uint64_t handle_bswap(uint64_t val, MemOp op)
 {
-    if ((big_endian && NEED_BE_BSWAP) || (!big_endi= an && NEED_LE_BSWAP)) {
-        switch (size) {
-        case 1: return val;
-        case 2: return bswap16(val);
-        case 4: return bswap32(val);
-        case 8: return bswap64(val);
+    if ((memop_big_endian(op) && NEED_BE_BSWAP)= ||
+        (!memop_big_endian(op) && NEE= D_LE_BSWAP)) {
+        switch (op & MO_SIZE) {
+        case MO_8: return val;
+        case MO_16: return bswap16(val);
+        case MO_32: return bswap32(val);
+        case MO_64: return bswap64(val);
         default:
             g_assert_not_reached()= ;
         }
@@ -1246,7 +1246,7 @@ typedef uint64_t FullLoadHelper(CPUArchState= *env, target_ulong addr,
 
 static inline uint64_t __attribute__((always_inline))
 load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi= ,
-            uintptr_t retaddr, size_t s= ize, bool big_endian, bool code_read,
+            uintptr_t retaddr, MemO= p op, bool code_read,
             FullLoadHelper *full_l= oad)
 {
     uintptr_t mmu_idx =3D get_mmuidx(oi);
@@ -1260,6 +1260,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
     unsigned a_bits =3D get_alignment_bits(get_memop(o= i));
     void *haddr;
     uint64_t res;
+    size_t size =3D memop_size(op);
 
     /* Handle CPU specific unaligned behaviour */
     if (addr & ((1 << a_bits) - 1)) {
@@ -1305,9 +1306,10 @@ load_helper(CPUArchState *env, target_ulong= addr, TCGMemOpIdx oi,
             }
         }
 
+        /* FIXME: io_readx ignores MO_BSWAP. =  */
         res =3D io_readx(env, &env_tlb(e= nv)->d[mmu_idx].iotlb[index],
-                    = ;   mmu_idx, addr, retaddr, access_type, size);
-        return handle_bswap(res, size, big_endian= );
+                   &= nbsp;   mmu_idx, addr, retaddr, access_type, op);
+        return handle_bswap(res, op);
     }
 
     /* Handle slow unaligned access (it spans two page= s or IO).  */
@@ -1324,7 +1326,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
         r2 =3D full_load(env, addr2, oi, ret= addr);
         shift =3D (addr & (size - 1)) * = 8;
 
-        if (big_endian) {
+        if (memop_big_endian(op)) {
             /* Big-endian combine.=  */
             res =3D (r1 << s= hift) | (r2 >> ((size * 8) - shift));
         } else {
@@ -1336,30 +1338,27 @@ load_helper(CPUArchState *env, target_ulon= g addr, TCGMemOpIdx oi,
 
  do_aligned_access:
     haddr =3D (void *)((uintptr_t)addr + entry->= ;addend);
-    switch (size) {
-    case 1:
+    switch (op) {
+    case MO_8:
         res =3D ldub_p(haddr);
         break;
-    case 2:
-        if (big_endian) {
-            res =3D lduw_be_p(haddr);
-        } else {
-            res =3D lduw_le_p(haddr);
-        }
+    case MO_BEUW:
+        res =3D lduw_be_p(haddr);
         break;
-    case 4:
-        if (big_endian) {
-            res =3D (uint32_t)ldl_be_p(= haddr);
-        } else {
-            res =3D (uint32_t)ldl_le_p(= haddr);
-        }
+    case MO_LEUW:
+        res =3D lduw_le_p(haddr);
         break;
-    case 8:
-        if (big_endian) {
-            res =3D ldq_be_p(haddr);
-        } else {
-            res =3D ldq_le_p(haddr);
-        }
+    case MO_BEUL:
+        res =3D (uint32_t)ldl_be_p(haddr);
+        break;
+    case MO_LEUL:
+        res =3D (uint32_t)ldl_le_p(haddr);
+        break;
+    case MO_BEQ:
+        res =3D ldq_be_p(haddr);
+        break;
+    case MO_LEQ:
+        res =3D ldq_le_p(haddr);
         break;
     default:
         g_assert_not_reached();
@@ -1381,8 +1380,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
 static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong ad= dr,
                    =            TCGMemOpIdx oi, uintptr_t retaddr)=
 {
-    return load_helper(env, addr, oi, retaddr, 1, false, fa= lse,
-                    = ;   full_ldub_mmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, fa= lse, full_ldub_mmu);
 }
 
 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_u= long addr,
@@ -1394,7 +1392,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArch= State *env, target_ulong addr,
 static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW,= false,
                    =     full_le_lduw_mmu);
 }
 
@@ -1407,7 +1405,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW,= false,
                    =     full_be_lduw_mmu);
 }
 
@@ -1420,7 +1418,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL,= false,
                    =     full_le_ldul_mmu);
 }
 
@@ -1433,7 +1431,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL,= false,
                    =     full_be_ldul_mmu);
 }
 
@@ -1446,14 +1444,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArc= hState *env, target_ulong addr,
 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,=
                    =         TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, = false,
                    =     helper_le_ldq_mmu);
 }
 
 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,=
                    =         TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, = false,
                    =     helper_be_ldq_mmu);
 }
 
@@ -1499,7 +1497,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchS= tate *env, target_ulong addr,
 
 static inline void __attribute__((always_inline))
 store_helper(CPUArchState *env, target_ulong addr, uint64_t val,=
-             TCGMemOpIdx oi, uintptr_t = retaddr, size_t size, bool big_endian)
+             TCGMemOpIdx oi, uintpt= r_t retaddr, MemOp op)
 {
     uintptr_t mmu_idx =3D get_mmuidx(oi);
     uintptr_t index =3D tlb_index(env, mmu_idx, addr);=
@@ -1508,6 +1506,7 @@ store_helper(CPUArchState *env, target_ulong= addr, uint64_t val,
     const size_t tlb_off =3D offsetof(CPUTLBEntry, add= r_write);
     unsigned a_bits =3D get_alignment_bits(get_memop(o= i));
     void *haddr;
+    size_t size =3D memop_size(op);
 
     /* Handle CPU specific unaligned behaviour */
     if (addr & ((1 << a_bits) - 1)) {
@@ -1553,9 +1552,10 @@ store_helper(CPUArchState *env, target_ulon= g addr, uint64_t val,
             }
         }
 
+        /* FIXME: io_writex ignores MO_BSWAP.=  */
         io_writex(env, &env_tlb(env)->= ;d[mmu_idx].iotlb[index], mmu_idx,
-                  handle= _bswap(val, size, big_endian),
-                  addr, = retaddr, size);
+                  ha= ndle_bswap(val, op),
+                  ad= dr, retaddr, op);
         return;
     }
 
@@ -1591,7 +1591,7 @@ store_helper(CPUArchState *env, target_ulong= addr, uint64_t val,
          */
         for (i =3D 0; i < size; ++= ;i) {
             uint8_t val8;
-            if (big_endian) {
+            if (memop_big_endian(op= )) {
                 /* Big-e= ndian extract.  */
                 val8 =3D= val >> (((size - 1) * 8) - (i * 8));
             } else {
@@ -1605,30 +1605,27 @@ store_helper(CPUArchState *env, target_ulo= ng addr, uint64_t val,
 
  do_aligned_access:
     haddr =3D (void *)((uintptr_t)addr + entry->= ;addend);
-    switch (size) {
-    case 1:
+    switch (op) {
+    case MO_8:
         stb_p(haddr, val);
         break;
-    case 2:
-        if (big_endian) {
-            stw_be_p(haddr, val);
-        } else {
-            stw_le_p(haddr, val);
-        }
+    case MO_BEUW:
+        stw_be_p(haddr, val);
         break;
-    case 4:
-        if (big_endian) {
-            stl_be_p(haddr, val);
-        } else {
-            stl_le_p(haddr, val);
-        }
+    case MO_LEUW:
+        stw_le_p(haddr, val);
         break;
-    case 8:
-        if (big_endian) {
-            stq_be_p(haddr, val);
-        } else {
-            stq_le_p(haddr, val);
-        }
+    case MO_BEUL:
+        stl_be_p(haddr, val);
+        break;
+    case MO_LEUL:
+        stl_le_p(haddr, val);
+        break;
+    case MO_BEQ:
+        stq_be_p(haddr, val);
+        break;
+    case MO_LEQ:
+        stq_le_p(haddr, val);
         break;
     default:
         g_assert_not_reached();
@@ -1639,43 +1636,43 @@ store_helper(CPUArchState *env, target_ulo= ng addr, uint64_t val,
 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, ui= nt8_t val,
                    =      TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 1, false);
+    store_helper(env, addr, val, oi, retaddr, MO_8);
 }
 
 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uin= t16_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 2, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEUW);=
 }
 
 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uin= t16_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 2, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEUW);=
 }
 
 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uin= t32_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 4, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEUL);=
 }
 
 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uin= t32_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 4, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEUL);=
 }
 
 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uin= t64_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 8, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEQ);<= /div>
 }
 
 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uin= t64_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 8, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEQ);<= /div>
 }
 
 /* First set of helpers allows passing in of OI and RETADDR. &nb= sp;This makes
@@ -1740,8 +1737,7 @@ void helper_be_stq_mmu(CPUArchState *env, ta= rget_ulong addr, uint64_t val,
 static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong a= ddr,
                    =             TCGMemOpIdx oi, uintptr_t retaddr= )
 {
-    return load_helper(env, addr, oi, retaddr, 1, false, tr= ue,
-                    = ;   full_ldub_cmmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, tr= ue, full_ldub_cmmu);
 }
 
 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr= ,
@@ -1753,7 +1749,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW,= true,
                    =     full_le_lduw_cmmu);
 }
 
@@ -1766,7 +1762,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW,= true,
                    =     full_be_lduw_cmmu);
 }
 
@@ -1779,7 +1775,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL,= true,
                    =     full_le_ldul_cmmu);
 }
 
@@ -1792,7 +1788,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL,= true,
                    =     full_be_ldul_cmmu);
 }
 
@@ -1805,13 +1801,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *= env, target_ulong addr,
 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr= ,
                    =          TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, = true,
                    =     helper_le_ldq_cmmu);
 }
 
 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr= ,
                    =          TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, = true,
                    =     helper_be_ldq_cmmu);
 }
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 47a5500..e6e03d9 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -129,4 +129,10 @@ static inline MemOp size_memop(unsigned size)=
 #endif
 }
 
+/* Big endianness from MemOp.  */
+static inline bool memop_big_endian(MemOp op)
+{
+    return (op & MO_BSWAP) =3D=3D MO_BE;
+}
+
 #endif
diff --git a/memory.c b/memory.c
index 11db6ec..264c624 100644
--- a/memory.c
+++ b/memory.c
@@ -343,15 +343,6 @@ static void flatview_simplify(FlatView *view)=
     }
 }
 
-static bool memory_region_big_endian(MemoryRegion *mr)
-{
-#ifdef TARGET_WORDS_BIGENDIAN
-    return mr->ops->endianness !=3D MO_LE;
-#else
-    return mr->ops->endianness =3D=3D MO_BE;
-#endif
-}
-
 static bool memory_region_wrong_endianness(MemoryRegion *mr)
 {
 #ifdef TARGET_WORDS_BIGENDIAN
@@ -564,7 +555,7 @@ static MemTxResult access_with_adjusted_size(h= waddr addr,
     /* FIXME: support unaligned access? */
     access_size =3D MAX(MIN(size, access_size_max), ac= cess_size_min);
     access_mask =3D MAKE_64BIT_MASK(0, access_size * 8= );
-    if (memory_region_big_endian(mr)) {
+    if (memop_big_endian(mr->ops->endianness)) {<= /div>
         for (i =3D 0; i < size; i += =3D access_size) {
             r |=3D access_fn(mr, a= ddr + i, value, access_size,
                    =      (size - access_size - i) * 8, access_mask, attrs);
-- 
1.8.3.1

​


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