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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng --- Changes in v2: None hw/riscv/sifive_u.c | 5 +++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 6 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bddf892..7b4a684 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -10,6 +10,7 @@ * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -43,6 +44,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" +#include "hw/riscv/sifive_u_otp.h" #include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" @@ -65,10 +67,12 @@ static const struct MemmapEntry { [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] =3D { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] =3D { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, [SIFIVE_U_GEM] =3D { 0x100900FC, 0x2000 }, }; =20 +#define SIFIVE_OTP_SERIAL 1 #define GEM_REVISION 0x10070109 =20 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, @@ -441,6 +445,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base); + sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL); =20 for (i =3D 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] =3D qdev_get_gpio_in(DEVICE(s->plic), i); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 19d5a6f..2f475c5 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -54,6 +54,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM }; --=20 2.7.4