From nobody Sat Feb 7 21:48:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=bt.com ARC-Seal: i=1; a=rsa-sha256; t=1564038694; cv=none; d=zoho.com; s=zohoarc; b=Jusgeq0HVW6z/m6giRyCNNojBaf0TU9iT82takFtQavbBRHoo9AgMjVMAiq8ThklQSRwKG67j8ZvhKszRsHWbE4PifSxAAgSNZ0vnPNfayOhxmSrKb2g1UIpLLm1mSAb5LplF7nVNh0CcAa+nxuQE8hPXHHZXsoDLB2+Vk9tV7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564038694; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dfkNN1agYNVtjcEIPuyfG2hX3YAoHyNGnXmwy2q0GgI=; b=Qr9RGkfI/SlbARquNWSTFi8efFuae2HNi0BKvXheHXxONREt8R1sf+XqNqMIBYUP9Fl0ExeDOqsDcyKMz+tQmMQJN2S6+H57YU4Vcga62Ai1p3pov7XJkZbn0YQPSKz7r+Jvd94oZEvJJMLJzrUXGBwfm9XoGAWTc45JIulY8IU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564038694293532.9600540369785; Thu, 25 Jul 2019 00:11:34 -0700 (PDT) Received: from localhost ([::1]:56384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXuX-0001V2-4E for importer@patchew.org; Thu, 25 Jul 2019 03:11:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54047) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqXuM-00010Y-9z for qemu-devel@nongnu.org; Thu, 25 Jul 2019 03:11:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqXuL-0004qP-5F for qemu-devel@nongnu.org; Thu, 25 Jul 2019 03:11:22 -0400 Received: from smtpe1.intersmtp.com ([62.239.224.235]:1901) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqXuD-0004dA-Jq; Thu, 25 Jul 2019 03:11:13 -0400 Received: from tpw09926dag18f.domain1.systemhost.net (10.9.212.26) by RDW083A011ED67.bt.com (10.187.98.37) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 08:16:19 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18f.domain1.systemhost.net (10.9.212.26) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 25 Jul 2019 08:11:11 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Thu, 25 Jul 2019 08:11:11 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute Thread-Index: AQHVQrgj3lFqGc7qHUC7G4brIcZ9XQ== Date: Thu, 25 Jul 2019 07:11:11 +0000 Message-ID: <1564038671025.43293@bt.com> References: , <1563810716254.18886@bt.com>,<1564038073754.91133@bt.com> In-Reply-To: <1564038073754.91133@bt.com> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.42] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.235 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v3 13/15] cputlb: Byte swap memory transaction attribute X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, walling@linux.ibm.com, mst@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, Alistair.Francis@wdc.com, arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com, ehabkost@redhat.com, sw@weilnetz.de, alex.williamson@redhat.com, qemu-arm@nongnu.org, david@gibson.dropbear.id.au, qemu-riscv@nongnu.org, cohuck@redhat.com, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, amarkovic@wavecomp.com, pbonzini@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e61b1eb..f292a87 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..a0644eb 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* SPARC64: TTE invert endianness */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1