From nobody Fri May 17 15:32:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1564034980; cv=none; d=zoho.com; s=zohoarc; b=A1slQ3iewjq2VgTNVbpWTpUzOs0VkbFt9qRLFSOKitEdnSazt0RY/8+e8hg54qXWaGnqj+kqWJRyb4gASIjMyrlGNmDSrYeNG7KSRTcsIya7VAuzlLg5sWBc5PGuRKAuZjruy98CQXUNsXihQVIR+Xp+teRcPjLlWBWndMcv+pA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564034980; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=+S+yg9XIepwDBJ7Dh+mkCvb9Pq7W+GnssC6S10wt3IY=; b=Q7Z2LPMfpRG/ng7ewdyKNpZkkYuCN4IW/uJzs2aKbca+EGjM4Y4ztWjyNnchu5b3Tn9Tdc1EvV60F94UWZagTI4Q4xhkC5Kw1j+IJDDGUK17Z3G/TKkxwSETRXp6052HfsFvJ4xGMP8b3jScD7EW05reyniKzyDY2bHPpNbrh6c= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1564034980726687.9898444228226; Wed, 24 Jul 2019 23:09:40 -0700 (PDT) Received: from localhost ([::1]:55960 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqWwd-00007J-N6 for importer@patchew.org; Thu, 25 Jul 2019 02:09:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40111) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hqWwS-0008AT-Ng for qemu-devel@nongnu.org; Thu, 25 Jul 2019 02:09:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hqWwR-0003C6-5Y for qemu-devel@nongnu.org; Thu, 25 Jul 2019 02:09:28 -0400 Received: from mga12.intel.com ([192.55.52.136]:28605) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hqWwQ-00038C-OX for qemu-devel@nongnu.org; Thu, 25 Jul 2019 02:09:27 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jul 2019 23:09:10 -0700 Received: from liujing-dell.bj.intel.com ([10.238.145.70]) by fmsmga002.fm.intel.com with ESMTP; 24 Jul 2019 23:09:08 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,305,1559545200"; d="scan'208";a="197762169" From: Jing Liu To: qemu-devel@nongnu.org, pbonzini@redhat.com Date: Thu, 25 Jul 2019 14:14:16 +0800 Message-Id: <1564035256-11828-1-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 Subject: [Qemu-devel] [PATCH v2] x86: Intel AVX512_BF16 feature enabling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jing Liu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel CooperLake cpu adds AVX512_BF16 instruction, defining as CPUID.(EAX=3D7,ECX=3D1):EAX[bit 05]. The patch adds a property for setting the subleaf of CPUID leaf 7 in case that people would like to specify it. The release spec link as follows, https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jing Liu --- target/i386/cpu.c | 39 ++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 7 +++++++ target/i386/kvm.c | 3 ++- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 805ce95..517dedb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -770,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_= t vendor1, /* CPUID_7_0_ECX_OSPKE is dynamic */ \ CPUID_7_0_ECX_LA57) #define TCG_7_0_EDX_FEATURES 0 +#define TCG_7_1_EAX_FEATURES 0 #define TCG_APM_FEATURES 0 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) @@ -1095,6 +1096,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D TCG_7_0_EDX_FEATURES, }, + [FEAT_7_1_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, "avx512-bf16", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, + }, + .tcg_features =3D TCG_7_1_EAX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -4293,13 +4313,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, case 7: /* Structured Extended Feature Flags Enumeration Leaf */ if (count =3D=3D 0) { - *eax =3D 0; /* Maximum ECX value for sub-leaves */ + /* Maximum ECX value for sub-leaves */ + *eax =3D env->cpuid_level_func7; *ebx =3D env->features[FEAT_7_0_EBX]; /* Feature flags */ *ecx =3D env->features[FEAT_7_0_ECX]; /* Feature flags */ if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { *ecx |=3D CPUID_7_0_ECX_OSPKE; } *edx =3D env->features[FEAT_7_0_EDX]; /* Feature flags */ + } else if (count =3D=3D 1) { + *eax =3D env->features[FEAT_7_1_EAX]; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; } else { *eax =3D 0; *ebx =3D 0; @@ -4949,6 +4975,11 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, F= eatureWord w) x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); break; } + + if (eax =3D=3D 7) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, + fi->cpuid.ecx); + } } =20 /* Calculate XSAVE components based on the configured CPU feature flags */ @@ -5067,6 +5098,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Erro= r **errp) x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); + x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); @@ -5098,6 +5130,9 @@ static void x86_cpu_expand_features(X86CPU *cpu, Erro= r **errp) } =20 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set = */ + if (env->cpuid_level_func7 =3D=3D UINT32_MAX) { + env->cpuid_level_func7 =3D env->cpuid_min_level_func7; + } if (env->cpuid_level =3D=3D UINT32_MAX) { env->cpuid_level =3D env->cpuid_min_level; } @@ -5869,6 +5904,8 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit= , 0), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), + DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, + UINT32_MAX), DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 05393cf..df9106f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -479,6 +479,7 @@ typedef enum FeatureWord { FEAT_7_0_EBX, /* CPUID[EAX=3D7,ECX=3D0].EBX */ FEAT_7_0_ECX, /* CPUID[EAX=3D7,ECX=3D0].ECX */ FEAT_7_0_EDX, /* CPUID[EAX=3D7,ECX=3D0].EDX */ + FEAT_7_1_EAX, /* CPUID[EAX=3D7,ECX=3D1].EAX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ @@ -692,6 +693,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypa= ss Disable */ =20 +#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction= */ + #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and = do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Predicti= on Barrier */ @@ -1322,6 +1325,10 @@ typedef struct CPUX86State { /* Fields after this point are preserved across CPU reset. */ =20 /* processor features (e.g. for CPUID insn) */ + /* Minimum cpuid leaf 7 value */ + uint32_t cpuid_level_func7; + /* Actual cpuid leaf 7 value */ + uint32_t cpuid_min_level_func7; /* Minimum level/xlevel/xlevel2, based on CPU model + features */ uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ diff --git a/target/i386/kvm.c b/target/i386/kvm.c index ec7870c..fd0a447 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1493,6 +1493,7 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; + case 0x7: case 0x14: { uint32_t times; =20 @@ -1505,7 +1506,7 @@ int kvm_arch_init_vcpu(CPUState *cs) for (j =3D 1; j <=3D times; ++j) { if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x14,ecx:0x%x)\n", j); + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); abort(); } c =3D &cpuid_data.entries[cpuid_i++]; --=20 1.8.3.1