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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 1/7] target/i386: handle filtered_features in a new function mark_unavailable_features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The next patch will add a different reason for filtering features, unrelated to host feature support. Extract a new function that takes care of disabli= ng the features and reporting them. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 76 ++++++++++++++++++++++++++++++---------------------= ---- 1 file changed, 41 insertions(+), 35 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index da6eb67..9149d0d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3236,17 +3236,39 @@ static char *feature_word_description(FeatureWordIn= fo *f, uint32_t bit) return NULL; } =20 -static void report_unavailable_features(FeatureWord w, uint32_t mask) +static bool x86_cpu_have_filtered_features(X86CPU *cpu) { + FeatureWord w; + + for (w =3D 0; w < ARRAY_SIZE(feature_word_info); w++) { + if (cpu->filtered_features[w]) { + return true; + } + } + + return false; +} + +static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint32_t= mask, + const char *prefix) +{ + CPUX86State *env =3D &cpu->env; FeatureWordInfo *f =3D &feature_word_info[w]; int i; char *feat_word_str; =20 + env->features[w] &=3D ~mask; + cpu->filtered_features[w] |=3D mask; + + if (!cpu->check_cpuid && !cpu->enforce_cpuid) { + return; + } + for (i =3D 0; i < 32; ++i) { if ((1UL << i) & mask) { feat_word_str =3D feature_word_description(f, i); - warn_report("%s doesn't support requested feature: %s%s%s [bit= %d]", - accel_uses_host_cpuid() ? "host" : "TCG", + warn_report("%s: %s%s%s [bit %d]", + prefix, feat_word_str, f->feat_names[i] ? "." : "", f->feat_names[i] ? f->feat_names[i] : "", i); @@ -3691,7 +3713,7 @@ static void x86_cpu_parse_featurestr(const char *type= name, char *features, } =20 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp); -static int x86_cpu_filter_features(X86CPU *cpu); +static void x86_cpu_filter_features(X86CPU *cpu); =20 /* Build a list with the name of all features on a feature word array */ static void x86_cpu_list_feature_names(FeatureWordArray features, @@ -3923,15 +3945,6 @@ static uint32_t x86_cpu_get_supported_feature_word(F= eatureWord w, return r; } =20 -static void x86_cpu_report_filtered_features(X86CPU *cpu) -{ - FeatureWord w; - - for (w =3D 0; w < FEATURE_WORDS; w++) { - report_unavailable_features(w, cpu->filtered_features[w]); - } -} - static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) { PropValue *pv; @@ -5170,21 +5183,20 @@ out: * * Returns: 0 if all flags are supported by the host, non-zero otherwise. */ -static int x86_cpu_filter_features(X86CPU *cpu) +static void x86_cpu_filter_features(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; FeatureWord w; - int rv =3D 0; + const char *prefix =3D accel_uses_host_cpuid() + ? "host doesn't support requested feature" + : "TCG doesn't support requested feature"; =20 for (w =3D 0; w < FEATURE_WORDS; w++) { uint32_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); uint32_t requested_features =3D env->features[w]; - env->features[w] &=3D host_feat; - cpu->filtered_features[w] =3D requested_features & ~env->features[= w]; - if (cpu->filtered_features[w]) { - rv =3D 1; - } + uint32_t unavailable_features =3D requested_features & ~host_feat; + mark_unavailable_features(cpu, w, unavailable_features, prefix); } =20 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && @@ -5210,13 +5222,9 @@ static int x86_cpu_filter_features(X86CPU *cpu) * host can't emulate the capabilities we report on * cpu_x86_cpuid(), intel-pt can't be enabled on the current h= ost. */ - env->features[FEAT_7_0_EBX] &=3D ~CPUID_7_0_EBX_INTEL_PT; - cpu->filtered_features[FEAT_7_0_EBX] |=3D CPUID_7_0_EBX_INTEL_= PT; - rv =3D 1; + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INT= EL_PT, prefix); } } - - return rv; } =20 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) @@ -5257,16 +5265,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) goto out; } =20 - if (x86_cpu_filter_features(cpu) && - (cpu->check_cpuid || cpu->enforce_cpuid)) { - x86_cpu_report_filtered_features(cpu); - if (cpu->enforce_cpuid) { - error_setg(&local_err, - accel_uses_host_cpuid() ? - "Host doesn't support requested features" : - "TCG doesn't support requested features"); - goto out; - } + x86_cpu_filter_features(cpu); + + if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { + error_setg(&local_err, + accel_uses_host_cpuid() ? + "Host doesn't support requested features" : + "TCG doesn't support requested features"); + goto out; } =20 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 2/7] target/i386: introduce generic feature dependency mechanism X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Sometimes a CPU feature does not make sense unless another is present. In the case of VMX features, KVM does not even allow setting the VMX controls to some invalid combinations. Therefore, this patch adds a generic mechanism that looks for bits that the user explicitly cleared, and uses them to remove other bits from the expanded CPU definition. If these dependent bits were also explicitly *set* by the user, this will be a warning for "-cpu check" and an error for "-cpu enforce". If not, then the dependent bits are cleared silently, for convenience. With VMX features, this will be used so that for example "-cpu host,-rdrand" will also hide support for RDRAND exiting. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 77 +++++++++++++++++++++++++++++++++++----------------= ---- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9149d0d..412e834 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -799,10 +799,6 @@ typedef struct FeatureWordInfo { /* If type=3D=3DMSR_FEATURE_WORD */ struct { uint32_t index; - struct { /*CPUID that enumerate this MSR*/ - FeatureWord cpuid_class; - uint32_t cpuid_flag; - } cpuid_dep; } msr; }; uint32_t tcg_features; /* Feature flags supported by TCG */ @@ -1197,10 +1193,6 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .msr =3D { .index =3D MSR_IA32_ARCH_CAPABILITIES, - .cpuid_dep =3D { - FEAT_7_0_EDX, - CPUID_7_0_EDX_ARCH_CAPABILITIES - } }, }, [FEAT_CORE_CAPABILITY] =3D { @@ -1217,14 +1209,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { }, .msr =3D { .index =3D MSR_IA32_CORE_CAPABILITY, - .cpuid_dep =3D { - FEAT_7_0_EDX, - CPUID_7_0_EDX_CORE_CAPABILITY, - }, }, }, }; =20 +typedef struct FeatureDep { + uint16_t from, to; + uint64_t from_flag, to_flags; +} FeatureDep; + +static FeatureDep feature_dependencies[] =3D { + { + .from =3D FEAT_7_0_EDX, .from_flag =3D CPUID_7_0_EDX_AR= CH_CAPABILITIES, + .to =3D FEAT_ARCH_CAPABILITIES, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_7_0_EDX, .from_flag =3D CPUID_7_0_EDX_CO= RE_CAPABILITY, + .to =3D FEAT_CORE_CAPABILITY, .to_flags =3D ~0ull, + }, +}; + typedef struct X86RegisterInfo32 { /* Name of register */ const char *name; @@ -5086,9 +5090,42 @@ static void x86_cpu_expand_features(X86CPU *cpu, Err= or **errp) { CPUX86State *env =3D &cpu->env; FeatureWord w; + int i; GList *l; Error *local_err =3D NULL; =20 + for (l =3D plus_features; l; l =3D l->next) { + const char *prop =3D l->data; + object_property_set_bool(OBJECT(cpu), true, prop, &local_err); + if (local_err) { + goto out; + } + } + + for (l =3D minus_features; l; l =3D l->next) { + const char *prop =3D l->data; + object_property_set_bool(OBJECT(cpu), false, prop, &local_err); + if (local_err) { + goto out; + } + } + + for (i =3D 0; i < ARRAY_SIZE(feature_dependencies); i++) { + FeatureDep *d =3D &feature_dependencies[i]; + if ((env->user_features[d->from] & d->from_flag) && + !(env->features[d->from] & d->from_flag)) { + uint64_t unavailable_features =3D env->features[d->to] & d->to= _flags; + + /* Not an error unless the dependent feature was added explici= tly. */ + mark_unavailable_features(cpu, d->to, unavailable_features & e= nv->user_features[d->to], + "This feature depends on other featu= res that were not requested"); + + /* Prevent adding the feature in the loop below. */ + env->user_features[d->to] |=3D d->to_flags; + env->features[d->to] &=3D ~d->to_flags; + } + } + /*TODO: Now cpu->max_features doesn't overwrite features * set using QOM properties, and we can convert * plus_features & minus_features to global properties @@ -5106,22 +5143,6 @@ static void x86_cpu_expand_features(X86CPU *cpu, Err= or **errp) } } =20 - for (l =3D plus_features; l; l =3D l->next) { - const char *prop =3D l->data; - object_property_set_bool(OBJECT(cpu), true, prop, &local_err); - if (local_err) { - goto out; - } - } - - for (l =3D minus_features; l; l =3D l->next) { - const char *prop =3D l->data; - object_property_set_bool(OBJECT(cpu), false, prop, &local_err); - if (local_err) { - goto out; - } - } - if (!kvm_enabled() || !cpu->expose_kvm) { env->features[FEAT_KVM] =3D 0; } --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1562080175; 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Tue, 02 Jul 2019 08:01:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 2 Jul 2019 17:01:17 +0200 Message-Id: <1562079681-19204-4-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1562079681-19204-1-git-send-email-pbonzini@redhat.com> References: <1562079681-19204-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 3/7] target/i386: expand feature words to 64 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" VMX requires 64-bit feature words for the IA32_VMX_EPT_VPID_CAP and IA32_VMX_BASIC MSRs. (The VMX control MSRs are 64-bit wide but actually have only 32 bits of information). Signed-off-by: Paolo Bonzini --- include/sysemu/kvm.h | 2 +- target/i386/cpu.c | 63 +++++++++++++++++++++++++++---------------------= ---- target/i386/cpu.h | 4 ++-- target/i386/kvm.c | 2 +- 4 files changed, 37 insertions(+), 34 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index acd90ae..f8157bc 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -463,7 +463,7 @@ int kvm_vm_check_extension(KVMState *s, unsigned int ex= tension); =20 uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function, uint32_t index, int reg); -uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index); +uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index); =20 =20 void kvm_set_sigmask_len(KVMState *s, unsigned int sigmask_len); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 412e834..4de44e4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -787,7 +787,7 @@ typedef struct FeatureWordInfo { * In cases of disagreement between feature naming conventions, * aliases may be added. */ - const char *feat_names[32]; + const char *feat_names[64]; union { /* If type=3D=3DCPUID_FEATURE_WORD */ struct { @@ -801,11 +801,11 @@ typedef struct FeatureWordInfo { uint32_t index; } msr; }; - uint32_t tcg_features; /* Feature flags supported by TCG */ - uint32_t unmigratable_flags; /* Feature flags known to be unmigratable= */ - uint32_t migratable_flags; /* Feature flags known to be migratable */ + uint64_t tcg_features; /* Feature flags supported by TCG */ + uint64_t unmigratable_flags; /* Feature flags known to be unmigratable= */ + uint64_t migratable_flags; /* Feature flags known to be migratable */ /* Features that shouldn't be auto-enabled by "-cpu host" */ - uint32_t no_autoenable_flags; + uint64_t no_autoenable_flags; } FeatureWordInfo; =20 static FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { @@ -1337,14 +1337,14 @@ const char *get_register_name_32(unsigned int reg) * Returns the set of feature flags that are supported and migratable by * QEMU, for a given FeatureWord. */ -static uint32_t x86_cpu_get_migratable_flags(FeatureWord w) +static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) { FeatureWordInfo *wi =3D &feature_word_info[w]; - uint32_t r =3D 0; + uint64_t r =3D 0; int i; =20 - for (i =3D 0; i < 32; i++) { - uint32_t f =3D 1U << i; + for (i =3D 0; i < 64; i++) { + uint64_t f =3D 1ULL << i; =20 /* If the feature name is known, it is implicitly considered migra= table, * unless it is explicitly set in unmigratable_flags */ @@ -3059,7 +3059,7 @@ void x86_cpu_change_kvm_default(const char *prop, con= st char *value) assert(pv->prop); } =20 -static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w, +static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, bool migratable_only); =20 static bool lmce_supported(void) @@ -3253,7 +3253,7 @@ static bool x86_cpu_have_filtered_features(X86CPU *cp= u) return false; } =20 -static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint32_t= mask, +static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t= mask, const char *prefix) { CPUX86State *env =3D &cpu->env; @@ -3268,8 +3268,8 @@ static void mark_unavailable_features(X86CPU *cpu, Fe= atureWord w, uint32_t mask, return; } =20 - for (i =3D 0; i < 32; ++i) { - if ((1UL << i) & mask) { + for (i =3D 0; i < 64; ++i) { + if ((1ULL << i) & mask) { feat_word_str =3D feature_word_description(f, i); warn_report("%s: %s%s%s [bit %d]", prefix, @@ -3512,7 +3512,7 @@ static void x86_cpu_get_feature_words(Object *obj, Vi= sitor *v, const char *name, void *opaque, Error **errp) { - uint32_t *array =3D (uint32_t *)opaque; + uint64_t *array =3D (uint64_t *)opaque; FeatureWord w; X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] =3D { }; X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] =3D { }; @@ -3596,6 +3596,7 @@ static inline void feat2prop(char *s) /* Return the feature property name for a feature flag bit */ static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) { + const char *name; /* XSAVE components are automatically enabled by other features, * so return the original feature name instead */ @@ -3609,9 +3610,11 @@ static const char *x86_cpu_feature_name(FeatureWord = w, int bitnr) } } =20 - assert(bitnr < 32); + assert(bitnr < 64); assert(w < FEATURE_WORDS); - return feature_word_info[w].feat_names[bitnr]; + name =3D feature_word_info[w].feat_names[bitnr]; + assert(bitnr < 32 || !(name && feature_word_info[w].type =3D=3D CPUID_= FEATURE_WORD)); + return name; } =20 /* Compatibily hack to maintain legacy +-feat semantic, @@ -3727,10 +3730,10 @@ static void x86_cpu_list_feature_names(FeatureWordA= rray features, strList **next =3D feat_names; =20 for (w =3D 0; w < FEATURE_WORDS; w++) { - uint32_t filtered =3D features[w]; + uint64_t filtered =3D features[w]; int i; - for (i =3D 0; i < 32; i++) { - if (filtered & (1UL << i)) { + for (i =3D 0; i < 64; i++) { + if (filtered & (1ULL << i)) { strList *new =3D g_new0(strList, 1); new->value =3D g_strdup(x86_cpu_feature_name(w, i)); *next =3D new; @@ -3866,7 +3869,7 @@ void x86_cpu_list(void) names =3D NULL; for (i =3D 0; i < ARRAY_SIZE(feature_word_info); i++) { FeatureWordInfo *fw =3D &feature_word_info[i]; - for (j =3D 0; j < 32; j++) { + for (j =3D 0; j < 64; j++) { if (fw->feat_names[j]) { names =3D g_list_append(names, (gpointer)fw->feat_names[j]= ); } @@ -3913,11 +3916,11 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Er= ror **errp) return cpu_list; } =20 -static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w, +static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, bool migratable_only) { FeatureWordInfo *wi =3D &feature_word_info[w]; - uint32_t r =3D 0; + uint64_t r =3D 0; =20 if (kvm_enabled()) { switch (wi->type) { @@ -4057,7 +4060,7 @@ static QDict *x86_cpu_static_props(void) for (w =3D 0; w < FEATURE_WORDS; w++) { FeatureWordInfo *fi =3D &feature_word_info[w]; int bit; - for (bit =3D 0; bit < 32; bit++) { + for (bit =3D 0; bit < 64; bit++) { if (!fi->feat_names[bit]) { continue; } @@ -5213,10 +5216,10 @@ static void x86_cpu_filter_features(X86CPU *cpu) : "TCG doesn't support requested feature"; =20 for (w =3D 0; w < FEATURE_WORDS; w++) { - uint32_t host_feat =3D + uint64_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); - uint32_t requested_features =3D env->features[w]; - uint32_t unavailable_features =3D requested_features & ~host_feat; + uint64_t requested_features =3D env->features[w]; + uint64_t unavailable_features =3D requested_features & ~host_feat; mark_unavailable_features(cpu, w, unavailable_features, prefix); } =20 @@ -5512,7 +5515,7 @@ static void x86_cpu_unrealizefn(DeviceState *dev, Err= or **errp) =20 typedef struct BitProperty { FeatureWord w; - uint32_t mask; + uint64_t mask; } BitProperty; =20 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, @@ -5520,7 +5523,7 @@ static void x86_cpu_get_bit_prop(Object *obj, Visitor= *v, const char *name, { X86CPU *cpu =3D X86_CPU(obj); BitProperty *fp =3D opaque; - uint32_t f =3D cpu->env.features[fp->w]; + uint64_t f =3D cpu->env.features[fp->w]; bool value =3D (f & fp->mask) =3D=3D fp->mask; visit_type_bool(v, name, &value, errp); } @@ -5573,7 +5576,7 @@ static void x86_cpu_register_bit_prop(X86CPU *cpu, { BitProperty *fp; ObjectProperty *op; - uint32_t mask =3D (1UL << bitnr); + uint64_t mask =3D (1ULL << bitnr); =20 op =3D object_property_find(OBJECT(cpu), prop_name, NULL); if (op) { @@ -5708,7 +5711,7 @@ static void x86_cpu_initfn(Object *obj) for (w =3D 0; w < FEATURE_WORDS; w++) { int bitnr; =20 - for (bitnr =3D 0; bitnr < 32; bitnr++) { + for (bitnr =3D 0; bitnr < 64; bitnr++) { x86_cpu_register_feature_bit_props(cpu, w, bitnr); } } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9334579..4e5dc30 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -501,7 +501,7 @@ typedef enum FeatureWord { FEATURE_WORDS, } FeatureWord; =20 -typedef uint32_t FeatureWordArray[FEATURE_WORDS]; +typedef uint64_t FeatureWordArray[FEATURE_WORDS]; =20 /* cpuid_features bits */ #define CPUID_FP87 (1U << 0) @@ -1438,7 +1438,7 @@ struct X86CPU { } mwait; =20 /* Features that were filtered out because of missing host capabilitie= s */ - uint32_t filtered_features[FEATURE_WORDS]; + FeatureWordArray filtered_features; =20 /* Enable PMU CPUID bits. This can't be enabled by default yet because * it doesn't have ABI stability guarantees, as it passes all PMU CPUID diff --git a/target/i386/kvm.c b/target/i386/kvm.c index e4b4f57..6801696 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -432,7 +432,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, return ret; } =20 -uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) +uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) { struct { struct kvm_msrs info; --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 02 Jul 2019 08:01:27 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 2 Jul 2019 17:01:18 +0200 Message-Id: <1562079681-19204-5-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1562079681-19204-1-git-send-email-pbonzini@redhat.com> References: <1562079681-19204-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 4/7] target/i386: add VMX definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These will be used to compile the list of VMX features for named CPU models, and/or by the code that sets up the VMX MSRs. Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 125 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4e5dc30..ec479d5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -452,6 +452,25 @@ typedef enum X86Seg { #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 =20 +#define MSR_IA32_VMX_BASIC 0x00000480 +#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 +#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 +#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 +#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 +#define MSR_IA32_VMX_MISC 0x00000485 +#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 +#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 +#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 +#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 +#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a +#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b +#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 +#define MSR_IA32_VMX_VMFUNC 0x00000491 + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -746,6 +765,112 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; =20 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) =20 +/* VMX MSR features */ +#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) +#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) +#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) + +#define MSR_VMX_MISC_STORE_LMA (1ULL << 5) +#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) +#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) +#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) +#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) +#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) + +#define MSR_VMX_EPT_EXECONLY (1ULL << 0) +#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) +#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) +#define MSR_VMX_EPT_UC (1ULL << 8) +#define MSR_VMX_EPT_WB (1ULL << 14) +#define MSR_VMX_EPT_2MB (1ULL << 16) +#define MSR_VMX_EPT_1GB (1ULL << 17) +#define MSR_VMX_EPT_INVEPT (1ULL << 20) +#define MSR_VMX_EPT_AD_BITS (1ULL << 21) +#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) +#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) +#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) +#define MSR_VMX_EPT_INVVPID (1ULL << 32) +#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) +#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) +#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) +#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) + +#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) + + +/* VMX controls */ +#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 +#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 +#define VMX_CPU_BASED_HLT_EXITING 0x00000080 +#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 +#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 +#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 +#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 +#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 +#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 +#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 +#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 +#define VMX_CPU_BASED_TPR_SHADOW 0x00200000 +#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 +#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 +#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 +#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 +#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 +#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 +#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 +#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 +#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 + +#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 +#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 +#define VMX_SECONDARY_EXEC_DESC 0x00000004 +#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 +#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 +#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 +#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 +#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 +#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 +#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 +#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 +#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 +#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 +#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 +#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 +#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 +#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 +#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 +#define VMX_SECONDARY_EXEC_XSAVES 0x00100000 + +#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 +#define VMX_PIN_BASED_NMI_EXITING 0x00000008 +#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 +#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 +#define VMX_PIN_BASED_POSTED_INTR 0x00000080 + +#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 +#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 +#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 +#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 +#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 +#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 +#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 +#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 +#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 +#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 +#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 +#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 + +#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 +#define VMX_VM_ENTRY_IA32E_MODE 0x00000200 +#define VMX_VM_ENTRY_SMM 0x00000400 +#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 +#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 +#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 +#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 +#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 +#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 +#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 + /* Supported Hyper-V Enlightenments */ #define HYPERV_FEAT_RELAXED 0 #define HYPERV_FEAT_VAPIC 1 --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1562080202; cv=none; d=zoho.com; s=zohoarc; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 5/7] vmxcap: correct the name of the variables X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The low bits are 1 if the control must be one, the high bits are 1 if the control can be one. Correct the variable names as they are very confusing. Signed-off-by: Paolo Bonzini --- scripts/kvm/vmxcap | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap index 99a8146..2db6832 100755 --- a/scripts/kvm/vmxcap +++ b/scripts/kvm/vmxcap @@ -51,15 +51,15 @@ class Control(object): return (val & 0xffffffff, val >> 32) def show(self): print(self.name) - mbz, mb1 =3D self.read2(self.cap_msr) - tmbz, tmb1 =3D 0, 0 + mb1, cb1 =3D self.read2(self.cap_msr) + tmb1, tcb1 =3D 0, 0 if self.true_cap_msr: - tmbz, tmb1 =3D self.read2(self.true_cap_msr) + tmb1, tcb1 =3D self.read2(self.true_cap_msr) for bit in sorted(self.bits.keys()): - zero =3D not (mbz & (1 << bit)) - one =3D mb1 & (1 << bit) - true_zero =3D not (tmbz & (1 << bit)) - true_one =3D tmb1 & (1 << bit) + zero =3D not (mb1 & (1 << bit)) + one =3D cb1 & (1 << bit) + true_zero =3D not (tmb1 & (1 << bit)) + true_one =3D tcb1 & (1 << bit) s=3D '?' if (self.true_cap_msr and true_zero and true_one and one and not zero): --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 6/7] target/i386: add VMX features X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add code to convert the VMX feature words back into MSR values, allowing the user to enable/disable VMX features as they wish. The same infrastructure enables support for limiting VMX features in named CPU models. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 221 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/i386/cpu.h | 9 +++ target/i386/kvm.c | 154 ++++++++++++++++++++++++++++++++++++- 3 files changed, 382 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4de44e4..12f76a3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1211,6 +1211,163 @@ static FeatureWordInfo feature_word_info[FEATURE_WO= RDS] =3D { .index =3D MSR_IA32_CORE_CAPABILITY, }, }, + + [FEAT_VMX_PROCBASED_CTLS] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", + NULL, NULL, NULL, "vmx-hlt-exit", + NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", + "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", + "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", + "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", = "vmx-movdr-exit", + "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", + "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-s= econdary-ctls", + }, + .msr =3D { + .index =3D MSR_IA32_VMX_TRUE_PROCBASED_CTLS, + } + }, + + [FEAT_VMX_SECONDARY_CTLS] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exi= t", + "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrest= ricted-guest", + "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-= exit", + "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encl= s-exit", + "vmx-rdseed-exit", "vmx-pml", NULL, NULL, + "vmx-xsaves", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_PROCBASED_CTLS2, + } + }, + + [FEAT_VMX_PINBASED_CTLS] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", + NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_TRUE_PINBASED_CTLS, + } + }, + + [FEAT_VMX_EXIT_CTLS] =3D { + .type =3D MSR_FEATURE_WORD, + /* + * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from + * the LM CPUID bit. + */ + .feat_names =3D { + NULL, NULL, "vmx-exit-nosave-debugctl", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, + "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-in= tr", + NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", + "vmx-exit-save-efer", "vmx-exit-load-efer", + "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", + NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, + } + }, + + [FEAT_VMX_ENTRY_CTLS] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, "vmx-entry-noload-debugctl", NULL, + NULL, NULL, NULL, NULL, + NULL, "vmx-entry-ia32e-mode", NULL, NULL, + NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat",= "vmx-entry-load-efer", + "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NUL= L, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_TRUE_ENTRY_CTLS, + } + }, + + [FEAT_VMX_MISC] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutd= own", + "vmx-activity-wait-sipi", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_MISC, + } + }, + + [FEAT_VMX_EPT_VPID_CAPS] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + "vmx-ept-execonly", NULL, NULL, NULL, + NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, + "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, + NULL, "vmx-invept-single-context", "vmx-invept-all-context", N= ULL, + NULL, NULL, NULL, NULL, + "vmx-invvpid", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "vmx-invvpid-single-addr", "vmx-invept-single-context", + "vmx-invvpid-all-context", "vmx-invept-single-context-nogl= obals", + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_VMX_EPT_VPID_CAP, + } + }, + + [FEAT_VMX_BASIC] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + [54] =3D "vmx-ins-outs", + [55] =3D "vmx-true-ctls", + }, + .msr =3D { + .index =3D MSR_IA32_VMX_BASIC, + }, + /* Just to be safe - we don't support setting the MSEG version fie= ld. */ + .no_autoenable_flags =3D MSR_VMX_BASIC_DUAL_MONITOR, + }, + + [FEAT_VMX_VMFUNC] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + [0] =3D "vmx-eptp-switching", + }, + .msr =3D { + .index =3D MSR_IA32_VMX_VMFUNC, + } + }, + }; =20 typedef struct FeatureDep { @@ -1227,6 +1384,70 @@ static FeatureDep feature_dependencies[] =3D { .from =3D FEAT_7_0_EDX, .from_flag =3D CPUID_7_0_EDX_CO= RE_CAPABILITY, .to =3D FEAT_CORE_CAPABILITY, .to_flags =3D ~0ull, }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_PROCBASED_CTLS, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_PINBASED_CTLS, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_EXIT_CTLS, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_ENTRY_CTLS, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_MISC, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_VMX, + .to =3D FEAT_VMX_BASIC, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_8000_0001_EDX, .from_flag =3D CPUID_EXT2_LM, + .to =3D FEAT_VMX_ENTRY_CTLS, .to_flags =3D VMX_VM_ENTRY_IA32= E_MODE, + }, + { + .from =3D FEAT_VMX_PROCBASED_CTLS, .from_flag =3D VMX_CPU_BASED_AC= TIVATE_SECONDARY_CONTROLS, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D ~0ull, + }, + { + .from =3D FEAT_XSAVE, .from_flag =3D CPUID_XSAVE_XSAV= ES, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D VMX_SECONDARY_EXE= C_XSAVES, + }, + { + .from =3D FEAT_1_ECX, .from_flag =3D CPUID_EXT_RDRAND, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D VMX_SECONDARY_EXE= C_RDRAND_EXITING, + }, + { + .from =3D FEAT_7_0_EBX, .from_flag =3D CPUID_7_0_EBX_IN= VPCID, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D VMX_SECONDARY_EXE= C_ENABLE_INVPCID, + }, + { + .from =3D FEAT_7_0_EBX, .from_flag =3D CPUID_7_0_EBX_RD= SEED, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D VMX_SECONDARY_EXE= C_RDSEED_EXITING, + }, + { + .from =3D FEAT_8000_0001_EDX, .from_flag =3D CPUID_EXT2_RDTSC= P, + .to =3D FEAT_VMX_SECONDARY_CTLS, .to_flags =3D VMX_SECONDARY_EXE= C_RDTSCP, + }, + { + .from =3D FEAT_VMX_SECONDARY_CTLS, .from_flag =3D VMX_SECONDARY_EX= EC_ENABLE_EPT, + .to =3D FEAT_VMX_EPT_VPID_CAPS, .to_flags =3D 0xffffffffull, + }, + { + .from =3D FEAT_VMX_SECONDARY_CTLS, .from_flag =3D VMX_SECONDARY_EX= EC_ENABLE_VPID, + .to =3D FEAT_VMX_EPT_VPID_CAPS, .to_flags =3D 0xffffffffull << = 32, + }, + { + .from =3D FEAT_VMX_SECONDARY_CTLS, .from_flag =3D VMX_SECONDARY_EX= EC_ENABLE_VMFUNC, + .to =3D FEAT_VMX_VMFUNC, .to_flags =3D ~0ull, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ec479d5..a5710c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -517,6 +517,15 @@ typedef enum FeatureWord { FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ FEAT_ARCH_CAPABILITIES, FEAT_CORE_CAPABILITY, + FEAT_VMX_PROCBASED_CTLS, + FEAT_VMX_SECONDARY_CTLS, + FEAT_VMX_PINBASED_CTLS, + FEAT_VMX_EXIT_CTLS, + FEAT_VMX_ENTRY_CTLS, + FEAT_VMX_MISC, + FEAT_VMX_EPT_VPID_CAPS, + FEAT_VMX_BASIC, + FEAT_VMX_VMFUNC, FEATURE_WORDS, } FeatureWord; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6801696..e35489c 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -96,6 +96,7 @@ static bool has_msr_virt_ssbd; static bool has_msr_smi_count; static bool has_msr_arch_capabs; static bool has_msr_core_capabs; +static bool has_msr_vmx_vmfunc; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -438,7 +439,8 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *s= , uint32_t index) struct kvm_msrs info; struct kvm_msr_entry entries[1]; } msr_data; - uint32_t ret; + uint64_t value; + uint32_t ret, can_be_one, must_be_one; =20 if (kvm_feature_msrs =3D=3D NULL) { /* Host doesn't support feature MS= Rs */ return 0; @@ -464,7 +466,25 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *= s, uint32_t index) exit(1); } =20 - return msr_data.entries[0].data; + value =3D msr_data.entries[0].data; + switch (index) { + case MSR_IA32_VMX_PROCBASED_CTLS2: + case MSR_IA32_VMX_TRUE_PINBASED_CTLS: + case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: + case MSR_IA32_VMX_TRUE_ENTRY_CTLS: + case MSR_IA32_VMX_TRUE_EXIT_CTLS: + /* + * Return true for bits that can be one, but do not have to be one. + * The SDM tells us which bits could have a "must be one" setting, + * so we can do the opposite transformation in make_vmx_msr_value. + */ + must_be_one =3D (uint32_t)value; + can_be_one =3D (uint32_t)(value >> 32); + return can_be_one & ~must_be_one; + + default: + return value; + } } =20 =20 @@ -1933,6 +1953,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_CORE_CAPABILITY: has_msr_core_capabs =3D true; break; + case MSR_IA32_VMX_VMFUNC: + has_msr_vmx_vmfunc =3D true; + break; } } } @@ -2407,6 +2430,126 @@ static int kvm_put_msr_feature_control(X86CPU *cpu) return 0; } =20 +static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) +{ + uint32_t default1, can_be_one, can_be_zero; + uint32_t must_be_one; + + switch (index) { + case MSR_IA32_VMX_TRUE_PINBASED_CTLS: + default1 =3D 0x00000016; + break; + case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: + default1 =3D 0x0401e172; + break; + case MSR_IA32_VMX_TRUE_ENTRY_CTLS: + default1 =3D 0x000011ff; + break; + case MSR_IA32_VMX_TRUE_EXIT_CTLS: + default1 =3D 0x00036dff; + break; + case MSR_IA32_VMX_PROCBASED_CTLS2: + default1 =3D 0; + break; + default: + abort(); + } + + /* If a feature bit is set, the control can be either set or clear. + * Otherwise the value is limited to either 0 or 1 by default1. + */ + can_be_one =3D features | default1; + can_be_zero =3D features | ~default1; + must_be_one =3D ~can_be_zero; + + /* + * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be = one). + * Bit 32:63 -> 1 if the control bit can be one. + */ + return must_be_one | (((uint64_t)can_be_one) << 32); +} + +#define VMCS12_MAX_FIELD_INDEX (0x17) + +static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) +{ + uint64_t kvm_vmx_basic =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_VMX_BASIC); + uint64_t kvm_vmx_misc =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_VMX_MISC); + uint64_t kvm_vmx_ept_vpid =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_VMX_EPT_VPID_CAP); + + /* + * If the guest is 64-bit, a value of 1 is allowed for the host address + * space size vmexit control. + */ + uint64_t fixed_vmx_exit =3D f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM + ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0; + + /* + * Bits 0-30, 32-44 and 50-53 come from the host. KVM should + * not change them for backwards compatibility. + */ + uint64_t fixed_vmx_basic =3D kvm_vmx_basic & 0x003c1fff7fffffffULL; + + /* + * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can + * change in the future but are always zero for now, clear them to be + * future proof. Bits 32-63 in theory could change, though KVM does + * not support dual-monitor treatment and probably never will; mask + * them out as well. + */ + uint64_t fixed_vmx_misc =3D kvm_vmx_misc & 0x0e00001f; + + /* + * EPT memory types should not change either, so we do not bother + * adding features for them. + */ + uint64_t fixed_vmx_ept_mask =3D + (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? = 0x4100ull : 0); + uint64_t fixed_vmx_ept_vpid =3D kvm_vmx_ept_vpid & fixed_vmx_ept_mask; + + kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, + make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, + f[FEAT_VMX_PROCBASED_CTLS])); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, + make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS, + f[FEAT_VMX_PINBASED_CTLS])); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, + make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS, + f[FEAT_VMX_EXIT_CTLS]) | fixed_vm= x_exit); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, + make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS, + f[FEAT_VMX_ENTRY_CTLS])); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2, + make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2, + f[FEAT_VMX_SECONDARY_CTLS])); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP, + f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC, + f[FEAT_VMX_BASIC] | fixed_vmx_basic); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC, + f[FEAT_VMX_MISC] | fixed_vmx_misc); + if (has_msr_vmx_vmfunc) { + kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]); + } + + /* + * Just to be safe, write these with constant values. The CRn_FIXED1 + * MSRs are generated by KVM based on the vCPU's CPUID. + */ + kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0, + CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, + CR4_VMXE_MASK); + kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, + VMCS12_MAX_FIELD_INDEX << 1); +} + static int kvm_put_msrs(X86CPU *cpu, int level) { CPUX86State *env =3D &cpu->env; @@ -2659,6 +2802,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]); } } + /* + * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but + * all kernels with MSR features should have them. + */ + if (kvm_feature_msrs && cpu_has_vmx(env)) { + kvm_msr_entry_add_vmx(cpu, env->features); + } =20 ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { --=20 1.8.3.1 From nobody Sun May 19 11:37:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 7/7] target/i386: work around KVM_GET_MSRS bug for secondary execution controls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some secondary controls are automatically enabled/disabled based on the CPU= ID values that are set for the guest. However, they are still available at a global level and therefore should be present when KVM_GET_MSRS is sent to /dev/kvm. Unfortunately KVM forgot to include those, so fix that. Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index e35489c..84b42a5 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -469,6 +469,23 @@ uint64_t kvm_arch_get_supported_msr_feature(KVMState *= s, uint32_t index) value =3D msr_data.entries[0].data; switch (index) { case MSR_IA32_VMX_PROCBASED_CTLS2: + /* KVM forgot to add these bits for some time, do this ourselves. = */ + if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & CPUID_XSAVE_X= SAVES) { + value |=3D (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32; + } + if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & CPUID_EXT_RDRAN= D) { + value |=3D (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32; + } + if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_I= NVPCID) { + value |=3D (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32; + } + if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_R= DSEED) { + value |=3D (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32; + } + if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & CPUID_= EXT2_RDTSCP) { + value |=3D (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32; + } + /* fall through */ case MSR_IA32_VMX_TRUE_PINBASED_CTLS: case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: case MSR_IA32_VMX_TRUE_ENTRY_CTLS: --=20 1.8.3.1