From nobody Tue Feb 10 11:14:35 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561718769; cv=none; d=zoho.com; s=zohoarc; b=mXgWbvsrslSl2oa2a5gWL5lAygdi8UNsWW7cRX37RW9t7BrlYz8Uo1t8w7YcurAeJw0PSG2UjEdsobTcmrzvUdzJ2X05r98sKcaGiRIXwcSa65lReUjpxQQfoSzPj2qLRYJbXqlJyrRITHkhKy10iM89NvFZUgqxnz8qIoGJCsE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561718769; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=AKY2QouieN7eJC7pnE+rd4UO4DIxoD1pYnI9hOJ3Hu0=; b=A2LblWYur/L5WMwDE3VfDTSUj1Fbg8955BgLTtQI1bviuwKep6/eUZukzfSQq7cLaGRYLTD1BCkwKMuBHX033plOQHvg/Bnpc0fKC31oUAM0z2NVxFXuRxf0py6OyPFCzGmiFF3AdPjEJmmtpGoPltNMR+7/+whzTs8qcFVijeE= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561718768645500.27937290129523; Fri, 28 Jun 2019 03:46:08 -0700 (PDT) Received: from localhost ([::1]:58702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgoON-0000ea-R4 for importer@patchew.org; Fri, 28 Jun 2019 06:46:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33646) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hgoMH-0006yB-BV for qemu-devel@nongnu.org; Fri, 28 Jun 2019 06:43:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hgoMG-0000IV-4g for qemu-devel@nongnu.org; Fri, 28 Jun 2019 06:43:57 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46657 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgoMF-0000H5-Tt for qemu-devel@nongnu.org; Fri, 28 Jun 2019 06:43:56 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 765461A2449; Fri, 28 Jun 2019 12:43:52 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 545C91A2015; Fri, 28 Jun 2019 12:43:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Fri, 28 Jun 2019 12:43:38 +0200 Message-Id: <1561718618-20218-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561718618-20218-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561718618-20218-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v16 5/5] linux-user: Handle EXCP_FPE properly for MIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Handle EXCP_FPE properly for MIPS in cpu loop. Note that a vast majority of FP instructions are not affected by the absence of the code in this patch, as they use alternative code paths for handling floating point exceptions (see, for example, invocations of update_fcr31()) - they rely on softfloat library for keeping track on exceptions that needs to be raised. However, there are few MIPS FP instructions (an example is CTC1) that use function do_raise_exception() directly, and they need the case that is added in this patch to propagate the FPE exception as designed. The code is based on kernel's function force_fcr31_sig() in arch/mips/kernel.traps.c. Reported-by: Yunqiang Su Signed-off-by: Aleksandar Markovic Reviewed-by: Laurent Vivier --- linux-user/mips/cpu_loop.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 43ba267..0ba894f 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -540,6 +540,23 @@ done_syscall: info.si_code =3D TARGET_ILL_ILLOPC; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_FPE: + info.si_signo =3D TARGET_SIGFPE; + info.si_errno =3D 0; + info.si_code =3D TARGET_FPE_FLTUNK; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { + info.si_code =3D TARGET_FPE_FLTINV; + } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { + info.si_code =3D TARGET_FPE_FLTDIV; + } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { + info.si_code =3D TARGET_FPE_FLTOVF; + } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW)= { + info.si_code =3D TARGET_FPE_FLTUND; + } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { + info.si_code =3D TARGET_FPE_FLTRES; + } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; /* The code below was inspired by the MIPS Linux kernel trap * handling code in arch/mips/kernel/traps.c. */ --=20 2.7.4