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Thu, 27 Jun 2019 06:57:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36512 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgS5v-0001g4-8x for qemu-devel@nongnu.org; Thu, 27 Jun 2019 06:57:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4E9151A456F; Thu, 27 Jun 2019 12:56:30 +0200 (CEST) Received: from rtrkw870-lin.domain.local (rtrkw870-lin.domain.local [10.10.13.132]) by mail.rt-rk.com (Postfix) with ESMTPSA id 15D9E1A45A3; Thu, 27 Jun 2019 12:56:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Brankovic To: qemu-devel@nongnu.org Date: Thu, 27 Jun 2019 12:56:23 +0200 Message-Id: <1561632985-24866-12-git-send-email-stefan.brankovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561632985-24866-1-git-send-email-stefan.brankovic@rt-rk.com> References: <1561632985-24866-1-git-send-email-stefan.brankovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 11/13] tcg: Add opcodes for verctor vmrgl instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stefan.brankovic@rt-rk.com, hsp.cat7@gmail.com, richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Stefan Brankovic --- accel/tcg/tcg-runtime-gvec.c | 42 ++++++++++++++++++++++++++++++++++++++++= ++ accel/tcg/tcg-runtime.h | 4 ++++ tcg/i386/tcg-target.h | 1 + tcg/tcg-op-gvec.c | 24 ++++++++++++++++++++++++ tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-vec.c | 5 +++++ tcg/tcg-op.h | 1 + tcg/tcg-opc.h | 1 + tcg/tcg.c | 2 ++ tcg/tcg.h | 1 + 10 files changed, 83 insertions(+) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 28173ae..152f277 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1500,3 +1500,45 @@ void HELPER(gvec_vmrgh32)(void *d, void *a, void *b,= uint32_t desc) } clear_high(d, oprsz, desc); } + +void HELPER(gvec_vmrgl8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < (oprsz / 2); i +=3D sizeof(uint8_t)) { + uint8_t aa =3D *(uint8_t *)(a + i); + uint8_t bb =3D *(uint8_t *)(b + i); + *(uint8_t *)(d + 2 * i) =3D bb; + *(uint8_t *)(d + 2 * i + sizeof(uint8_t)) =3D aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_vmrgl16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < (oprsz / 2); i +=3D sizeof(uint16_t)) { + uint16_t aa =3D *(uint16_t *)(a + i); + uint16_t bb =3D *(uint16_t *)(b + i); + *(uint16_t *)(d + 2 * i) =3D bb; + *(uint16_t *)(d + 2 * i + sizeof(uint16_t)) =3D aa; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_vmrgl32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint32_t)) { + uint32_t aa =3D *(uint32_t *)(a + i); + uint32_t bb =3D *(uint32_t *)(b + i); + *(uint32_t *)(d + 2 * i) =3D bb; + *(uint32_t *)(d + 2 * i + sizeof(uint32_t)) =3D aa; + } + clear_high(d, oprsz, desc); +} diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 089956f..fd0ba1e 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -309,3 +309,7 @@ DEF_HELPER_FLAGS_5(gvec_bitsel, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vmrgh8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vmrgh16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vmrgh32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_vmrgl8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_vmrgl16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_vmrgl32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index daae35f..e825324 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -193,6 +193,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec -1 #define TCG_TARGET_HAS_vmrgh_vec 1 +#define TCG_TARGET_HAS_vmrgl_vec 0 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 2560fb6..da1d272 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2125,6 +2125,30 @@ void tcg_gen_gvec_vmrgh(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 +static const TCGOpcode vecop_list_vmrgl[] =3D { INDEX_op_vmrgl_vec, 0 }; + +void tcg_gen_gvec_vmrgl(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen3 g[3] =3D { + { .fniv =3D tcg_gen_vmrgl_vec, + .fno =3D gen_helper_gvec_vmrgl8, + .opt_opc =3D vecop_list_vmrgl, + .vece =3D MO_8 }, + { .fniv =3D tcg_gen_vmrgl_vec, + .fno =3D gen_helper_gvec_vmrgl16, + .opt_opc =3D vecop_list_vmrgl, + .vece =3D MO_16 }, + { + .fniv =3D tcg_gen_vmrgl_vec, + .fno =3D gen_helper_gvec_vmrgl32, + .opt_opc =3D vecop_list_vmrgl, + .vece =3D MO_32 } + }; + tcg_debug_assert(vece <=3D MO_64); + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Perform a vector negation using normal negation and a mask. Compare gen_subv_mask above. */ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m) diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 8c04d71..a2eb45c 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -275,6 +275,8 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, ui= nt32_t aofs, /* Vector merge. */ void tcg_gen_gvec_vmrgh(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_vmrgl(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index fb0b83e..ab22335 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -668,6 +668,11 @@ void tcg_gen_vmrgh_vec(unsigned vece, TCGv_vec r, TCGv= _vec a, TCGv_vec b) do_op3(vece, r, a, b, INDEX_op_vmrgh_vec); } =20 +void tcg_gen_vmrgl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(vece, r, a, b, INDEX_op_vmrgl_vec); +} + void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { do_op3_nofail(vece, r, a, b, INDEX_op_shlv_vec); diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d8de022..c101170 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -986,6 +986,7 @@ void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_v= ec a, TCGv_vec b); void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 void tcg_gen_vmrgh_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_vmrgl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); =20 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 2bc3bdf..d99131a 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -236,6 +236,7 @@ DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mi= nmax_vec)) DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) =20 DEF(vmrgh_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_vmrgh_vec)) +DEF(vmrgl_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_vmrgl_vec)) =20 DEF(and_vec, 1, 2, 0, IMPLVEC) DEF(or_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/tcg.c b/tcg/tcg.c index fed9a6f..01245d5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1648,6 +1648,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_minmax_vec; case INDEX_op_vmrgh_vec: return have_vec && TCG_TARGET_HAS_vmrgh_vec; + case INDEX_op_vmrgl_vec: + return have_vec && TCG_TARGET_HAS_vmrgl_vec; case INDEX_op_bitsel_vec: return have_vec && TCG_TARGET_HAS_bitsel_vec; case INDEX_op_cmpsel_vec: diff --git a/tcg/tcg.h b/tcg/tcg.h index 05b9b51..6f9f333 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -187,6 +187,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_vmrgh_vec 0 +#define TCG_TARGET_HAS_vmrgl_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 #else --=20 2.7.4