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Thu, 27 Jun 2019 06:57:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36500 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hgS5v-0001fs-8J for qemu-devel@nongnu.org; Thu, 27 Jun 2019 06:57:35 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2DA471A45AE; Thu, 27 Jun 2019 12:56:30 +0200 (CEST) Received: from rtrkw870-lin.domain.local (rtrkw870-lin.domain.local [10.10.13.132]) by mail.rt-rk.com (Postfix) with ESMTPSA id EEA2D1A4583; Thu, 27 Jun 2019 12:56:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Brankovic To: qemu-devel@nongnu.org Date: Thu, 27 Jun 2019 12:56:21 +0200 Message-Id: <1561632985-24866-10-git-send-email-stefan.brankovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561632985-24866-1-git-send-email-stefan.brankovic@rt-rk.com> References: <1561632985-24866-1-git-send-email-stefan.brankovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 09/13] tcg/i386: Implement vector vmrgh instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stefan.brankovic@rt-rk.com, hsp.cat7@gmail.com, richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Stefan Brankovic --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index e11b22d..daae35f 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -192,7 +192,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec -1 -#define TCG_TARGET_HAS_vmrgh_vec 0 +#define TCG_TARGET_HAS_vmrgh_vec 1 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6ddeebf..31e1b2b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2823,6 +2823,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, case INDEX_op_umax_vec: insn =3D umax_insn[vece]; goto gen_simd; + case INDEX_op_vmrgh_vec: + insn =3D punpckh_insn[vece]; + goto gen_simd; case INDEX_op_shlv_vec: insn =3D shlv_insn[vece]; goto gen_simd; @@ -3223,6 +3226,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_umin_vec: case INDEX_op_smax_vec: case INDEX_op_umax_vec: + case INDEX_op_vmrgh_vec: case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: @@ -3321,6 +3325,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_umax_vec: case INDEX_op_abs_vec: return vece <=3D MO_32; + case INDEX_op_vmrgh_vec: + return vece <=3D MO_32 ? -1 : 0; =20 default: return 0; @@ -3614,6 +3620,14 @@ static void expand_vec_cmpsel(TCGType type, unsigned= vece, TCGv_vec v0, tcg_temp_free_vec(t); } =20 +static void expand_vec_vmrg(TCGOpcode opc, TCGType type, unsigned vece, + TCGv_vec v0, TCGv_vec v1, TCGv_vec v2) +{ + vec_gen_3(opc, type, vece, + tcgv_vec_arg(v0), tcgv_vec_arg(v2), + tcgv_vec_arg(v1)); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -3653,6 +3667,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGAr= g)); break; =20 + case INDEX_op_vmrgh_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_vmrg(opc, type, vece, v0, v1, v2); + break; + default: break; } --=20 2.7.4