From nobody Mon Feb 9 20:12:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561309704; cv=none; d=zoho.com; s=zohoarc; b=FihyG49E6MdBu7pr+dETQt69xD7X9lr3iKKrMLkc21WWEGU2924a9EpMQ8HJPodk5VeIY7LsxsQ+3sY0STK9Qj83AU4BqqzyYh5JlftQbFLyUkDkVW4prHWZFxtUtTg226PedvjwifdMxO9Hkcs0SMduMtHWuo3gp5F6lw1PRMo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561309704; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=89lgXHbN+pvxth4CTM7COwMV1d/Jdaj22vGzh7axjU8=; b=nGn6odQ4NvgZK5ryE+zH8Tmnd9kFEeKXbuxo5HUNIxq6Hc2GbQFy1dJ33pJjVyxy7wgHu0nS4AblyKlcDpPtdLghmO0UGf8QlQ/Fy4sLzJ0mT4yn5n+wtSuLP4jbA6avhep4nnitYy3pUEGTG+qtVtPbz1gaZLhBPwSL+mQGong= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561309703838231.89419525163976; Sun, 23 Jun 2019 10:08:23 -0700 (PDT) Received: from localhost ([::1]:45802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5yU-0003Oj-Hx for importer@patchew.org; Sun, 23 Jun 2019 13:08:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34158) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wM-0001dB-Q2 for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wL-0004Iu-GF for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41125 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wL-0004H9-4A for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:05 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 779C61A1DC5; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4DA051A1DB6; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:41 +0200 Message-Id: <1561309489-16146-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add support for vector saturated add/subtract using Altivec instructions: VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index a86ed57..368c250 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -155,7 +155,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 0 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index e254fa4..108882f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -474,12 +474,24 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, #define STVX XO31(231) #define STVEWX XO31(199) =20 +#define VADDSBS VX4(768) +#define VADDUBS VX4(512) #define VADDUBM VX4(0) +#define VADDSHS VX4(832) +#define VADDUHS VX4(576) #define VADDUHM VX4(64) +#define VADDSWS VX4(896) +#define VADDUWS VX4(640) #define VADDUWM VX4(128) =20 +#define VSUBSBS VX4(1792) +#define VSUBUBS VX4(1536) #define VSUBUBM VX4(1024) +#define VSUBSHS VX4(1856) +#define VSUBUHS VX4(1600) #define VSUBUHM VX4(1088) +#define VSUBSWS VX4(1920) +#define VSUBUWS VX4(1664) #define VSUBUWM VX4(1152) =20 #define VMAXSB VX4(258) @@ -2845,6 +2857,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: return vece <=3D MO_32 ? -1 : 0; @@ -2947,6 +2963,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, eq_op[4] =3D { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 }, gts_op[4] =3D { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 }, gtu_op[4] =3D { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 }, + ssadd_op[4] =3D { VADDSBS, VADDSHS, VADDSWS, 0 }, + usadd_op[4] =3D { VADDUBS, VADDUHS, VADDUWS, 0 }, + sssub_op[4] =3D { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, + ussub_op[4] =3D { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, umin_op[4] =3D { VMINUB, VMINUH, VMINUW, 0 }, smin_op[4] =3D { VMINSB, VMINSH, VMINSW, 0 }, umax_op[4] =3D { VMAXUB, VMAXUH, VMAXUW, 0 }, @@ -2973,6 +2993,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_sub_vec: insn =3D sub_op[vece]; break; + case INDEX_op_ssadd_vec: + insn =3D ssadd_op[vece]; + break; + case INDEX_op_sssub_vec: + insn =3D sssub_op[vece]; + break; + case INDEX_op_usadd_vec: + insn =3D usadd_op[vece]; + break; + case INDEX_op_ussub_vec: + insn =3D ussub_op[vece]; + break; case INDEX_op_smin_vec: insn =3D smin_op[vece]; break; @@ -3279,6 +3311,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_andc_vec: case INDEX_op_orc_vec: case INDEX_op_cmp_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_smax_vec: case INDEX_op_smin_vec: case INDEX_op_umax_vec: --=20 2.7.4