From nobody Mon Feb 9 23:40:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561310771; cv=none; d=zoho.com; s=zohoarc; b=hnLTMCVObgXwsZlwoHL6G4m+JP3MSgnMN6rNAN09BkSv55XT5NJDDGfuZZKhr8Ila9ZsxKP20mAHY+PWOtQiP2I0IIOdif80ww87zcbzYgU03v0bW5FmA2EbeLfhZ8l2M0Ow6sPLlyLicyQkZPWLoLXTevOlKNgG8d8AUKmG1WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561310771; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jpFFSdL7+4ylXXlvRvPGyvG2O9sRrELGNtpjQtGUE04=; b=j0qYuHb47FPF1jjP9pRXPTPQGeEYO16Hyw8kum27ca9eJlkzpQNyWVj+Othl4D9EuPsPqPxLhHQ4qp4p2cqESVKHi0Ju3ZWWtwzZn58K0kwIDPgXD4lnKoH9pQI+ekCStmmGyCsj6S1422cYhqEc0uzijzeaLbQPqg2MKWLP9aQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561310771772751.677422615718; Sun, 23 Jun 2019 10:26:11 -0700 (PDT) Received: from localhost ([::1]:45924 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf6Fm-0001ng-KO for importer@patchew.org; Sun, 23 Jun 2019 13:26:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34290) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wg-0001kq-Vb for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wc-0004jb-3b for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:25 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:39474 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wV-0003MV-Am for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:17 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 59A6C1A1D2D; Sun, 23 Jun 2019 19:05:11 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3D9F61A1D2A; Sun, 23 Jun 2019 19:05:11 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:35 +0200 Message-Id: <1561309489-16146-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Detect during initialization if the emulated CPU supports Altivec, and store the result in the flag have_isa_altivec. The definition of Altivec SIMD instructions set evolved over time. Different generations of Altivec will be distinguished by other flags in TCG, and they are currently have_isa_2_06 and have_isa_3_00. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 25 +++++++++++++++++++++++++ tcg/ppc/tcg-target.inc.c | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 690fa74..f6283f4 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -58,6 +58,7 @@ typedef enum { TCG_AREG0 =3D TCG_REG_R27 } TCGReg; =20 +extern bool have_isa_altivec; extern bool have_isa_2_06; extern bool have_isa_3_00; =20 @@ -135,6 +136,30 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +/* + * While technically Altivec could support V64, it has no 64-bit store + * instruction and substituting two 32-bit stores makes the generated + * code quite large. + */ +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_v128 have_isa_altivec +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_cmp_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 8e1bba7..26892de 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -64,6 +64,7 @@ =20 static tcg_insn_unit *tb_ret_addr; =20 +bool have_isa_altivec; bool have_isa_2_06; bool have_isa_3_00; =20 @@ -2781,6 +2782,9 @@ static void tcg_target_init(TCGContext *s) unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); unsigned long hwcap2 =3D qemu_getauxval(AT_HWCAP2); =20 + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { + have_isa_altivec =3D true; + } if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 =3D true; } @@ -2792,6 +2796,10 @@ static void tcg_target_init(TCGContext *s) =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; + if (have_isa_altivec) { + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xffffffff00000000ull; + } =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); --=20 2.7.4