From nobody Tue Feb 10 05:40:01 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561311072; cv=none; d=zoho.com; s=zohoarc; b=nDSqM9+tUgUFfcUYGCGX8MduRf9SAN0Vy9ywtKuvqACiLaY1g4aGz6+b2Zb4NTSNHMDhBvFXHDpxriqAN4Ww/b1zw2CzutFKVN8vAusfLGgDOGXem+eXYkvVv8c5iItbWkzzdaSjV03yiR6pXvYroSLZ/02FdEwMUeu77ox9QRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561311072; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=aSbrmliSPiL/6NudB6VG2v4K2+rB8R6j+K6eiTi/pMc=; b=XFtD6/bKVQM7Nj9aWfyBHIQXQ74Pda8RLb/vUbWg5j+XJm/73GogjK6xLUzzROtDi6JKo2PQeaH2pa4tYPyn5nyd88MI5zu53osDrVtI16MGrLNYVTkaC4EqGoRSfjFLvLMag9xaq4p9hyzvTT2XRI/SGTJJdDNWl1JBxCxohYo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561311072675647.6452762087217; Sun, 23 Jun 2019 10:31:12 -0700 (PDT) Received: from localhost ([::1]:45994 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf6Kb-0007tx-TE for importer@patchew.org; Sun, 23 Jun 2019 13:31:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34335) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hf5wk-0001o7-QM for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hf5wg-0004rA-Mx for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:28 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41133 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hf5wZ-0004Ja-E1 for qemu-devel@nongnu.org; Sun, 23 Jun 2019 13:06:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B5C001A1E02; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 84D531A1D85; Sun, 23 Jun 2019 19:05:45 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 23 Jun 2019 19:04:45 +0200 Message-Id: <1561309489-16146-13-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, "David Gibson --cc=amarkovic @ wavecomp . com" , Mark Cave-Ayland , Aleksandar Markovic , hsp.cat7@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson For Altivec, this is always an expansion. Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic --- tcg/ppc/tcg-target.h | 2 +- tcg/ppc/tcg-target.inc.c | 112 +++++++++++++++++++++++++++++++++++++++++++= +++- tcg/ppc/tcg-target.opc.h | 8 ++++ 3 files changed, 120 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 766706f..a130192 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -154,7 +154,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_cmp_vec 1 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 3eb18cb..3005c51 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -526,6 +526,25 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, #define VSRAB VX4(772) #define VSRAH VX4(836) #define VSRAW VX4(900) +#define VRLB VX4(4) +#define VRLH VX4(68) +#define VRLW VX4(132) + +#define VMULEUB VX4(520) +#define VMULEUH VX4(584) +#define VMULOUB VX4(8) +#define VMULOUH VX4(72) +#define VMSUMUHM VX4(38) + +#define VMRGHB VX4(12) +#define VMRGHH VX4(76) +#define VMRGHW VX4(140) +#define VMRGLB VX4(268) +#define VMRGLH VX4(332) +#define VMRGLW VX4(396) + +#define VPKUHUM VX4(14) +#define VPKUWUM VX4(78) =20 #define VAND VX4(1028) #define VANDC VX4(1092) @@ -2876,6 +2895,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_sarv_vec: return vece <=3D MO_32; case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: @@ -2989,7 +3009,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, smax_op[4] =3D { VMAXSB, VMAXSH, VMAXSW, 0 }, shlv_op[4] =3D { VSLB, VSLH, VSLW, 0 }, shrv_op[4] =3D { VSRB, VSRH, VSRW, 0 }, - sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }; + sarv_op[4] =3D { VSRAB, VSRAH, VSRAW, 0 }, + mrgh_op[4] =3D { VMRGHB, VMRGHH, VMRGHW, 0 }, + mrgl_op[4] =3D { VMRGLB, VMRGLH, VMRGLW, 0 }, + muleu_op[4] =3D { VMULEUB, VMULEUH, 0, 0 }, + mulou_op[4] =3D { VMULOUB, VMULOUH, 0, 0 }, + pkum_op[4] =3D { VPKUHUM, VPKUWUM, 0, 0 }, + rotl_op[4] =3D { VRLB, VRLH, VRLW, 0 }; =20 TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; @@ -3078,6 +3104,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, } break; =20 + case INDEX_op_ppc_mrgh_vec: + insn =3D mrgh_op[vece]; + break; + case INDEX_op_ppc_mrgl_vec: + insn =3D mrgl_op[vece]; + break; + case INDEX_op_ppc_muleu_vec: + insn =3D muleu_op[vece]; + break; + case INDEX_op_ppc_mulou_vec: + insn =3D mulou_op[vece]; + break; + case INDEX_op_ppc_pkum_vec: + insn =3D pkum_op[vece]; + break; + case INDEX_op_ppc_rotl_vec: + insn =3D rotl_op[vece]; + break; + case INDEX_op_ppc_msum_vec: + tcg_debug_assert(vece =3D=3D MO_16); + tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])= ); + return; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ @@ -3147,6 +3196,53 @@ static void expand_vec_cmp(TCGType type, unsigned ve= ce, TCGv_vec v0, } } =20 +static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2) +{ + TCGv_vec t1 =3D tcg_temp_new_vec(type); + TCGv_vec t2 =3D tcg_temp_new_vec(type); + TCGv_vec t3, t4; + + switch (vece) { + case MO_8: + case MO_16: + vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), + tcgv_vec_arg(t1), tcgv_vec_arg(t2)); + vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v0), tcgv_vec_arg(t1)); + break; + + case MO_32: + t3 =3D tcg_temp_new_vec(type); + t4 =3D tcg_temp_new_vec(type); + tcg_gen_dupi_vec(MO_8, t4, -16); + vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1), + tcgv_vec_arg(v2), tcgv_vec_arg(t4)); + vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), + tcgv_vec_arg(v1), tcgv_vec_arg(v2)); + tcg_gen_dupi_vec(MO_8, t3, 0); + vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3), + tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3)); + vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3), + tcgv_vec_arg(t3), tcgv_vec_arg(t4)); + tcg_gen_add_vec(MO_32, v0, t2, t3); + tcg_temp_free_vec(t3); + tcg_temp_free_vec(t4); + break; + + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(t1); + tcg_temp_free_vec(t2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -3173,6 +3269,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, = unsigned vece, v2 =3D temp_tcgv_vec(arg_temp(a2)); expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_mul_vec: + v2 =3D temp_tcgv_vec(arg_temp(a2)); + expand_vec_mul(type, vece, v0, v1, v2); + break; default: g_assert_not_reached(); } @@ -3219,6 +3319,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef v_r =3D { .args_ct_str =3D { "v", "r" } }; static const TCGTargetOpDef v_v =3D { .args_ct_str =3D { "v", "v" } }; static const TCGTargetOpDef v_v_v =3D { .args_ct_str =3D { "v", "v", "= v" } }; + static const TCGTargetOpDef v_v_v_v + =3D { .args_ct_str =3D { "v", "v", "v", "v" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -3374,6 +3476,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_ppc_mrgh_vec: + case INDEX_op_ppc_mrgl_vec: + case INDEX_op_ppc_muleu_vec: + case INDEX_op_ppc_mulou_vec: + case INDEX_op_ppc_pkum_vec: + case INDEX_op_ppc_rotl_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: @@ -3382,6 +3490,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_vec: case INDEX_op_dupm_vec: return &v_r; + case INDEX_op_ppc_msum_vec: + return &v_v_v_v; =20 default: return NULL; diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h index 4816a6c..5c6a5ad 100644 --- a/tcg/ppc/tcg-target.opc.h +++ b/tcg/ppc/tcg-target.opc.h @@ -1,3 +1,11 @@ /* Target-specific opcodes for host vector expansion. These will be emitted by tcg_expand_vec_op. For those familiar with GCC internals, consider these to be UNSPEC with names. */ + +DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC) +DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC) +DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC) --=20 2.7.4