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X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 01/25] kvm-all: Add/update fprintf's for kvm_*_ioeventfd_del X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yury Kotov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yury Kotov Signed-off-by: Yury Kotov Message-Id: <20190607090830.18807-1-yury-kotov@yandex-team.ru> Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b0c4bed..d2f481a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -863,8 +863,8 @@ static void kvm_mem_ioeventfd_add(MemoryListener *liste= ner, data, true, int128_get64(section->size), match_data); if (r < 0) { - fprintf(stderr, "%s: error adding ioeventfd: %s\n", - __func__, strerror(-r)); + fprintf(stderr, "%s: error adding ioeventfd: %s (%d)\n", + __func__, strerror(-r), -r); abort(); } } @@ -881,6 +881,8 @@ static void kvm_mem_ioeventfd_del(MemoryListener *liste= ner, data, false, int128_get64(section->size), match_data); if (r < 0) { + fprintf(stderr, "%s: error deleting ioeventfd: %s (%d)\n", + __func__, strerror(-r), -r); abort(); } } @@ -897,8 +899,8 @@ static void kvm_io_ioeventfd_add(MemoryListener *listen= er, data, true, int128_get64(section->size), match_data); if (r < 0) { - fprintf(stderr, "%s: error adding ioeventfd: %s\n", - __func__, strerror(-r)); + fprintf(stderr, "%s: error adding ioeventfd: %s (%d)\n", + __func__, strerror(-r), -r); abort(); } } @@ -916,6 +918,8 @@ static void kvm_io_ioeventfd_del(MemoryListener *listen= er, data, false, int128_get64(section->size), match_data); if (r < 0) { + fprintf(stderr, "%s: error deleting ioeventfd: %s (%d)\n", + __func__, strerror(-r), -r); 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 02/25] hax: Honor CPUState::halted X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Colin Xu , Yu Ning , Chuanxiao Dong Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Colin Xu QEMU tracks whether a vcpu is halted using CPUState::halted. E.g., after initialization or reset, halted is 0 for the BSP (vcpu 0) and 1 for the APs (vcpu 1, 2, ...). A halted vcpu should not be handed to the hypervisor to run (e.g. hax_vcpu_run()). Under HAXM, Android Emulator sometimes boots into a "vcpu shutdown request" error while executing in SeaBIOS, with the HAXM driver logging a guest triple fault in vcpu 1, 2, ... at RIP 0x3. That is ultimately because the HAX accelerator asks HAXM to run those APs when they are still in the halted state. Normally, the vcpu thread for an AP will start by looping in qemu_wait_io_event(), until the BSP kicks it via a pair of IPIs (INIT followed by SIPI). But because the HAX accelerator does not honor cpu->halted, it allows the AP vcpu thread to proceed to hax_vcpu_run() as soon as it receives any kick, even if the kick does not come from the BSP. It turns out that emulator has a worker thread which periodically kicks every vcpu thread (possibly to collect CPU usage data), and if one of these kicks comes before those by the BSP, the AP will start execution from the wrong RIP, resulting in the aforementioned SMP boot failure. The solution is inspired by the KVM accelerator (credit to Chuanxiao Dong for the pointer): 1. Get rid of questionable logic that unconditionally resets cpu->halted before hax_vcpu_run(). Instead, only reset it at the right moments (there are only a few "unhalt" events). 2. Add a check for cpu->halted before hax_vcpu_run(). Note that although the non-Unrestricted Guest (!ug_platform) code path also forcibly resets cpu->halted, it is left untouched, because only the UG code path supports SMP guests. The patch is first merged to android emulator with Change-Id: I9c5752cc737fd305d7eace1768ea12a07309d716 Cc: Yu Ning Cc: Chuanxiao Dong Signed-off-by: Colin Xu Message-Id: <20190610021939.13669-1-colin.xu@intel.com> --- cpus.c | 1 - target/i386/hax-all.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/cpus.c b/cpus.c index dde3b7b..1af51b7 100644 --- a/cpus.c +++ b/cpus.c @@ -1594,7 +1594,6 @@ static void *qemu_hax_cpu_thread_fn(void *arg) =20 cpu->thread_id =3D qemu_get_thread_id(); cpu->created =3D true; - cpu->halted =3D 0; current_cpu =3D cpu; =20 hax_init_vcpu(cpu); diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index 64fd51a..9e7b779 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -471,13 +471,35 @@ static int hax_vcpu_hax_exec(CPUArchState *env) return 0; } =20 - cpu->halted =3D 0; - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(x86_cpu->apic_state); } =20 + /* After a vcpu is halted (either because it is an AP and has just been + * reset, or because it has executed the HLT instruction), it will not= be + * run (hax_vcpu_run()) until it is unhalted. The next few if blocks c= heck + * for events that may change the halted state of this vcpu: + * a) Maskable interrupt, when RFLAGS.IF is 1; + * Note: env->eflags may not reflect the current RFLAGS state, bec= ause + * it is not updated after each hax_vcpu_run(). We cannot af= ford + * to fail to recognize any unhalt-by-maskable-interrupt eve= nt + * (in which case the vcpu will halt forever), and yet we ca= nnot + * afford the overhead of hax_vcpu_sync_state(). The current + * solution is to err on the side of caution and have the HLT + * handler (see case HAX_EXIT_HLT below) unconditionally set= the + * IF_MASK bit in env->eflags, which, in effect, disables the + * RFLAGS.IF check. + * b) NMI; + * c) INIT signal; + * d) SIPI signal. + */ + if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + (env->eflags & IF_MASK)) || + (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu->halted =3D 0; + } + if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { DPRINTF("\nhax_vcpu_hax_exec: handling INIT for %d\n", cpu->cpu_index); @@ -493,6 +515,16 @@ static int hax_vcpu_hax_exec(CPUArchState *env) hax_vcpu_sync_state(env, 1); } =20 + if (cpu->halted) { + /* If this vcpu is halted, we must not ask HAXM to run it. Instead= , we + * break out of hax_smp_cpu_exec() as if this vcpu had executed HL= T. + * That way, this vcpu thread will be trapped in qemu_wait_io_even= t(), + * until the vcpu is unhalted. + */ + cpu->exception_index =3D EXCP_HLT; + return 0; + } + do { int hax_ret; =20 --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561081710; cv=none; d=zoho.com; s=zohoarc; b=FfTLTQdqYlHukv3mTaqbX5SkUZqFG+mRR5VhqXhdkZuEgkHztkBfM6ZfGl4jw317XJtYvFc6Pq/xGTqjnrXN54vYz7BfDWkgRxkywFtl8pUXL0QeKdmrwayPuDfiw+OzMfx5Y2FzWC3Up0hZ8avggtVi68Bf6XLhBVgF3NVfLJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561081710; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jRxVFuHpbr4EI8miJwJfPa6C/23qivxTRXPqmbxVszk=; b=aHYuT3oN21z568UFSdq4lqEZGlF0WpgTvs68B4KLUosYWIm5QATsdhqRm1mBivHql8HWIyZU63akLu+cY6Jca3LYXFBLULkNNrd3iIgJTNnzzCXbzl9Fa8ERf7ozuD6UdUFTICJ9OnvSMbjPcLS7BpvAumdsJH4SvJnNyekxako= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561081710214549.0026741391587; Thu, 20 Jun 2019 18:48:30 -0700 (PDT) Received: from localhost ([::1]:54038 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he8f5-00009q-Pp for importer@patchew.org; Thu, 20 Jun 2019 21:48:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40741) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he8Zc-0006NK-RD for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:42:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1he8ZZ-00068o-AH for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:42:40 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:55299) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1he8ZY-00063q-OK for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:42:37 -0400 Received: by mail-wm1-x333.google.com with SMTP id a15so4783387wmj.5 for ; Thu, 20 Jun 2019 18:42:36 -0700 (PDT) Received: from 640k.lan ([93.56.166.5]) by smtp.gmail.com with ESMTPSA id d1sm1123125wru.41.2019.06.20.18.42.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Jun 2019 18:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=jRxVFuHpbr4EI8miJwJfPa6C/23qivxTRXPqmbxVszk=; b=SegDEA2Kis2UXGq82hZuCEsGldAWjiXXkdsmGJMjCbjnGKC2s2zchOnreAdo0wpJgH H7vVaHG2Wc+/VyPYKoGue/QaTAmP+8lC7ED1n8i/snRUCnQrxggmMbETAivbCjZP+iGf MVrS3ZOF79Zm4kjnM4j//qXBk9zEcPD3rJ/euR+rxy2tYSZDYaA4u08fHEV/j4FnWH1P rmq+uc5XmuHc3cyqSXk9lknwFcJWo3kHvkNgQaH2R2Wd7MIb8VZ2CJXjB8VO51lWCWWQ eeCA1Kgsd3otQnCccoxz2xJpAgzPkijh1T7Fx/1ltqUJ/VEfXuU6zLBuCxx9PrsWZBaX yoJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=jRxVFuHpbr4EI8miJwJfPa6C/23qivxTRXPqmbxVszk=; b=pIblYlyacLRv0cyB6aeHtYIn5Imb+UXNNNKMM8M0Dzt9SLEu7PrEixPFYnpcv+HSiJ eFbQhk4kqsFE7aPyBTprYsHzHglfWuURfBBdsvR2L6R61wPQCxtftugjSjK6pTqBqi1Q yNqU8p34fVxOkJd063NaOrqgTgQAcp6MiuDojm5d7qPTTUuxGLCFkbkxTFJ5HSieGITX UN9lLHl18MbYSbAzsRHLTiPJV3wKpabSDsalCbfoK0Xenm53Nwoc4b46JnaQapPdMj8U j4bgn5l8Zqt/U/x5399o0mjhuvNezSJdVbveEVf/pup5tYC20zK/6gNFhMyGAF5V2DoP VMXA== X-Gm-Message-State: APjAAAUT+MP2hwuuOe8Km2G31VoP6BpNGWXiN7oIC3agZq+025hPBx+g nhsmyQ/1Jkzl+bmUxRb/qYTf0IrJ X-Google-Smtp-Source: APXvYqxx/EjKtpQt8Q+UpkrZUXSw4t7g0NVuEg85MQbZLiVa0Yk1xzG8KuA/DQzrhdMFCitm31zJIw== X-Received: by 2002:a1c:2e16:: with SMTP id u22mr1507314wmu.80.1561081354771; Thu, 20 Jun 2019 18:42:34 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:08 +0200 Message-Id: <1561081350-3723-4-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 Subject: [Qemu-devel] [PULL 03/25] i386/kvm: convert hyperv enlightenments properties from bools to bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Representing Hyper-V properties as bits will allow us to check features and dependencies between them in a natural way. Suggested-by: Roman Kagan Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-2-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 3 +- target/i386/cpu.c | 44 ++++++++++++++++++--------- target/i386/cpu.h | 37 ++++++++++++++--------- target/i386/hyperv.c | 2 +- target/i386/kvm.c | 83 +++++++++++++++++++++--------------------------= ---- target/i386/machine.c | 2 +- 6 files changed, 91 insertions(+), 80 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2c5446b..e41192b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2386,7 +2386,8 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, } cpu->thread_id =3D topo.smt_id; =20 - if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && + !kvm_hv_vpindex_settable()) { error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); return; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fbed2eb..e90c1ac 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5853,21 +5853,37 @@ static Property x86_cpu_properties[] =3D { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), + { .name =3D "hv-spinlocks", .info =3D &qdev_prop_spinlocks }, - DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false), - DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false), - DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false), - DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false), - DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false), - DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), - DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false), - DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false), - DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false), - DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false), - DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment,= false), - DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false), - DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false), - DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false), + DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, + HYPERV_FEAT_RELAXED, 0), + DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, + HYPERV_FEAT_VAPIC, 0), + DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, + HYPERV_FEAT_TIME, 0), + DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, + HYPERV_FEAT_CRASH, 0), + DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, + HYPERV_FEAT_RESET, 0), + DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, + HYPERV_FEAT_VPINDEX, 0), + DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, + HYPERV_FEAT_RUNTIME, 0), + DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, + HYPERV_FEAT_SYNIC, 0), + DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, + HYPERV_FEAT_STIMER, 0), + DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, + HYPERV_FEAT_FREQUENCIES, 0), + DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, + HYPERV_FEAT_REENLIGHTENMENT, 0), + DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, + HYPERV_FEAT_TLBFLUSH, 0), + DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, + HYPERV_FEAT_EVMCS, 0), + DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, + HYPERV_FEAT_IPI, 0), + DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0732e05..30cd1a0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -734,6 +734,22 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) =20 +/* Supported Hyper-V Enlightenments */ +#define HYPERV_FEAT_RELAXED 0 +#define HYPERV_FEAT_VAPIC 1 +#define HYPERV_FEAT_TIME 2 +#define HYPERV_FEAT_CRASH 3 +#define HYPERV_FEAT_RESET 4 +#define HYPERV_FEAT_VPINDEX 5 +#define HYPERV_FEAT_RUNTIME 6 +#define HYPERV_FEAT_SYNIC 7 +#define HYPERV_FEAT_STIMER 8 +#define HYPERV_FEAT_FREQUENCIES 9 +#define HYPERV_FEAT_REENLIGHTENMENT 10 +#define HYPERV_FEAT_TLBFLUSH 11 +#define HYPERV_FEAT_EVMCS 12 +#define HYPERV_FEAT_IPI 13 + #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF #endif @@ -1370,23 +1386,11 @@ struct X86CPU { CPUNegativeOffsetState neg; CPUX86State env; =20 - bool hyperv_vapic; - bool hyperv_relaxed_timing; int hyperv_spinlock_attempts; char *hyperv_vendor_id; - bool hyperv_time; - bool hyperv_crash; - bool hyperv_reset; - bool hyperv_vpindex; - bool hyperv_runtime; - bool hyperv_synic; bool hyperv_synic_kvm_only; - bool hyperv_stimer; - bool hyperv_frequencies; - bool hyperv_reenlightenment; - bool hyperv_tlbflush; - bool hyperv_evmcs; - bool hyperv_ipi; + uint64_t hyperv_features; + bool check_cpuid; bool enforce_cpuid; bool expose_kvm; @@ -1906,4 +1910,9 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86X= SaveArea *buf); void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); void x86_update_hflags(CPUX86State* env); =20 +static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) +{ + return !!(cpu->hyperv_features & BIT(feat)); +} + #endif /* I386_CPU_H */ diff --git a/target/i386/hyperv.c b/target/i386/hyperv.c index b264a28..26efc1e 100644 --- a/target/i386/hyperv.c +++ b/target/i386/hyperv.c @@ -52,7 +52,7 @@ int kvm_hv_handle_exit(X86CPU *cpu, struct kvm_hyperv_exi= t *exit) =20 switch (exit->type) { case KVM_EXIT_HYPERV_SYNIC: - if (!cpu->hyperv_synic) { + if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { return -1; } =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6899061..b34eb81 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -634,28 +634,12 @@ unsigned long kvm_arch_vcpu_id(CPUState *cs) #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 #endif =20 -static bool hyperv_hypercall_available(X86CPU *cpu) -{ - return cpu->hyperv_vapic || - (cpu->hyperv_spinlock_attempts !=3D HYPERV_SPINLOCK_NEVER_RETRY= ); -} - static bool hyperv_enabled(X86CPU *cpu) { CPUState *cs =3D CPU(cpu); return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && - (hyperv_hypercall_available(cpu) || - cpu->hyperv_time || - cpu->hyperv_relaxed_timing || - cpu->hyperv_crash || - cpu->hyperv_reset || - cpu->hyperv_vpindex || - cpu->hyperv_runtime || - cpu->hyperv_synic || - cpu->hyperv_stimer || - cpu->hyperv_reenlightenment || - cpu->hyperv_tlbflush || - cpu->hyperv_ipi); + ((cpu->hyperv_spinlock_attempts !=3D HYPERV_SPINLOCK_NEVER_RETRY) = || + cpu->hyperv_features); } =20 static int kvm_arch_set_tsc_khz(CPUState *cs) @@ -704,14 +688,14 @@ static int hyperv_handle_properties(CPUState *cs) X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 - if (cpu->hyperv_relaxed_timing) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) { env->features[FEAT_HYPERV_EAX] |=3D HV_HYPERCALL_AVAILABLE; } - if (cpu->hyperv_vapic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { env->features[FEAT_HYPERV_EAX] |=3D HV_HYPERCALL_AVAILABLE; env->features[FEAT_HYPERV_EAX] |=3D HV_APIC_ACCESS_AVAILABLE; } - if (cpu->hyperv_time) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <=3D 0= ) { fprintf(stderr, "Hyper-V clocksources " "(requested by 'hv-time' cpu flag) " @@ -722,7 +706,7 @@ static int hyperv_handle_properties(CPUState *cs) env->features[FEAT_HYPERV_EAX] |=3D HV_TIME_REF_COUNT_AVAILABLE; env->features[FEAT_HYPERV_EAX] |=3D HV_REFERENCE_TSC_AVAILABLE; } - if (cpu->hyperv_frequencies) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_FREQUENCIES)) { if (!has_msr_hv_frequencies) { fprintf(stderr, "Hyper-V frequency MSRs " "(requested by 'hv-frequencies' cpu flag) " @@ -732,7 +716,7 @@ static int hyperv_handle_properties(CPUState *cs) env->features[FEAT_HYPERV_EAX] |=3D HV_ACCESS_FREQUENCY_MSRS; env->features[FEAT_HYPERV_EDX] |=3D HV_FREQUENCY_MSRS_AVAILABLE; } - if (cpu->hyperv_crash) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_CRASH)) { if (!has_msr_hv_crash) { fprintf(stderr, "Hyper-V crash MSRs " "(requested by 'hv-crash' cpu flag) " @@ -741,7 +725,7 @@ static int hyperv_handle_properties(CPUState *cs) } env->features[FEAT_HYPERV_EDX] |=3D HV_GUEST_CRASH_MSR_AVAILABLE; } - if (cpu->hyperv_reenlightenment) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { if (!has_msr_hv_reenlightenment) { fprintf(stderr, "Hyper-V Reenlightenment MSRs " @@ -752,7 +736,7 @@ static int hyperv_handle_properties(CPUState *cs) env->features[FEAT_HYPERV_EAX] |=3D HV_ACCESS_REENLIGHTENMENTS_CON= TROL; } env->features[FEAT_HYPERV_EDX] |=3D HV_CPU_DYNAMIC_PARTITIONING_AVAILA= BLE; - if (cpu->hyperv_reset) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RESET)) { if (!has_msr_hv_reset) { fprintf(stderr, "Hyper-V reset MSR " "(requested by 'hv-reset' cpu flag) " @@ -761,7 +745,7 @@ static int hyperv_handle_properties(CPUState *cs) } env->features[FEAT_HYPERV_EAX] |=3D HV_RESET_AVAILABLE; } - if (cpu->hyperv_vpindex) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { if (!has_msr_hv_vpindex) { fprintf(stderr, "Hyper-V VP_INDEX MSR " "(requested by 'hv-vpindex' cpu flag) " @@ -770,7 +754,7 @@ static int hyperv_handle_properties(CPUState *cs) } env->features[FEAT_HYPERV_EAX] |=3D HV_VP_INDEX_AVAILABLE; } - if (cpu->hyperv_runtime) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { if (!has_msr_hv_runtime) { fprintf(stderr, "Hyper-V VP_RUNTIME MSR " "(requested by 'hv-runtime' cpu flag) " @@ -779,10 +763,10 @@ static int hyperv_handle_properties(CPUState *cs) } env->features[FEAT_HYPERV_EAX] |=3D HV_VP_RUNTIME_AVAILABLE; } - if (cpu->hyperv_synic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { unsigned int cap =3D KVM_CAP_HYPERV_SYNIC; if (!cpu->hyperv_synic_kvm_only) { - if (!cpu->hyperv_vpindex) { + if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { fprintf(stderr, "Hyper-V SynIC " "(requested by 'hv-synic' cpu flag) " "requires Hyper-V VP_INDEX ('hv-vpindex')\n"); @@ -799,20 +783,20 @@ static int hyperv_handle_properties(CPUState *cs) =20 env->features[FEAT_HYPERV_EAX] |=3D HV_SYNIC_AVAILABLE; } - if (cpu->hyperv_stimer) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER)) { if (!has_msr_hv_stimer) { fprintf(stderr, "Hyper-V timers aren't supported by kernel\n"); return -ENOSYS; } env->features[FEAT_HYPERV_EAX] |=3D HV_SYNTIMERS_AVAILABLE; } - if (cpu->hyperv_relaxed_timing) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) { env->features[FEAT_HV_RECOMM_EAX] |=3D HV_RELAXED_TIMING_RECOMMEND= ED; } - if (cpu->hyperv_vapic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { env->features[FEAT_HV_RECOMM_EAX] |=3D HV_APIC_ACCESS_RECOMMENDED; } - if (cpu->hyperv_tlbflush) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TLBFLUSH)) { if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TLBFLUSH) <=3D 0) { fprintf(stderr, "Hyper-V TLB flush support " @@ -823,7 +807,7 @@ static int hyperv_handle_properties(CPUState *cs) env->features[FEAT_HV_RECOMM_EAX] |=3D HV_REMOTE_TLB_FLUSH_RECOMME= NDED; env->features[FEAT_HV_RECOMM_EAX] |=3D HV_EX_PROCESSOR_MASKS_RECOM= MENDED; } - if (cpu->hyperv_ipi) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_IPI)) { if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_SEND_IPI) <=3D 0) { fprintf(stderr, "Hyper-V IPI send support " @@ -834,7 +818,7 @@ static int hyperv_handle_properties(CPUState *cs) env->features[FEAT_HV_RECOMM_EAX] |=3D HV_CLUSTER_IPI_RECOMMENDED; env->features[FEAT_HV_RECOMM_EAX] |=3D HV_EX_PROCESSOR_MASKS_RECOM= MENDED; } - if (cpu->hyperv_evmcs) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { uint16_t evmcs_version; =20 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, @@ -856,7 +840,7 @@ static int hyperv_init_vcpu(X86CPU *cpu) CPUState *cs =3D CPU(cpu); int ret; =20 - if (cpu->hyperv_vpindex && !hv_vpindex_settable) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_setta= ble) { /* * the kernel doesn't support setting vp_index; assert that its va= lue * is in sync @@ -881,7 +865,7 @@ static int hyperv_init_vcpu(X86CPU *cpu) } } =20 - if (cpu->hyperv_synic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { uint32_t synic_cap =3D cpu->hyperv_synic_kvm_only ? KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; ret =3D kvm_vcpu_enable_cap(cs, synic_cap, 0); @@ -972,7 +956,7 @@ int kvm_arch_init_vcpu(CPUState *cs) memset(signature, 0, 12); memcpy(signature, cpu->hyperv_vendor_id, len); } - c->eax =3D cpu->hyperv_evmcs ? + c->eax =3D hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; c->ebx =3D signature[0]; c->ecx =3D signature[1]; @@ -1016,7 +1000,7 @@ int kvm_arch_init_vcpu(CPUState *cs) kvm_base =3D KVM_CPUID_SIGNATURE_NEXT; has_msr_hv_hypercall =3D true; =20 - if (cpu->hyperv_evmcs) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { __u32 function; =20 /* Create zeroed 0x40000006..0x40000009 leaves */ @@ -1360,7 +1344,7 @@ void kvm_arch_reset_vcpu(X86CPU *cpu) env->mp_state =3D KVM_MP_STATE_RUNNABLE; } =20 - if (cpu->hyperv_synic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { int i; for (i =3D 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { env->msr_hv_synic_sint[i] =3D HV_SINT_MASKED; @@ -2100,11 +2084,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, env->msr_hv_hypercall); } - if (cpu->hyperv_time) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc); } - if (cpu->hyperv_reenlightenment) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, env->msr_hv_reenlightenment_control); kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, @@ -2113,7 +2097,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_hv_tsc_emulation_status); } } - if (cpu->hyperv_vapic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, env->msr_hv_vapic); } @@ -2129,11 +2113,12 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_hv_runtime) { kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runt= ime); } - if (cpu->hyperv_vpindex && hv_vpindex_settable) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) + && hv_vpindex_settable) { kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, hyperv_vp_index(CPU(cpu))); } - if (cpu->hyperv_synic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { int j; =20 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION); @@ -2473,13 +2458,13 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0); kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0); } - if (cpu->hyperv_vapic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0); } - if (cpu->hyperv_time) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0); } - if (cpu->hyperv_reenlightenment) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0); kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0); kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0); @@ -2494,7 +2479,7 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_hv_runtime) { kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0); } - if (cpu->hyperv_synic) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { uint32_t msr; =20 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0); diff --git a/target/i386/machine.c b/target/i386/machine.c index 4aff1a7..a39ce7f 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -634,7 +634,7 @@ static bool hyperv_runtime_enable_needed(void *opaque) X86CPU *cpu =3D opaque; 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Thu, 20 Jun 2019 18:42:36 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:09 +0200 Message-Id: <1561081350-3723-5-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 04/25] i386/kvm: add support for KVM_GET_SUPPORTED_HV_CPUID X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov KVM now supports reporting supported Hyper-V features through CPUID (KVM_GET_SUPPORTED_HV_CPUID ioctl). Going forward, this is going to be the only way to announce new functionality and this has already happened with Direct Mode stimers. While we could just support KVM_GET_SUPPORTED_HV_CPUID for new features, it seems to be beneficial to use it for all Hyper-V enlightenments when possible. This way we can implement 'hv-all' pass-through mode giving the guest all supported Hyper-V features even when QEMU knows nothing about them. Implementation-wise we create a new kvm_hyperv_properties structure defining Hyper-V features, get_supported_hv_cpuid()/ get_supported_hv_cpuid_legacy() returning the supported CPUID set and a bit over-engineered hv_cpuid_check_and_set() which we will also be used to set cpu->hyperv_* properties for 'hv-all' mode. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-3-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 474 ++++++++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 356 insertions(+), 118 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index b34eb81..cd492d4 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -683,156 +683,394 @@ static bool tsc_is_stable_and_known(CPUX86State *en= v) || env->user_tsc_khz; } =20 -static int hyperv_handle_properties(CPUState *cs) +static struct { + const char *desc; + struct { + uint32_t fw; + uint32_t bits; + } flags[2]; +} kvm_hyperv_properties[] =3D { + [HYPERV_FEAT_RELAXED] =3D { + .desc =3D "relaxed timing (hv-relaxed)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_HYPERCALL_AVAILABLE}, + {.fw =3D FEAT_HV_RECOMM_EAX, + .bits =3D HV_RELAXED_TIMING_RECOMMENDED} + } + }, + [HYPERV_FEAT_VAPIC] =3D { + .desc =3D "virtual APIC (hv-vapic)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE}, + {.fw =3D FEAT_HV_RECOMM_EAX, + .bits =3D HV_APIC_ACCESS_RECOMMENDED} + } + }, + [HYPERV_FEAT_TIME] =3D { + .desc =3D "clocksources (hv-time)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABL= E | + HV_REFERENCE_TSC_AVAILABLE} + } + }, + [HYPERV_FEAT_CRASH] =3D { + .desc =3D "crash MSRs (hv-crash)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EDX, + .bits =3D HV_GUEST_CRASH_MSR_AVAILABLE} + } + }, + [HYPERV_FEAT_RESET] =3D { + .desc =3D "reset MSR (hv-reset)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_RESET_AVAILABLE} + } + }, + [HYPERV_FEAT_VPINDEX] =3D { + .desc =3D "VP_INDEX MSR (hv-vpindex)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_VP_INDEX_AVAILABLE} + } + }, + [HYPERV_FEAT_RUNTIME] =3D { + .desc =3D "VP_RUNTIME MSR (hv-runtime)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_VP_RUNTIME_AVAILABLE} + } + }, + [HYPERV_FEAT_SYNIC] =3D { + .desc =3D "synthetic interrupt controller (hv-synic)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_SYNIC_AVAILABLE} + } + }, + [HYPERV_FEAT_STIMER] =3D { + .desc =3D "synthetic timers (hv-stimer)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_SYNTIMERS_AVAILABLE} + } + }, + [HYPERV_FEAT_FREQUENCIES] =3D { + .desc =3D "frequency MSRs (hv-frequencies)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_ACCESS_FREQUENCY_MSRS}, + {.fw =3D FEAT_HYPERV_EDX, + .bits =3D HV_FREQUENCY_MSRS_AVAILABLE} + } + }, + [HYPERV_FEAT_REENLIGHTENMENT] =3D { + .desc =3D "reenlightenment MSRs (hv-reenlightenment)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EAX, + .bits =3D HV_ACCESS_REENLIGHTENMENTS_CONTROL} + } + }, + [HYPERV_FEAT_TLBFLUSH] =3D { + .desc =3D "paravirtualized TLB flush (hv-tlbflush)", + .flags =3D { + {.fw =3D FEAT_HV_RECOMM_EAX, + .bits =3D HV_REMOTE_TLB_FLUSH_RECOMMENDED | + HV_EX_PROCESSOR_MASKS_RECOMMENDED} + } + }, + [HYPERV_FEAT_EVMCS] =3D { + .desc =3D "enlightened VMCS (hv-evmcs)", + .flags =3D { + {.fw =3D FEAT_HV_RECOMM_EAX, + .bits =3D HV_ENLIGHTENED_VMCS_RECOMMENDED} + } + }, + [HYPERV_FEAT_IPI] =3D { + .desc =3D "paravirtualized IPI (hv-ipi)", + .flags =3D { + {.fw =3D FEAT_HV_RECOMM_EAX, + .bits =3D HV_CLUSTER_IPI_RECOMMENDED | + HV_EX_PROCESSOR_MASKS_RECOMMENDED} + } + }, +}; + +static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max) +{ + struct kvm_cpuid2 *cpuid; + int r, size; + + size =3D sizeof(*cpuid) + max * sizeof(*cpuid->entries); + cpuid =3D g_malloc0(size); + cpuid->nent =3D max; + + r =3D kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid); + if (r =3D=3D 0 && cpuid->nent >=3D max) { + r =3D -E2BIG; + } + if (r < 0) { + if (r =3D=3D -E2BIG) { + g_free(cpuid); + return NULL; + } else { + fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n", + strerror(-r)); + exit(1); + } + } + return cpuid; +} + +/* + * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough + * for all entries. + */ +static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs) +{ + struct kvm_cpuid2 *cpuid; + int max =3D 7; /* 0x40000000..0x40000005, 0x4000000A */ + + /* + * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with + * -E2BIG, however, it doesn't report back the right size. Keep increa= sing + * it and re-trying until we succeed. + */ + while ((cpuid =3D try_get_hv_cpuid(cs, max)) =3D=3D NULL) { + max++; + } + return cpuid; +} + +/* + * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature + * leaves from KVM_CAP_HYPERV* and present MSRs data. + */ +static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + struct kvm_cpuid2 *cpuid; + struct kvm_cpuid_entry2 *entry_feat, *entry_recomm; + + /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */ + cpuid =3D g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries)); + cpuid->nent =3D 2; + + /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */ + entry_feat =3D &cpuid->entries[0]; + entry_feat->function =3D HV_CPUID_FEATURES; =20 - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) { - env->features[FEAT_HYPERV_EAX] |=3D HV_HYPERCALL_AVAILABLE; + entry_recomm =3D &cpuid->entries[1]; + entry_recomm->function =3D HV_CPUID_ENLIGHTMENT_INFO; + entry_recomm->ebx =3D cpu->hyperv_spinlock_attempts; + + if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) { + entry_feat->eax |=3D HV_HYPERCALL_AVAILABLE; + entry_feat->eax |=3D HV_APIC_ACCESS_AVAILABLE; + entry_feat->edx |=3D HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; + entry_recomm->eax |=3D HV_RELAXED_TIMING_RECOMMENDED; + entry_recomm->eax |=3D HV_APIC_ACCESS_RECOMMENDED; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { - env->features[FEAT_HYPERV_EAX] |=3D HV_HYPERCALL_AVAILABLE; - env->features[FEAT_HYPERV_EAX] |=3D HV_APIC_ACCESS_AVAILABLE; + + if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { + entry_feat->eax |=3D HV_TIME_REF_COUNT_AVAILABLE; + entry_feat->eax |=3D HV_REFERENCE_TSC_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { - if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <=3D 0= ) { - fprintf(stderr, "Hyper-V clocksources " - "(requested by 'hv-time' cpu flag) " - "are not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_HYPERCALL_AVAILABLE; - env->features[FEAT_HYPERV_EAX] |=3D HV_TIME_REF_COUNT_AVAILABLE; - env->features[FEAT_HYPERV_EAX] |=3D HV_REFERENCE_TSC_AVAILABLE; + + if (has_msr_hv_frequencies) { + entry_feat->eax |=3D HV_ACCESS_FREQUENCY_MSRS; + entry_feat->edx |=3D HV_FREQUENCY_MSRS_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_FREQUENCIES)) { - if (!has_msr_hv_frequencies) { - fprintf(stderr, "Hyper-V frequency MSRs " - "(requested by 'hv-frequencies' cpu flag) " - "are not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_ACCESS_FREQUENCY_MSRS; - env->features[FEAT_HYPERV_EDX] |=3D HV_FREQUENCY_MSRS_AVAILABLE; + + if (has_msr_hv_crash) { + entry_feat->edx |=3D HV_GUEST_CRASH_MSR_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_CRASH)) { - if (!has_msr_hv_crash) { - fprintf(stderr, "Hyper-V crash MSRs " - "(requested by 'hv-crash' cpu flag) " - "are not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EDX] |=3D HV_GUEST_CRASH_MSR_AVAILABLE; + + if (has_msr_hv_reenlightenment) { + entry_feat->eax |=3D HV_ACCESS_REENLIGHTENMENTS_CONTROL; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { - if (!has_msr_hv_reenlightenment) { - fprintf(stderr, - "Hyper-V Reenlightenment MSRs " - "(requested by 'hv-reenlightenment' cpu flag) " - "are not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_ACCESS_REENLIGHTENMENTS_CON= TROL; + + if (has_msr_hv_reset) { + entry_feat->eax |=3D HV_RESET_AVAILABLE; } - env->features[FEAT_HYPERV_EDX] |=3D HV_CPU_DYNAMIC_PARTITIONING_AVAILA= BLE; - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RESET)) { - if (!has_msr_hv_reset) { - fprintf(stderr, "Hyper-V reset MSR " - "(requested by 'hv-reset' cpu flag) " - "is not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_RESET_AVAILABLE; + + if (has_msr_hv_vpindex) { + entry_feat->eax |=3D HV_VP_INDEX_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { - if (!has_msr_hv_vpindex) { - fprintf(stderr, "Hyper-V VP_INDEX MSR " - "(requested by 'hv-vpindex' cpu flag) " - "is not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_VP_INDEX_AVAILABLE; + + if (has_msr_hv_runtime) { + entry_feat->eax |=3D HV_VP_RUNTIME_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { - if (!has_msr_hv_runtime) { - fprintf(stderr, "Hyper-V VP_RUNTIME MSR " - "(requested by 'hv-runtime' cpu flag) " - "is not supported by kernel\n"); - return -ENOSYS; + + if (has_msr_hv_synic) { + unsigned int cap =3D cpu->hyperv_synic_kvm_only ? + KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; + + if (kvm_check_extension(cs->kvm_state, cap) > 0) { + entry_feat->eax |=3D HV_SYNIC_AVAILABLE; } - env->features[FEAT_HYPERV_EAX] |=3D HV_VP_RUNTIME_AVAILABLE; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { - unsigned int cap =3D KVM_CAP_HYPERV_SYNIC; - if (!cpu->hyperv_synic_kvm_only) { - if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { - fprintf(stderr, "Hyper-V SynIC " - "(requested by 'hv-synic' cpu flag) " - "requires Hyper-V VP_INDEX ('hv-vpindex')\n"); - return -ENOSYS; - } - cap =3D KVM_CAP_HYPERV_SYNIC2; - } =20 - if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap))= { - fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu fl= ag) " - "is not supported by kernel\n"); - return -ENOSYS; - } + if (has_msr_hv_stimer) { + entry_feat->eax |=3D HV_SYNTIMERS_AVAILABLE; + } =20 - env->features[FEAT_HYPERV_EAX] |=3D HV_SYNIC_AVAILABLE; + if (kvm_check_extension(cs->kvm_state, + KVM_CAP_HYPERV_TLBFLUSH) > 0) { + entry_recomm->eax |=3D HV_REMOTE_TLB_FLUSH_RECOMMENDED; + entry_recomm->eax |=3D HV_EX_PROCESSOR_MASKS_RECOMMENDED; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER)) { - if (!has_msr_hv_stimer) { - fprintf(stderr, "Hyper-V timers aren't supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HYPERV_EAX] |=3D HV_SYNTIMERS_AVAILABLE; + + if (kvm_check_extension(cs->kvm_state, + KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { + entry_recomm->eax |=3D HV_ENLIGHTENED_VMCS_RECOMMENDED; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) { - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_RELAXED_TIMING_RECOMMEND= ED; + + if (kvm_check_extension(cs->kvm_state, + KVM_CAP_HYPERV_SEND_IPI) > 0) { + entry_recomm->eax |=3D HV_CLUSTER_IPI_RECOMMENDED; + entry_recomm->eax |=3D HV_EX_PROCESSOR_MASKS_RECOMMENDED; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_APIC_ACCESS_RECOMMENDED; - } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TLBFLUSH)) { - if (kvm_check_extension(cs->kvm_state, - KVM_CAP_HYPERV_TLBFLUSH) <=3D 0) { - fprintf(stderr, "Hyper-V TLB flush support " - "(requested by 'hv-tlbflush' cpu flag) " - " is not supported by kernel\n"); - return -ENOSYS; - } - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_REMOTE_TLB_FLUSH_RECOMME= NDED; - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_EX_PROCESSOR_MASKS_RECOM= MENDED; + + return cpuid; +} + +static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r) +{ + struct kvm_cpuid_entry2 *entry; + uint32_t func; + int reg; + + switch (fw) { + case FEAT_HYPERV_EAX: + reg =3D R_EAX; + func =3D HV_CPUID_FEATURES; + break; + case FEAT_HYPERV_EDX: + reg =3D R_EDX; + func =3D HV_CPUID_FEATURES; + break; + case FEAT_HV_RECOMM_EAX: + reg =3D R_EAX; + func =3D HV_CPUID_ENLIGHTMENT_INFO; + break; + default: + return -EINVAL; } - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_IPI)) { - if (kvm_check_extension(cs->kvm_state, - KVM_CAP_HYPERV_SEND_IPI) <=3D 0) { - fprintf(stderr, "Hyper-V IPI send support " - "(requested by 'hv-ipi' cpu flag) " - " is not supported by kernel\n"); - return -ENOSYS; + + entry =3D cpuid_find_entry(cpuid, func, 0); + if (!entry) { + return -ENOENT; + } + + switch (reg) { + case R_EAX: + *r =3D entry->eax; + break; + case R_EDX: + *r =3D entry->edx; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid, + int feature) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + uint32_t r, fw, bits;; + int i; + + if (!hyperv_feat_enabled(cpu, feature)) { + return 0; + } + + for (i =3D 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i+= +) { + fw =3D kvm_hyperv_properties[feature].flags[i].fw; + bits =3D kvm_hyperv_properties[feature].flags[i].bits; + + if (!fw) { + continue; } - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_CLUSTER_IPI_RECOMMENDED; - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_EX_PROCESSOR_MASKS_RECOM= MENDED; + + if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) !=3D bits) { + fprintf(stderr, + "Hyper-V %s is not supported by kernel\n", + kvm_hyperv_properties[feature].desc); + return 1; + } + + env->features[fw] |=3D bits; } + + return 0; +} + +static int hyperv_handle_properties(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + struct kvm_cpuid2 *cpuid; + int r =3D 0; + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { uint16_t evmcs_version; =20 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, (uintptr_t)&evmcs_version)) { - fprintf(stderr, "Hyper-V Enlightened VMCS " - "(requested by 'hv-evmcs' cpu flag) " - "is not supported by kernel\n"); + fprintf(stderr, "Hyper-V %s is not supported by kernel\n", + kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); return -ENOSYS; } env->features[FEAT_HV_RECOMM_EAX] |=3D HV_ENLIGHTENED_VMCS_RECOMME= NDED; env->features[FEAT_HV_NESTED_EAX] =3D evmcs_version; } =20 - return 0; + if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { + cpuid =3D get_supported_hv_cpuid(cs); + } else { + cpuid =3D get_supported_hv_cpuid_legacy(cs); + } + + /* Features */ + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI); + + /* Dependencies */ + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && + !cpu->hyperv_synic_kvm_only && + !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { + fprintf(stderr, "Hyper-V %s requires %s\n", + kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, + kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); + r |=3D 1; + } + + /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ + env->features[FEAT_HYPERV_EDX] |=3D HV_CPU_DYNAMIC_PARTITIONING_AVAILA= BLE; + + g_free(cpuid); + + return r ? -ENOSYS : 0; } =20 static int hyperv_init_vcpu(X86CPU *cpu) --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 05/25] i386/kvm: move Hyper-V CPUID filling to hyperv_handle_properties() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Let's consolidate Hyper-V features handling in hyperv_handle_properties(). The change is necessary to support 'hv-passthrough' mode as we'll be just copying CPUIDs from KVM instead of filling them in. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-4-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 163 ++++++++++++++++++++++++++++++--------------------= ---- 1 file changed, 90 insertions(+), 73 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index cd492d4..a041b4d 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1013,13 +1013,25 @@ static int hv_cpuid_check_and_set(CPUState *cs, str= uct kvm_cpuid2 *cpuid, return 0; } =20 -static int hyperv_handle_properties(CPUState *cs) +/* + * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_e= nt in + * case of success, errno < 0 in case of failure and 0 when no Hyper-V + * extentions are enabled. + */ +static int hyperv_handle_properties(CPUState *cs, + struct kvm_cpuid_entry2 *cpuid_ent) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; struct kvm_cpuid2 *cpuid; + struct kvm_cpuid_entry2 *c; + uint32_t signature[3]; + uint32_t cpuid_i =3D 0; int r =3D 0; =20 + if (!hyperv_enabled(cpu)) + return 0; + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { uint16_t evmcs_version; =20 @@ -1068,9 +1080,80 @@ static int hyperv_handle_properties(CPUState *cs) /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ env->features[FEAT_HYPERV_EDX] |=3D HV_CPU_DYNAMIC_PARTITIONING_AVAILA= BLE; =20 + if (r) { + r =3D -ENOSYS; + goto free; + } + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; + if (!cpu->hyperv_vendor_id) { + memcpy(signature, "Microsoft Hv", 12); + } else { + size_t len =3D strlen(cpu->hyperv_vendor_id); + + if (len > 12) { + error_report("hv-vendor-id truncated to 12 characters"); + len =3D 12; + } + memset(signature, 0, 12); + memcpy(signature, cpu->hyperv_vendor_id, len); + } + c->eax =3D hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? + HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; + c->ebx =3D signature[0]; + c->ecx =3D signature[1]; + c->edx =3D signature[2]; + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_INTERFACE; + memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); + c->eax =3D signature[0]; + c->ebx =3D 0; + c->ecx =3D 0; + c->edx =3D 0; + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_VERSION; + c->eax =3D 0x00001bbc; + c->ebx =3D 0x00060001; + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_FEATURES; + c->eax =3D env->features[FEAT_HYPERV_EAX]; + c->ebx =3D env->features[FEAT_HYPERV_EBX]; + c->edx =3D env->features[FEAT_HYPERV_EDX]; + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_ENLIGHTMENT_INFO; + c->eax =3D env->features[FEAT_HV_RECOMM_EAX]; + c->ebx =3D cpu->hyperv_spinlock_attempts; + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_IMPLEMENT_LIMITS; + c->eax =3D cpu->hv_max_vps; + c->ebx =3D 0x40; + + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { + __u32 function; + + /* Create zeroed 0x40000006..0x40000009 leaves */ + for (function =3D HV_CPUID_IMPLEMENT_LIMITS + 1; + function < HV_CPUID_NESTED_FEATURES; function++) { + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D function; + } + + c =3D &cpuid_ent[cpuid_i++]; + c->function =3D HV_CPUID_NESTED_FEATURES; + c->eax =3D env->features[FEAT_HV_NESTED_EAX]; + } + r =3D cpuid_i; + +free: g_free(cpuid); =20 - return r ? -ENOSYS : 0; + return r; } =20 static int hyperv_init_vcpu(X86CPU *cpu) @@ -1179,79 +1262,13 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 /* Paravirtualization CPUIDs */ - if (hyperv_enabled(cpu)) { - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; - if (!cpu->hyperv_vendor_id) { - memcpy(signature, "Microsoft Hv", 12); - } else { - size_t len =3D strlen(cpu->hyperv_vendor_id); - - if (len > 12) { - error_report("hv-vendor-id truncated to 12 characters"); - len =3D 12; - } - memset(signature, 0, 12); - memcpy(signature, cpu->hyperv_vendor_id, len); - } - c->eax =3D hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? - HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; - c->ebx =3D signature[0]; - c->ecx =3D signature[1]; - c->edx =3D signature[2]; - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_INTERFACE; - memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); - c->eax =3D signature[0]; - c->ebx =3D 0; - c->ecx =3D 0; - c->edx =3D 0; - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_VERSION; - c->eax =3D 0x00001bbc; - c->ebx =3D 0x00060001; - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_FEATURES; - r =3D hyperv_handle_properties(cs); - if (r) { - return r; - } - c->eax =3D env->features[FEAT_HYPERV_EAX]; - c->ebx =3D env->features[FEAT_HYPERV_EBX]; - c->edx =3D env->features[FEAT_HYPERV_EDX]; - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_ENLIGHTMENT_INFO; - - c->eax =3D env->features[FEAT_HV_RECOMM_EAX]; - c->ebx =3D cpu->hyperv_spinlock_attempts; - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_IMPLEMENT_LIMITS; - - c->eax =3D cpu->hv_max_vps; - c->ebx =3D 0x40; - + r =3D hyperv_handle_properties(cs, cpuid_data.entries); + if (r < 0) { + return r; + } else if (r > 0) { + cpuid_i =3D r; kvm_base =3D KVM_CPUID_SIGNATURE_NEXT; has_msr_hv_hypercall =3D true; - - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { - __u32 function; - - /* Create zeroed 0x40000006..0x40000009 leaves */ - for (function =3D HV_CPUID_IMPLEMENT_LIMITS + 1; - function < HV_CPUID_NESTED_FEATURES; function++) { - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D function; - } - - c =3D &cpuid_data.entries[cpuid_i++]; - c->function =3D HV_CPUID_NESTED_FEATURES; - c->eax =3D env->features[FEAT_HV_NESTED_EAX]; - } } =20 if (cpu->expose_kvm) { --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 06/25] i386/kvm: document existing Hyper-V enlightenments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Currently, there is no doc describing hv-* CPU flags, people are encouraged to get the information from Microsoft Hyper-V Top Level Functional specification (TLFS). There is, however, a bit of QEMU specifics. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-5-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- docs/hyperv.txt | 181 ++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 181 insertions(+) create mode 100644 docs/hyperv.txt diff --git a/docs/hyperv.txt b/docs/hyperv.txt new file mode 100644 index 0000000..c423e0f --- /dev/null +++ b/docs/hyperv.txt @@ -0,0 +1,181 @@ +Hyper-V Enlightenments +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + +1. Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In some cases when implementing a hardware interface in software is slow, = KVM +implements its own paravirtualized interfaces. This works well for Linux as +guest support for such features is added simultaneously with the feature i= tself. +It may, however, be hard-to-impossible to add support for these interfaces= to +proprietary OSes, namely, Microsoft Windows. + +KVM on x86 implements Hyper-V Enlightenments for Windows guests. These fea= tures +make Windows and Hyper-V guests think they're running on top of a Hyper-V +compatible hypervisor and use Hyper-V specific features. + + +2. Setup +=3D=3D=3D=3D=3D=3D=3D=3D=3D +No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In +QEMU, individual enlightenments can be enabled through CPU flags, e.g: + + qemu-system-x86_64 --enable-kvm --cpu host,hv_relaxed,hv_vpindex,hv_time= , ... + +Sometimes there are dependencies between enlightenments, QEMU is supposed = to +check that the supplied configuration is sane. + +When any set of the Hyper-V enlightenments is enabled, QEMU changes hyperv= isor +identification (CPUID 0x40000000..0x4000000A) to Hyper-V. KVM identificati= on +and features are kept in leaves 0x40000100..0x40000101. + + +3. Existing enlightenments +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +3.1. hv-relaxed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This feature tells guest OS to disable watchdog timeouts as it is running = on a +hypervisor. It is known that some Windows versions will do this even when = they +see 'hypervisor' CPU flag. + +3.2. hv-vapic +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides so-called VP Assist page MSR to guest allowing it to work with AP= IC +more efficiently. In particular, this enlightenment allows paravirtualized +(exit-less) EOI processing. + +3.3. hv-spinlocks=3Dxxx +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables paravirtualized spinlocks. The parameter indicates how many times +spinlock acquisition should be attempted before indicating the situation t= o the +hypervisor. A special value 0xffffffff indicates "never to retry". + +3.4. hv-vpindex +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides HV_X64_MSR_VP_INDEX (0x40000002) MSR to the guest which has Virtu= al +processor index information. This enlightenment makes sense in conjunction= with +hv-synic, hv-stimer and other enlightenments which require the guest to kn= ow its +Virtual Processor indices (e.g. when VP index needs to be passed in a +hypercall). + +3.5. hv-runtime +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides HV_X64_MSR_VP_RUNTIME (0x40000010) MSR to the guest. The MSR keep= s the +virtual processor run time in 100ns units. This gives guest operating syst= em an +idea of how much time was 'stolen' from it (when the virtual CPU was preem= pted +to perform some other work). + +3.6. hv-crash +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides HV_X64_MSR_CRASH_P0..HV_X64_MSR_CRASH_P5 (0x40000100..0x40000105)= and +HV_X64_MSR_CRASH_CTL (0x40000105) MSRs to the guest. These MSRs are writte= n to +by the guest when it crashes, HV_X64_MSR_CRASH_P0..HV_X64_MSR_CRASH_P5 MSRs +contain additional crash information. This information is outputted in QEM= U log +and through QAPI. +Note: unlike under genuine Hyper-V, write to HV_X64_MSR_CRASH_CTL causes g= uest +to shutdown. This effectively blocks crash dump generation by Windows. + +3.7. hv-time +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables two Hyper-V-specific clocksources available to the guest: MSR-based +Hyper-V clocksource (HV_X64_MSR_TIME_REF_COUNT, 0x40000020) and Reference = TSC +page (enabled via MSR HV_X64_MSR_REFERENCE_TSC, 0x40000021). Both clocksou= rces +are per-guest, Reference TSC page clocksource allows for exit-less time st= amp +readings. Using this enlightenment leads to significant speedup of all tim= estamp +related operations. + +3.8. hv-synic +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables Hyper-V Synthetic interrupt controller - an extension of a local A= PIC. +When enabled, this enlightenment provides additional communication facilit= ies +to the guest: SynIC messages and Events. This is a pre-requisite for +implementing VMBus devices (not yet in QEMU). Additionally, this enlighten= ment +is needed to enable Hyper-V synthetic timers. SynIC is controlled through = MSRs +HV_X64_MSR_SCONTROL..HV_X64_MSR_EOM (0x40000080..0x40000084) and +HV_X64_MSR_SINT0..HV_X64_MSR_SINT15 (0x40000090..0x4000009F) + +Requires: hv-vpindex + +3.9. hv-stimer +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables Hyper-V synthetic timers. There are four synthetic timers per virt= ual +CPU controlled through HV_X64_MSR_STIMER0_CONFIG..HV_X64_MSR_STIMER3_COUNT +(0x400000B0..0x400000B7) MSRs. These timers can work either in single-shot= or +periodic mode. It is known that certain Windows versions revert to using H= PET +(or even RTC when HPET is unavailable) extensively when this enlightenment= is +not provided; this can lead to significant CPU consumption, even when virt= ual +CPU is idle. + +Requires: hv-vpindex, hv-synic, hv-time + +3.10. hv-tlbflush +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables paravirtualized TLB shoot-down mechanism. On x86 architecture, rem= ote +TLB flush procedure requires sending IPIs and waiting for other CPUs to pe= rform +local TLB flush. In virtualized environment some virtual CPUs may not even= be +scheduled at the time of the call and may not require flushing (or, flushi= ng +may be postponed until the virtual CPU is scheduled). hv-tlbflush enlighte= nment +implements TLB shoot-down through hypervisor enabling the optimization. + +Requires: hv-vpindex + +3.11. hv-ipi +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Enables paravirtualized IPI send mechanism. HvCallSendSyntheticClusterIpi +hypercall may target more than 64 virtual CPUs simultaneously, doing the s= ame +through APIC requires more than one access (and thus exit to the hyperviso= r). + +Requires: hv-vpindex + +3.12. hv-vendor-id=3Dxxx +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This changes Hyper-V identification in CPUID 0x40000000.EBX-EDX from the d= efault +"Microsoft Hv". The parameter should be no longer than 12 characters. Acco= rding +to the specification, guests shouldn't use this information and it is unkn= own +if there is a Windows version which acts differently. +Note: hv-vendor-id is not an enlightenment and thus doesn't enable Hyper-V +identification when specified without some other enlightenment. + +3.13. hv-reset +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides HV_X64_MSR_RESET (0x40000003) MSR to the guest allowing it to res= et +itself by writing to it. Even when this MSR is enabled, it is not a recomm= ended +way for Windows to perform system reboot and thus it may not be used. + +3.14. hv-frequencies +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Provides HV_X64_MSR_TSC_FREQUENCY (0x40000022) and HV_X64_MSR_APIC_FREQUEN= CY +(0x40000023) allowing the guest to get its TSC/APIC frequencies without do= ing +measurements. + +3.15 hv-reenlightenment +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The enlightenment is nested specific, it targets Hyper-V on KVM guests. Wh= en +enabled, it provides HV_X64_MSR_REENLIGHTENMENT_CONTROL (0x40000106), +HV_X64_MSR_TSC_EMULATION_CONTROL (0x40000107)and HV_X64_MSR_TSC_EMULATION_= STATUS +(0x40000108) MSRs allowing the guest to get notified when TSC frequency ch= anges +(only happens on migration) and keep using old frequency (through emulatio= n in +the hypervisor) until it is ready to switch to the new one. This, in conju= nction +with hv-frequencies, allows Hyper-V on KVM to pass stable clocksource (Ref= erence +TSC page) to its own guests. + +Recommended: hv-frequencies + +3.16. hv-evmcs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The enlightenment is nested specific, it targets Hyper-V on KVM guests. Wh= en +enabled, it provides Enlightened VMCS feature to the guest. The feature +implements paravirtualized protocol between L0 (KVM) and L1 (Hyper-V) +hypervisors making L2 exits to the hypervisor faster. The feature is Intel= -only. +Note: some virtualization features (e.g. Posted Interrupts) are disabled w= hen +hv-evmcs is enabled. It may make sense to measure your nested workload wit= h and +without the feature to find out if enabling it is beneficial. + +Requires: hv-vapic + + +4. Useful links +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Hyper-V Top Level Functional specification and other information: +https://github.com/MicrosoftDocs/Virtualization-Documentation --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561082874; cv=none; d=zoho.com; s=zohoarc; b=DpKH9rbaLyA1Rhcortk1ch8dsUpRRHlOtYNUDxGsWFiggb8Dc0ZRNi/Hwzc72j2KRKpf99/S7FyeV6yUgqrY8Zs9afM8EJxXZZ8hjnpV4nv0MlR3FiHISAWeIUpAzvmE4OLF5qkwMZjqMIQ28wyEKnCvQy/1dNJmmh4yRtc3pss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561082874; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=rLWxEjPZN+ttDy6470/jW3LY13Gz8VOEZike0sn0oXQ=; b=HruLLHaZEsb+Sh4aiL53poOH7g+65F3LDOmmxrW7Toa2nco5tnXVSkGZZ1RAi8rQRTyHOnKv1kzPbOR5rbBPyStjwPMTj6lNUHWI1oiJeySIVGP5NokflWSnHT6bn4QBf4umUxmk3Um/OMSCa/qlVqXUldLttax57aDsEuhnljA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561082874260388.3533066255444; Thu, 20 Jun 2019 19:07:54 -0700 (PDT) Received: from localhost ([::1]:54128 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he8xz-0005yw-8h for importer@patchew.org; Thu, 20 Jun 2019 22:07:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41383) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he8a7-0006i9-Vj for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1he8a4-0006hZ-5n for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:11 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:35230) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1he8a3-0006H9-66 for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:07 -0400 Received: by mail-wm1-x32e.google.com with SMTP id c6so4929085wml.0 for ; Thu, 20 Jun 2019 18:42:41 -0700 (PDT) Received: from 640k.lan ([93.56.166.5]) by smtp.gmail.com with ESMTPSA id d1sm1123125wru.41.2019.06.20.18.42.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Jun 2019 18:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=rLWxEjPZN+ttDy6470/jW3LY13Gz8VOEZike0sn0oXQ=; b=TZZHIvtLm+DkuRRO2AQJKzG01U+Je1wC8UwFdiM+DaXQr1qnIwzu3xBJy93qXwlY1o WyboqPgRUgr1qIIKQdP4XDR/t88qM8h95n+DbSvOYDwIIJKmwrLFzIMnoOyJLgzi5/a5 HYuhiVTbXJW7cubRQFNsCK7uGU160ALpKOSNKJvNEmXNLobSxK2omSufOnMEo7jVVqo9 5s7J+TeEQPAU2SNQMlxSR5EmTgW2tTB/is2vX6d2Cx/O8gnHD4eLAXqQi+U6UflyKzN9 pLmSAalAvMtzvrJQkt4BqWIpAlYr/GE0B+J3gDxQSFz2z4gChiWlWu7brhoueuQApyoT mi8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=rLWxEjPZN+ttDy6470/jW3LY13Gz8VOEZike0sn0oXQ=; b=G0Zh7t/MTQFQFoOrGVk1dVyYHuEg35699z0oS7UB0AHYRIjd1/F4DPr093CUCTFzvb O0uHochhXujQKQe2I4yBOvWNguP4Cj0jM51xIbDlVq3dEGsbbl7lrGNE5zSnNz5LDlJf cghuVc2SKIjl+RDHgD1SC6vHDQN90e8NqaTxca7F77T60m/OISmVi1hzBaSyG3nAHKBG EHK2GlmbjbLy+Yeme2k5zwitnhPPOflkeLNFUI1ZBm9DEmA7iuv/hbcY8wvNa9vNZJAk Ra8YXjPzNSd+nD1jr8HGKd905wUOzbx/xebAzpV9Eks32/tTWCkD/dZAgqPDfTpAxlwx PySg== X-Gm-Message-State: APjAAAX8gIQqVtE77woBHapK4IeMj8PXD13L6sG7NlAxT1Wg5VVRHuk1 GpG1soM3Q6gSr2A0WfspjYbnhbPG X-Google-Smtp-Source: APXvYqwAUnczJwFYtM12p0LE6xdnzBvr+y1QVlH8VScxu4voXqZljbwu+u9naqQDgylmEkNib9QHDA== X-Received: by 2002:a05:600c:2243:: with SMTP id a3mr1459914wmm.83.1561081360686; Thu, 20 Jun 2019 18:42:40 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:12 +0200 Message-Id: <1561081350-3723-8-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PULL 07/25] i386/kvm: implement 'hv-passthrough' mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov In many case we just want to give Windows guests all currently supported Hyper-V enlightenments and that's where this new mode may come handy. We pass through what was returned by KVM_GET_SUPPORTED_HV_CPUID. hv_cpuid_check_and_set() is modified to also set cpu->hyperv_* flags as we may want to check them later (and we actually do for hv_runtime, hv_synic,...). 'hv-passthrough' is a development only feature, a migration blocker is added to prevent issues while migrating between hosts with different feature sets. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-6-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- docs/hyperv.txt | 10 +++++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 1 + target/i386/kvm.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++-----= ---- 4 files changed, 87 insertions(+), 14 deletions(-) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index c423e0f..beadb2d 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -175,6 +175,16 @@ without the feature to find out if enabling it is bene= ficial. Requires: hv-vapic =20 =20 +4. Development features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In some cases (e.g. during development) it may make sense to use QEMU in +'pass-through' mode and give Windows guests all enlightenments currently +supported by KVM. This pass-through mode is enabled by "hv-passthrough" CPU +flag. +Note: enabling this flag effectively prevents migration as supported featu= res +may differ between target and destination. + + 4. Useful links =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Hyper-V Top Level Functional specification and other information: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e90c1ac..e07996c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5883,6 +5883,7 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_EVMCS, 0), DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, HYPERV_FEAT_IPI, 0), + DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), =20 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 30cd1a0..86edbf5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1390,6 +1390,7 @@ struct X86CPU { char *hyperv_vendor_id; bool hyperv_synic_kvm_only; uint64_t hyperv_features; + bool hyperv_passthrough; =20 bool check_cpuid; bool enforce_cpuid; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index a041b4d..93ac6ba 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -639,7 +639,7 @@ static bool hyperv_enabled(X86CPU *cpu) CPUState *cs =3D CPU(cpu); return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 && ((cpu->hyperv_spinlock_attempts !=3D HYPERV_SPINLOCK_NEVER_RETRY) = || - cpu->hyperv_features); + cpu->hyperv_features || cpu->hyperv_passthrough); } =20 static int kvm_arch_set_tsc_khz(CPUState *cs) @@ -985,10 +985,10 @@ static int hv_cpuid_check_and_set(CPUState *cs, struc= t kvm_cpuid2 *cpuid, { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; - uint32_t r, fw, bits;; + uint32_t r, fw, bits; int i; =20 - if (!hyperv_feat_enabled(cpu, feature)) { + if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) { return 0; } =20 @@ -1001,15 +1001,23 @@ static int hv_cpuid_check_and_set(CPUState *cs, str= uct kvm_cpuid2 *cpuid, } =20 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) !=3D bits) { - fprintf(stderr, - "Hyper-V %s is not supported by kernel\n", - kvm_hyperv_properties[feature].desc); - return 1; + if (hyperv_feat_enabled(cpu, feature)) { + fprintf(stderr, + "Hyper-V %s is not supported by kernel\n", + kvm_hyperv_properties[feature].desc); + return 1; + } else { + return 0; + } } =20 env->features[fw] |=3D bits; } =20 + if (cpu->hyperv_passthrough) { + cpu->hyperv_features |=3D BIT(feature); + } + return 0; } =20 @@ -1027,22 +1035,29 @@ static int hyperv_handle_properties(CPUState *cs, struct kvm_cpuid_entry2 *c; uint32_t signature[3]; uint32_t cpuid_i =3D 0; - int r =3D 0; + int r; =20 if (!hyperv_enabled(cpu)) return 0; =20 - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) || + cpu->hyperv_passthrough) { uint16_t evmcs_version; =20 - if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, - (uintptr_t)&evmcs_version)) { + r =3D kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, + (uintptr_t)&evmcs_version); + + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) { fprintf(stderr, "Hyper-V %s is not supported by kernel\n", kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); return -ENOSYS; } - env->features[FEAT_HV_RECOMM_EAX] |=3D HV_ENLIGHTENED_VMCS_RECOMME= NDED; - env->features[FEAT_HV_NESTED_EAX] =3D evmcs_version; + + if (!r) { + env->features[FEAT_HV_RECOMM_EAX] |=3D + HV_ENLIGHTENED_VMCS_RECOMMENDED; + env->features[FEAT_HV_NESTED_EAX] =3D evmcs_version; + } } =20 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { @@ -1051,8 +1066,33 @@ static int hyperv_handle_properties(CPUState *cs, cpuid =3D get_supported_hv_cpuid_legacy(cs); } =20 + if (cpu->hyperv_passthrough) { + memcpy(cpuid_ent, &cpuid->entries[0], + cpuid->nent * sizeof(cpuid->entries[0])); + + c =3D cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0); + if (c) { + env->features[FEAT_HYPERV_EAX] =3D c->eax; + env->features[FEAT_HYPERV_EBX] =3D c->ebx; + env->features[FEAT_HYPERV_EDX] =3D c->eax; + } + c =3D cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0); + if (c) { + env->features[FEAT_HV_RECOMM_EAX] =3D c->eax; + + /* hv-spinlocks may have been overriden */ + if (cpu->hyperv_spinlock_attempts !=3D HYPERV_SPINLOCK_NEVER_R= ETRY) { + c->ebx =3D cpu->hyperv_spinlock_attempts; + } + } + c =3D cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0); + if (c) { + env->features[FEAT_HV_NESTED_EAX] =3D c->eax; + } + } + /* Features */ - r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED); + r =3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH); @@ -1085,6 +1125,12 @@ static int hyperv_handle_properties(CPUState *cs, goto free; } =20 + if (cpu->hyperv_passthrough) { + /* We already copied all feature words from KVM as is */ + r =3D cpuid->nent; + goto free; + } + c =3D &cpuid_ent[cpuid_i++]; c->function =3D HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; if (!cpu->hyperv_vendor_id) { @@ -1156,11 +1202,26 @@ free: return r; } =20 +static Error *hv_passthrough_mig_blocker; + static int hyperv_init_vcpu(X86CPU *cpu) { CPUState *cs =3D CPU(cpu); + Error *local_err =3D NULL; int ret; =20 + if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker =3D=3D NULL)= { + error_setg(&hv_passthrough_mig_blocker, + "'hv-passthrough' CPU flag prevents migration, use expl= icit" + " set of hv-* flags instead"); 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Thu, 20 Jun 2019 18:42:41 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:13 +0200 Message-Id: <1561081350-3723-9-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::332 Subject: [Qemu-devel] [PULL 08/25] i386/kvm: hv-stimer requires hv-time and hv-synic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Synthetic timers operate in hv-time time and Windows won't use these without SynIC. Add .dependencies field to kvm_hyperv_properties[] and a generic mechanism to check dependencies between features. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-7-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 93ac6ba..58afa31 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -689,6 +689,7 @@ static struct { uint32_t fw; uint32_t bits; } flags[2]; + uint64_t dependencies; } kvm_hyperv_properties[] =3D { [HYPERV_FEAT_RELAXED] =3D { .desc =3D "relaxed timing (hv-relaxed)", @@ -756,7 +757,8 @@ static struct { .flags =3D { {.fw =3D FEAT_HYPERV_EAX, .bits =3D HV_SYNTIMERS_AVAILABLE} - } + }, + .dependencies =3D BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME) }, [HYPERV_FEAT_FREQUENCIES] =3D { .desc =3D "frequency MSRs (hv-frequencies)", @@ -986,12 +988,25 @@ static int hv_cpuid_check_and_set(CPUState *cs, struc= t kvm_cpuid2 *cpuid, X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; uint32_t r, fw, bits; - int i; + uint64_t deps; + int i, dep_feat =3D 0; =20 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) { return 0; } =20 + deps =3D kvm_hyperv_properties[feature].dependencies; + while ((dep_feat =3D find_next_bit(&deps, 64, dep_feat)) < 64) { + if (!(hyperv_feat_enabled(cpu, dep_feat))) { + fprintf(stderr, + "Hyper-V %s requires Hyper-V %s\n", + kvm_hyperv_properties[feature].desc, + kvm_hyperv_properties[dep_feat].desc); + return 1; + } + dep_feat++; + } + for (i =3D 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i+= +) { fw =3D kvm_hyperv_properties[feature].flags[i].fw; bits =3D kvm_hyperv_properties[feature].flags[i].bits; @@ -1107,11 +1122,11 @@ static int hyperv_handle_properties(CPUState *cs, r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI); =20 - /* Dependencies */ + /* Additional dependencies not covered by kvm_hyperv_properties[] */ if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && !cpu->hyperv_synic_kvm_only && !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { - fprintf(stderr, "Hyper-V %s requires %s\n", + fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n", kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); 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X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 09/25] i386/kvm: hv-tlbflush/ipi require hv-vpindex X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov The corresponding hypercalls require using VP indexes. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-8-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 58afa31..1dfa282 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -782,7 +782,8 @@ static struct { {.fw =3D FEAT_HV_RECOMM_EAX, .bits =3D HV_REMOTE_TLB_FLUSH_RECOMMENDED | HV_EX_PROCESSOR_MASKS_RECOMMENDED} - } + }, + .dependencies =3D BIT(HYPERV_FEAT_VPINDEX) }, [HYPERV_FEAT_EVMCS] =3D { .desc =3D "enlightened VMCS (hv-evmcs)", @@ -797,7 +798,8 @@ static struct { {.fw =3D FEAT_HV_RECOMM_EAX, .bits =3D HV_CLUSTER_IPI_RECOMMENDED | HV_EX_PROCESSOR_MASKS_RECOMMENDED} - } + }, + .dependencies =3D BIT(HYPERV_FEAT_VPINDEX) }, }; =20 --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 10/25] i386/kvm: hv-evmcs requires hv-vapic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Enlightened VMCS is enabled by writing to a field in VP assist page and these require virtual APIC. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-9-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 1dfa282..86de510 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -790,7 +790,8 @@ static struct { .flags =3D { {.fw =3D FEAT_HV_RECOMM_EAX, .bits =3D HV_ENLIGHTENED_VMCS_RECOMMENDED} - } + }, + .dependencies =3D BIT(HYPERV_FEAT_VAPIC) }, [HYPERV_FEAT_IPI] =3D { .desc =3D "paravirtualized IPI (hv-ipi)", --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 20 Jun 2019 18:42:44 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:16 +0200 Message-Id: <1561081350-3723-12-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 11/25] i386/kvm: add support for Direct Mode for Hyper-V synthetic timers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vitaly Kuznetsov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vitaly Kuznetsov Hyper-V on KVM can only use Synthetic timers with Direct Mode (opting for an interrupt instead of VMBus message). This new capability is only announced in KVM_GET_SUPPORTED_HV_CPUID. Signed-off-by: Vitaly Kuznetsov Message-Id: <20190517141924.19024-10-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini --- docs/hyperv.txt | 10 ++++++++++ target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + target/i386/hyperv-proto.h | 1 + target/i386/kvm.c | 9 +++++++++ 5 files changed, 23 insertions(+) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index beadb2d..8fdf25c 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -174,6 +174,16 @@ without the feature to find out if enabling it is bene= ficial. =20 Requires: hv-vapic =20 +3.17. hv-stimer-direct +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Hyper-V specification allows synthetic timer operation in two modes: "clas= sic", +when expiration event is delivered as SynIC message and "direct", when the= event +is delivered via normal interrupt. It is known that nested Hyper-V can only +use synthetic timers in direct mode and thus 'hv-stimer-direct' needs to be +enabled. + +Requires: hv-vpindex, hv-synic, hv-time, hv-stimer + =20 4. Development features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e07996c..7beb8ab 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5883,6 +5883,8 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_EVMCS, 0), DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, HYPERV_FEAT_IPI, 0), + DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, + HYPERV_FEAT_STIMER_DIRECT, 0), DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), =20 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 86edbf5..7470acf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -749,6 +749,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define HYPERV_FEAT_TLBFLUSH 11 #define HYPERV_FEAT_EVMCS 12 #define HYPERV_FEAT_IPI 13 +#define HYPERV_FEAT_STIMER_DIRECT 14 =20 #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF diff --git a/target/i386/hyperv-proto.h b/target/i386/hyperv-proto.h index c0272b3..cffac10 100644 --- a/target/i386/hyperv-proto.h +++ b/target/i386/hyperv-proto.h @@ -49,6 +49,7 @@ #define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) #define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) #define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) +#define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19) =20 /* * HV_CPUID_ENLIGHTMENT_INFO.EAX bits diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 86de510..a323b1f 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -802,6 +802,14 @@ static struct { }, .dependencies =3D BIT(HYPERV_FEAT_VPINDEX) }, + [HYPERV_FEAT_STIMER_DIRECT] =3D { + .desc =3D "direct mode synthetic timers (hv-stimer-direct)", + .flags =3D { + {.fw =3D FEAT_HYPERV_EDX, + .bits =3D HV_STIMER_DIRECT_MODE_AVAILABLE} + }, + .dependencies =3D BIT(HYPERV_FEAT_STIMER) + }, }; =20 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max) @@ -1124,6 +1132,7 @@ static int hyperv_handle_properties(CPUState *cs, r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS); r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI); + r |=3D hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT); =20 /* Additional dependencies not covered by kvm_hyperv_properties[] */ if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 20 Jun 2019 18:42:45 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:17 +0200 Message-Id: <1561081350-3723-13-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 12/25] target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiaoyao Li Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only enumerates the feature split lock detection (via bit 5) by now. The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30= ]. The latest kernel patches about them can be found here: https://lkml.org/lkml/2019/4/24/1909 Signed-off-by: Xiaoyao Li Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 22 +++++++++++++++++++++- target/i386/cpu.h | 5 +++++ target/i386/kvm.c | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7beb8ab..c330fd9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1085,7 +1085,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", - NULL, "arch-capabilities", NULL, "ssbd", + NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid =3D { .eax =3D 7, @@ -1203,6 +1203,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { } }, }, + [FEAT_CORE_CAPABILITY] =3D { + .type =3D MSR_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, "split-lock-detect", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .msr =3D { + .index =3D MSR_IA32_CORE_CAPABILITY, + .cpuid_dep =3D { + FEAT_7_0_EDX, + CPUID_7_0_EDX_CORE_CAPABILITY, + }, + }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7470acf..7f48136 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -345,6 +345,7 @@ typedef enum X86Seg { #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f #define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_CORE_CAPABILITY 0xcf #define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 =20 @@ -496,6 +497,7 @@ typedef enum FeatureWord { FEAT_XSAVE_COMP_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ FEAT_ARCH_CAPABILITIES, + FEAT_CORE_CAPABILITY, FEATURE_WORDS, } FeatureWord; =20 @@ -687,6 +689,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ +#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypa= ss Disable */ =20 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and @@ -734,6 +737,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) =20 +#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) + /* Supported Hyper-V Enlightenments */ #define HYPERV_FEAT_RELAXED 0 #define HYPERV_FEAT_VAPIC 1 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index a323b1f..279f99a 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -95,6 +95,7 @@ static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; static bool has_msr_arch_capabs; +static bool has_msr_core_capabs; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -1842,6 +1843,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_ARCH_CAPABILITIES: has_msr_arch_capabs =3D true; break; + case MSR_IA32_CORE_CAPABILITY: + has_msr_core_capabs =3D true; + break; } } } @@ -2368,6 +2372,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->features[FEAT_ARCH_CAPABILITIES]); } =20 + if (has_msr_core_capabs) { + kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, + env->features[FEAT_CORE_CAPABILITY]); + } + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. 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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PULL 13/25] target/i386: kvm: Delete VMX migration blocker on vCPU init failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Commit d98f26073beb ("target/i386: kvm: add VMX migration blocker") added migration blocker for vCPU exposed with Intel VMX because QEMU doesn't yet contain code to support migration of nested virtualization workloads. However, that commit missed adding deletion of the migration blocker in case init of vCPU failed. Similar to invtsc_mig_blocker. This commit fix that issue. Fixes: d98f26073beb ("target/i386: kvm: add VMX migration blocker") Signed-off-by: Liran Alon Reviewed-by: Maran Wilson Message-Id: <20190619162140.133674-2-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 279f99a..c5cbead 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1333,7 +1333,7 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 r =3D kvm_arch_set_tsc_khz(cs); if (r < 0) { - goto fail; + return r; } =20 /* vcpu's TSC frequency is either specified by user, or following @@ -1622,7 +1622,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (local_err) { error_report_err(local_err); error_free(invtsc_mig_blocker); - return r; + goto fail2; } } } @@ -1673,6 +1673,9 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 fail: migrate_del_blocker(invtsc_mig_blocker); + fail2: + migrate_del_blocker(vmx_mig_blocker); + return r; } =20 --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 14/25] KVM: Introduce kvm_arch_destroy_vcpu() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Simiar to how kvm_init_vcpu() calls kvm_arch_init_vcpu() to perform arch-dependent initialisation, introduce kvm_arch_destroy_vcpu() to be called from kvm_destroy_vcpu() to perform arch-dependent destruction. This was added because some architectures (Such as i386) currently do not free memory that it have allocated in kvm_arch_init_vcpu(). Suggested-by: Maran Wilson Reviewed-by: Maran Wilson Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-3-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 5 +++++ include/sysemu/kvm.h | 1 + target/arm/kvm32.c | 5 +++++ target/arm/kvm64.c | 5 +++++ target/i386/kvm.c | 12 ++++++++++++ target/mips/kvm.c | 5 +++++ target/ppc/kvm.c | 5 +++++ target/s390x/kvm.c | 10 ++++++++++ 8 files changed, 48 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index d2f481a..f0f5ab8 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -291,6 +291,11 @@ int kvm_destroy_vcpu(CPUState *cpu) =20 DPRINTF("kvm_destroy_vcpu\n"); =20 + ret =3D kvm_arch_destroy_vcpu(cpu); + if (ret < 0) { + goto err; + } + mmap_size =3D kvm_ioctl(s, KVM_GET_VCPU_MMAP_SIZE, 0); if (mmap_size < 0) { ret =3D mmap_size; diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index a6d1cd1..64f55e5 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -371,6 +371,7 @@ int kvm_arch_put_registers(CPUState *cpu, int level); int kvm_arch_init(MachineState *ms, KVMState *s); =20 int kvm_arch_init_vcpu(CPUState *cpu); +int kvm_arch_destroy_vcpu(CPUState *cpu); =20 bool kvm_vcpu_id_is_valid(int vcpu_id); =20 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 4e54e37..51f78f7 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -240,6 +240,11 @@ int kvm_arch_init_vcpu(CPUState *cs) return kvm_arm_init_cpreg_list(cpu); } =20 +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + typedef struct Reg { uint64_t id; int offset; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 998d21f..22d19c9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -654,6 +654,11 @@ int kvm_arch_init_vcpu(CPUState *cs) return kvm_arm_init_cpreg_list(cpu); } =20 +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) { /* Return true if the regidx is a register we should synchronize diff --git a/target/i386/kvm.c b/target/i386/kvm.c index c5cbead..26d8c61 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1679,6 +1679,18 @@ int kvm_arch_init_vcpu(CPUState *cs) return r; } =20 +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + if (cpu->kvm_msr_buf) { + g_free(cpu->kvm_msr_buf); + cpu->kvm_msr_buf =3D NULL; + } + + return 0; +} + void kvm_arch_reset_vcpu(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 8e72850..938f8f1 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -91,6 +91,11 @@ int kvm_arch_init_vcpu(CPUState *cs) return ret; } =20 +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + void kvm_mips_reset_vcpu(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d4107dd..4b4989c 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -521,6 +521,11 @@ int kvm_arch_init_vcpu(CPUState *cs) return ret; } =20 +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + static void kvm_sw_tlb_put(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c index bcec979..0267c6c 100644 --- a/target/s390x/kvm.c +++ b/target/s390x/kvm.c @@ -368,6 +368,16 @@ int kvm_arch_init_vcpu(CPUState *cs) return 0; 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Thu, 20 Jun 2019 18:42:48 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:20 +0200 Message-Id: <1561081350-3723-16-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 Subject: [Qemu-devel] [PULL 15/25] target/i386: kvm: Use symbolic constant for #DB/#BP exception constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Reviewed-by: Nikita Leshenko Reviewed-by: Krish Sadhukhan Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-4-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 26d8c61..c763643 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -3345,9 +3345,9 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu) unsigned long reinject_trap =3D 0; =20 if (!kvm_has_vcpu_events()) { - if (env->exception_injected =3D=3D 1) { + if (env->exception_injected =3D=3D EXCP01_DB) { reinject_trap =3D KVM_GUESTDBG_INJECT_DB; - } else if (env->exception_injected =3D=3D 3) { + } else if (env->exception_injected =3D=3D EXCP03_INT3) { reinject_trap =3D KVM_GUESTDBG_INJECT_BP; } env->exception_injected =3D -1; @@ -3859,8 +3859,8 @@ static int kvm_handle_debug(X86CPU *cpu, int ret =3D 0; int n; =20 - if (arch_info->exception =3D=3D 1) { - if (arch_info->dr6 & (1 << 14)) { + if (arch_info->exception =3D=3D EXCP01_DB) { + if (arch_info->dr6 & DR6_BS) { if (cs->singlestep_enabled) { ret =3D EXCP_DEBUG; } --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 20 Jun 2019 18:42:49 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:21 +0200 Message-Id: <1561081350-3723-17-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 16/25] target/i386: kvm: Re-inject #DB to guest with updated DR6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon If userspace (QEMU) debug guest, when #DB is raised in guest and intercepted by KVM, KVM forwards information on #DB to userspace instead of injecting #DB to guest. While doing so, KVM don't update vCPU DR6 but instead report the #DB DR6 value to userspace for further handling. See KVM's handle_exception() DB_VECTOR handler. QEMU handler for this case is kvm_handle_debug(). This handler basically checks if #DB is related to one of user set hardware breakpoints and if not, it re-inject #DB into guest. The re-injection is done by setting env->exception_injected to #DB which will later be passed as events.exception.nr to KVM_SET_VCPU_EVENTS ioctl by kvm_put_vcpu_events(). However, in case userspace re-injects #DB, KVM expects userspace to set vCPU DR6 as reported to userspace when #DB was intercepted! Otherwise, KVM_REQ_EVENT handler will inject #DB with wrong DR6 to guest. Fix this issue by updating vCPU DR6 appropriately when re-inject #DB to guest. Reviewed-by: Nikita Leshenko Reviewed-by: Krish Sadhukhan Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-5-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index c763643..9864aa0 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -3897,6 +3897,9 @@ static int kvm_handle_debug(X86CPU *cpu, /* pass to guest */ env->exception_injected =3D arch_info->exception; env->has_error_code =3D 0; + if (arch_info->exception =3D=3D EXCP01_DB) { + env->dr[6] =3D arch_info->dr6; + } } =20 return ret; --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 20 Jun 2019 18:42:49 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:22 +0200 Message-Id: <1561081350-3723-18-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 Subject: [Qemu-devel] [PULL 17/25] target/i386: kvm: Block migration for vCPUs exposed with nested virtualization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Commit d98f26073beb ("target/i386: kvm: add VMX migration blocker") added a migration blocker for vCPU exposed with Intel VMX. However, migration should also be blocked for vCPU exposed with AMD SVM. Both cases should be blocked because QEMU should extract additional vCPU state from KVM that should be migrated as part of vCPU VMState. E.g. Whether vCPU is running in guest-mode or host-mode. Fixes: d98f26073beb ("target/i386: kvm: add VMX migration blocker") Reviewed-by: Maran Wilson Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-6-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 6 ------ target/i386/cpu.h | 22 ++++++++++++++++++++++ target/i386/kvm.c | 14 +++++++------- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c330fd9..61e44cb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5215,12 +5215,6 @@ static int x86_cpu_filter_features(X86CPU *cpu) return rv; } =20 -#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_INTEL_= 1 && \ - (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_INTEL_= 2 && \ - (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_INTEL_= 3) -#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_AMD_1 &&= \ - (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 &&= \ - (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f48136..4ae4145 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -722,6 +722,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; =20 #define CPUID_VENDOR_HYGON "HygonGenuine" =20 +#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_INTEL_= 1 && \ + (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_INTEL_= 2 && \ + (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_INTEL_= 3) +#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_AMD_1 &&= \ + (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_AMD_2 &&= \ + (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_AMD_3) + #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 @@ -1848,6 +1855,21 @@ static inline int32_t x86_get_a20_mask(CPUX86State *= env) } } =20 +static inline bool cpu_has_vmx(CPUX86State *env) +{ + return (env->features[FEAT_1_ECX] & CPUID_EXT_VMX); +} + +static inline bool cpu_has_svm(CPUX86State *env) +{ + return (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM); +} + +static inline bool cpu_has_nested_virt(CPUX86State *env) +{ + return (cpu_has_vmx(env) || cpu_has_svm(env)); +} + /* fpu_helper.c */ void update_fp_status(CPUX86State *env); void update_mxcsr_status(CPUX86State *env); diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9864aa0..f9872f1 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1299,7 +1299,7 @@ static int hyperv_init_vcpu(X86CPU *cpu) } =20 static Error *invtsc_mig_blocker; -static Error *vmx_mig_blocker; +static Error *nested_virt_mig_blocker; =20 #define KVM_MAX_CPUID_ENTRIES 100 =20 @@ -1597,13 +1597,13 @@ int kvm_arch_init_vcpu(CPUState *cs) !!(c->ecx & CPUID_EXT_SMX); } =20 - if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) { - error_setg(&vmx_mig_blocker, - "Nested VMX virtualization does not support live migrat= ion yet"); - r =3D migrate_add_blocker(vmx_mig_blocker, &local_err); + if (cpu_has_nested_virt(env) && !nested_virt_mig_blocker) { + error_setg(&nested_virt_mig_blocker, + "Nested virtualization does not support live migration = yet"); + r =3D migrate_add_blocker(nested_virt_mig_blocker, &local_err); if (local_err) { error_report_err(local_err); - error_free(vmx_mig_blocker); + error_free(nested_virt_mig_blocker); return r; } } @@ -1674,7 +1674,7 @@ int kvm_arch_init_vcpu(CPUState *cs) fail: migrate_del_blocker(invtsc_mig_blocker); fail2: - migrate_del_blocker(vmx_mig_blocker); + migrate_del_blocker(nested_virt_mig_blocker); =20 return r; } --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561082757; 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Thu, 20 Jun 2019 18:42:50 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:23 +0200 Message-Id: <1561081350-3723-19-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 18/25] linux-headers: sync with latest KVM headers from Linux 5.2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Improve the KVM_{GET,SET}_NESTED_STATE structs by detailing the format of VMX nested state data in a struct. In order to avoid changing the ioctl values of KVM_{GET,SET}_NESTED_STATE, there is a need to preserve sizeof(struct kvm_nested_state). This is done by defining the data struct as "data.vmx[0]". It was the most elegant way I found to preserve struct size while still keeping struct readable and easy to maintain. It does have a misfortunate side-effect that now it has to be accessed as "data.vmx[0]" rather than just "data.vmx". Because we are already modifying these structs, I also modified the following: * Define the "format" field values as macros. * Rename vmcs_pa to vmcs12_pa for better readability. Signed-off-by: Liran Alon Reviewed-by: Maran Wilson Message-Id: <20190619162140.133674-7-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- linux-headers/asm-x86/kvm.h | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 7a0e64c..6e7dd79 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -383,16 +383,26 @@ struct kvm_sync_regs { #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) =20 +#define KVM_STATE_NESTED_FORMAT_VMX 0 +#define KVM_STATE_NESTED_FORMAT_SVM 1 + #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 #define KVM_STATE_NESTED_EVMCS 0x00000004 =20 +#define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 + #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 =20 -struct kvm_vmx_nested_state { +struct kvm_vmx_nested_state_data { + __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; + __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; +}; + +struct kvm_vmx_nested_state_hdr { __u64 vmxon_pa; - __u64 vmcs_pa; + __u64 vmcs12_pa; =20 struct { __u16 flags; @@ -401,24 +411,25 @@ struct kvm_vmx_nested_state { =20 /* for KVM_CAP_NESTED_STATE */ struct kvm_nested_state { - /* KVM_STATE_* flags */ __u16 flags; - - /* 0 for VMX, 1 for SVM. */ __u16 format; - - /* 128 for SVM, 128 + VMCS size for VMX. */ __u32 size; =20 union { - /* VMXON, VMCS */ - struct kvm_vmx_nested_state vmx; + struct kvm_vmx_nested_state_hdr vmx; =20 /* Pad the header to 128 bytes. */ __u8 pad[120]; - }; + } hdr; =20 - __u8 data[0]; + /* + * Define data region as 0 bytes to preserve backwards-compatability + * to old definition of kvm_nested_state in order to avoid changing + * KVM_{GET,PUT}_NESTED_STATE ioctl values. + */ + union { + struct kvm_vmx_nested_state_data vmx[0]; + } data; }; =20 #endif /* _ASM_X86_KVM_H */ --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PULL 19/25] vmstate: Add support for kernel integer types X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Reviewed-by: Nikita Leshenko Reviewed-by: Maran Wilson Signed-off-by: Liran Alon Reviewed-by: Dr. David Alan Gilbert Message-Id: <20190619162140.133674-8-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- include/migration/vmstate.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 9224370..ca68584 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -797,6 +797,19 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT64_V(_f, _s, _v) \ VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint64, uint64_t) =20 +#ifdef CONFIG_LINUX + +#define VMSTATE_U8_V(_f, _s, _v) \ + VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint8, __u8) +#define VMSTATE_U16_V(_f, _s, _v) \ + VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint16, __u16) +#define VMSTATE_U32_V(_f, _s, _v) \ + VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint32, __u32) +#define VMSTATE_U64_V(_f, _s, _v) \ + VMSTATE_SINGLE(_f, _s, _v, vmstate_info_uint64, __u64) + +#endif + #define VMSTATE_BOOL(_f, _s) \ VMSTATE_BOOL_V(_f, _s, 0) =20 @@ -818,6 +831,19 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT64(_f, _s) \ VMSTATE_UINT64_V(_f, _s, 0) =20 +#ifdef CONFIG_LINUX + +#define VMSTATE_U8(_f, _s) \ + VMSTATE_U8_V(_f, _s, 0) +#define VMSTATE_U16(_f, _s) \ + VMSTATE_U16_V(_f, _s, 0) +#define VMSTATE_U32(_f, _s) \ + VMSTATE_U32_V(_f, _s, 0) +#define VMSTATE_U64(_f, _s) \ + VMSTATE_U64_V(_f, _s, 0) + +#endif + #define VMSTATE_UINT8_EQUAL(_f, _s, _err_hint) \ VMSTATE_SINGLE_FULL(_f, _s, 0, 0, \ vmstate_info_uint8_equal, uint8_t, _err_hint) --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 20/25] target/i386: kvm: Add support for save and restore nested state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Kernel commit 8fcc4b5923af ("kvm: nVMX: Introduce KVM_CAP_NESTED_STATE") introduced new IOCTLs to extract and restore vCPU state related to Intel VMX & AMD SVM. Utilize these IOCTLs to add support for migration of VMs which are running nested hypervisors. Reviewed-by: Nikita Leshenko Reviewed-by: Maran Wilson Tested-by: Maran Wilson Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-9-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 8 ++ include/sysemu/kvm.h | 1 + target/i386/cpu.h | 3 + target/i386/kvm.c | 80 ++++++++++++++++++++ target/i386/machine.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 290 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f0f5ab8..e3cf728 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -87,6 +87,7 @@ struct KVMState #ifdef KVM_CAP_SET_GUEST_DEBUG QTAILQ_HEAD(, kvm_sw_breakpoint) kvm_sw_breakpoints; #endif + int max_nested_state_len; int many_ioeventfds; int intx_set_mask; bool sync_mmu; @@ -1681,6 +1682,8 @@ static int kvm_init(MachineState *ms) s->debugregs =3D kvm_check_extension(s, KVM_CAP_DEBUGREGS); #endif =20 + s->max_nested_state_len =3D kvm_check_extension(s, KVM_CAP_NESTED_STAT= E); + #ifdef KVM_CAP_IRQ_ROUTING kvm_direct_msi_allowed =3D (kvm_check_extension(s, KVM_CAP_SIGNAL_MSI)= > 0); #endif @@ -2248,6 +2251,11 @@ int kvm_has_debugregs(void) return kvm_state->debugregs; } =20 +int kvm_max_nested_state_length(void) +{ + return kvm_state->max_nested_state_len; +} + int kvm_has_many_ioeventfds(void) { if (!kvm_enabled()) { diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 64f55e5..acd90ae 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -210,6 +210,7 @@ bool kvm_has_sync_mmu(void); int kvm_has_vcpu_events(void); int kvm_has_robust_singlestep(void); int kvm_has_debugregs(void); +int kvm_max_nested_state_length(void); int kvm_has_pit_state2(void); int kvm_has_many_ioeventfds(void); int kvm_has_gsi_routing(void); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4ae4145..16d898c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1360,6 +1360,9 @@ typedef struct CPUX86State { #if defined(CONFIG_KVM) || defined(CONFIG_HVF) void *xsave_buf; #endif +#if defined(CONFIG_KVM) + struct kvm_nested_state *nested_state; +#endif #if defined(CONFIG_HVF) HVFX86EmulatorState *hvf_emul; #endif diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f9872f1..e924663 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1324,6 +1324,7 @@ int kvm_arch_init_vcpu(CPUState *cs) struct kvm_cpuid_entry2 *c; uint32_t signature[3]; int kvm_base =3D KVM_CPUID_SIGNATURE; + int max_nested_state_len; int r; Error *local_err =3D NULL; =20 @@ -1658,6 +1659,24 @@ int kvm_arch_init_vcpu(CPUState *cs) if (has_xsave) { env->xsave_buf =3D qemu_memalign(4096, sizeof(struct kvm_xsave)); } + + max_nested_state_len =3D kvm_max_nested_state_length(); + if (max_nested_state_len > 0) { + assert(max_nested_state_len >=3D offsetof(struct kvm_nested_state,= data)); + env->nested_state =3D g_malloc0(max_nested_state_len); + + env->nested_state->size =3D max_nested_state_len; + + if (IS_INTEL_CPU(env)) { + struct kvm_vmx_nested_state_hdr *vmx_hdr =3D + &env->nested_state->hdr.vmx; + + env->nested_state->format =3D KVM_STATE_NESTED_FORMAT_VMX; + vmx_hdr->vmxon_pa =3D -1ull; + vmx_hdr->vmcs12_pa =3D -1ull; + } + } + cpu->kvm_msr_buf =3D g_malloc0(MSR_BUF_SIZE); =20 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) { @@ -1682,12 +1701,18 @@ int kvm_arch_init_vcpu(CPUState *cs) int kvm_arch_destroy_vcpu(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; =20 if (cpu->kvm_msr_buf) { g_free(cpu->kvm_msr_buf); cpu->kvm_msr_buf =3D NULL; } =20 + if (env->nested_state) { + g_free(env->nested_state); + env->nested_state =3D NULL; + } + return 0; } =20 @@ -3411,6 +3436,52 @@ static int kvm_get_debugregs(X86CPU *cpu) return 0; } =20 +static int kvm_put_nested_state(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + int max_nested_state_len =3D kvm_max_nested_state_length(); + + if (max_nested_state_len <=3D 0) { + return 0; + } + + assert(env->nested_state->size <=3D max_nested_state_len); + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_stat= e); +} + +static int kvm_get_nested_state(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + int max_nested_state_len =3D kvm_max_nested_state_length(); + int ret; + + if (max_nested_state_len <=3D 0) { + return 0; + } + + /* + * It is possible that migration restored a smaller size into + * nested_state->hdr.size than what our kernel support. + * We preserve migration origin nested_state->hdr.size for + * call to KVM_SET_NESTED_STATE but wish that our next call + * to KVM_GET_NESTED_STATE will use max size our kernel support. + */ + env->nested_state->size =3D max_nested_state_len; + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_sta= te); + if (ret < 0) { + return ret; + } + + if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) { + env->hflags |=3D HF_GUEST_MASK; + } else { + env->hflags &=3D ~HF_GUEST_MASK; + } + + return ret; +} + int kvm_arch_put_registers(CPUState *cpu, int level) { X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -3418,6 +3489,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level) =20 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); =20 + ret =3D kvm_put_nested_state(x86_cpu); + if (ret < 0) { + return ret; + } + if (level >=3D KVM_PUT_RESET_STATE) { ret =3D kvm_put_msr_feature_control(x86_cpu); if (ret < 0) { @@ -3533,6 +3609,10 @@ int kvm_arch_get_registers(CPUState *cs) if (ret < 0) { goto out; } + ret =3D kvm_get_nested_state(cpu); + if (ret < 0) { + goto out; + } ret =3D 0; out: cpu_sync_bndcs_hflags(&cpu->env); diff --git a/target/i386/machine.c b/target/i386/machine.c index a39ce7f..a6afdf8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -231,6 +231,15 @@ static int cpu_pre_save(void *opaque) env->segs[R_SS].flags &=3D ~(env->segs[R_SS].flags & DESC_DPL_MASK= ); } =20 +#ifdef CONFIG_KVM + /* Verify we have nested virtualization state from kernel if required = */ + if (cpu_has_nested_virt(env) && !env->nested_state) { + error_report("Guest enabled nested virtualization but kernel " + "does not support saving of nested state"); + return -EINVAL; + } +#endif + return 0; } =20 @@ -278,6 +287,16 @@ static int cpu_post_load(void *opaque, int version_id) env->hflags &=3D ~HF_CPL_MASK; env->hflags |=3D (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MA= SK; =20 +#ifdef CONFIG_KVM + if ((env->hflags & HF_GUEST_MASK) && + (!env->nested_state || + !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) { + error_report("vCPU set in guest-mode inconsistent with " + "migrated kernel nested state"); + return -EINVAL; + } +#endif + env->fpstt =3D (env->fpus_vmstate >> 11) & 7; env->fpus =3D env->fpus_vmstate & ~0x3800; env->fptag_vmstate ^=3D 0xff; @@ -851,6 +870,182 @@ static const VMStateDescription vmstate_tsc_khz =3D { } }; =20 +#ifdef CONFIG_KVM + +static bool vmx_vmcs12_needed(void *opaque) +{ + struct kvm_nested_state *nested_state =3D opaque; + return (nested_state->size > + offsetof(struct kvm_nested_state, data.vmx[0].vmcs12)); +} + +static const VMStateDescription vmstate_vmx_vmcs12 =3D { + .name =3D "cpu/kvm_nested_state/vmx/vmcs12", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D vmx_vmcs12_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(data.vmx[0].vmcs12, + struct kvm_nested_state, + KVM_STATE_NESTED_VMX_VMCS_SIZE), + VMSTATE_END_OF_LIST() + } +}; + +static bool vmx_shadow_vmcs12_needed(void *opaque) +{ + struct kvm_nested_state *nested_state =3D opaque; + return (nested_state->size > + offsetof(struct kvm_nested_state, data.vmx[0].shadow_vmcs12)); +} + +static const VMStateDescription vmstate_vmx_shadow_vmcs12 =3D { + .name =3D "cpu/kvm_nested_state/vmx/shadow_vmcs12", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D vmx_shadow_vmcs12_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(data.vmx[0].shadow_vmcs12, + struct kvm_nested_state, + KVM_STATE_NESTED_VMX_VMCS_SIZE), + VMSTATE_END_OF_LIST() + } +}; + +static bool vmx_nested_state_needed(void *opaque) +{ + struct kvm_nested_state *nested_state =3D opaque; + + return ((nested_state->format =3D=3D KVM_STATE_NESTED_FORMAT_VMX) && + ((nested_state->hdr.vmx.vmxon_pa !=3D -1ull) || + (nested_state->hdr.vmx.smm.flags & KVM_STATE_NESTED_SMM_VMXON= ))); +} + +static const VMStateDescription vmstate_vmx_nested_state =3D { + .name =3D "cpu/kvm_nested_state/vmx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D vmx_nested_state_needed, + .fields =3D (VMStateField[]) { + VMSTATE_U64(hdr.vmx.vmxon_pa, struct kvm_nested_state), + VMSTATE_U64(hdr.vmx.vmcs12_pa, struct kvm_nested_state), + VMSTATE_U16(hdr.vmx.smm.flags, struct kvm_nested_state), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_vmx_vmcs12, + &vmstate_vmx_shadow_vmcs12, + NULL, + } +}; + +static bool svm_nested_state_needed(void *opaque) +{ + struct kvm_nested_state *nested_state =3D opaque; + + return (nested_state->format =3D=3D KVM_STATE_NESTED_FORMAT_SVM); +} + +static const VMStateDescription vmstate_svm_nested_state =3D { + .name =3D "cpu/kvm_nested_state/svm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D svm_nested_state_needed, + .fields =3D (VMStateField[]) { + VMSTATE_END_OF_LIST() + } +}; + +static bool nested_state_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return (env->nested_state && + (vmx_nested_state_needed(env->nested_state) || + svm_nested_state_needed(env->nested_state))); +} + +static int nested_state_post_load(void *opaque, int version_id) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + struct kvm_nested_state *nested_state =3D env->nested_state; + int min_nested_state_len =3D offsetof(struct kvm_nested_state, data); + int max_nested_state_len =3D kvm_max_nested_state_length(); + + /* + * If our kernel don't support setting nested state + * and we have received nested state from migration stream, + * we need to fail migration + */ + if (max_nested_state_len <=3D 0) { + error_report("Received nested state when kernel cannot restore it"= ); + return -EINVAL; + } + + /* + * Verify that the size of received nested_state struct + * at least cover required header and is not larger + * than the max size that our kernel support + */ + if (nested_state->size < min_nested_state_len) { + error_report("Received nested state size less than min: " + "len=3D%d, min=3D%d", + nested_state->size, min_nested_state_len); + return -EINVAL; + } + if (nested_state->size > max_nested_state_len) { + error_report("Recieved unsupported nested state size: " + "nested_state->size=3D%d, max=3D%d", + nested_state->size, max_nested_state_len); + return -EINVAL; + } + + /* Verify format is valid */ + if ((nested_state->format !=3D KVM_STATE_NESTED_FORMAT_VMX) && + (nested_state->format !=3D KVM_STATE_NESTED_FORMAT_SVM)) { + error_report("Received invalid nested state format: %d", + nested_state->format); + return -EINVAL; + } + + return 0; +} + +static const VMStateDescription vmstate_kvm_nested_state =3D { + .name =3D "cpu/kvm_nested_state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_U16(flags, struct kvm_nested_state), + VMSTATE_U16(format, struct kvm_nested_state), + VMSTATE_U32(size, struct kvm_nested_state), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_vmx_nested_state, + &vmstate_svm_nested_state, + NULL + } +}; + +static const VMStateDescription vmstate_nested_state =3D { + .name =3D "cpu/nested_state", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D nested_state_needed, + .post_load =3D nested_state_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_POINTER(env.nested_state, X86CPU, + vmstate_kvm_nested_state, + struct kvm_nested_state), + VMSTATE_END_OF_LIST() + } +}; + +#endif + static bool mcg_ext_ctl_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1113,6 +1308,9 @@ VMStateDescription vmstate_x86_cpu =3D { #ifndef TARGET_X86_64 &vmstate_efer32, #endif +#ifdef CONFIG_KVM + &vmstate_nested_state, +#endif NULL } }; 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 21/25] target/i386: kvm: Add support for KVM_CAP_EXCEPTION_PAYLOAD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Kernel commit c4f55198c7c2 ("kvm: x86: Introduce KVM_CAP_EXCEPTION_PAYLOAD") introduced a new KVM capability which allows userspace to correctly distinguish between pending and injected exceptions. This distinguish is important in case of nested virtualization scenarios because a L2 pending exception can still be intercepted by the L1 hypervisor while a L2 injected exception cannot. Furthermore, when an exception is attempted to be injected by QEMU, QEMU should specify the exception payload (CR2 in case of #PF or DR6 in case of #DB) instead of having the payload already delivered in the respective vCPU register. Because in case exception is injected to L2 guest and is intercepted by L1 hypervisor, then payload needs to be reported to L1 intercept (VMExit handler) while still preserving respective vCPU register unchanged. This commit adds support for QEMU to properly utilise this new KVM capability (KVM_CAP_EXCEPTION_PAYLOAD). Reviewed-by: Nikita Leshenko Signed-off-by: Liran Alon Message-Id: <20190619162140.133674-10-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 6 ++- target/i386/cpu.h | 6 ++- target/i386/hvf/hvf.c | 10 +++-- target/i386/hvf/x86hvf.c | 4 +- target/i386/kvm.c | 101 +++++++++++++++++++++++++++++++++++++++----= ---- target/i386/machine.c | 84 ++++++++++++++++++++++++++++++++++++++- 6 files changed, 187 insertions(+), 24 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 61e44cb..da6eb67 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4819,7 +4819,11 @@ static void x86_cpu_reset(CPUState *s) memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); =20 env->interrupt_injected =3D -1; - env->exception_injected =3D -1; + env->exception_nr =3D -1; + env->exception_pending =3D 0; + env->exception_injected =3D 0; + env->exception_has_payload =3D false; + env->exception_payload =3D 0; env->nmi_injected =3D false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 16d898c..7e003b8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1348,10 +1348,14 @@ typedef struct CPUX86State { =20 /* For KVM */ uint32_t mp_state; - int32_t exception_injected; + int32_t exception_nr; int32_t interrupt_injected; uint8_t soft_interrupt; + uint8_t exception_pending; + uint8_t exception_injected; uint8_t has_error_code; + uint8_t exception_has_payload; + uint64_t exception_payload; uint32_t ins_len; uint32_t sipi_vector; bool tsc_valid; diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 2751c81..dc4bb63 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -605,7 +605,9 @@ static void hvf_store_events(CPUState *cpu, uint32_t in= s_len, uint64_t idtvec_in X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - env->exception_injected =3D -1; + env->exception_nr =3D -1; + env->exception_pending =3D 0; + env->exception_injected =3D 0; env->interrupt_injected =3D -1; env->nmi_injected =3D false; if (idtvec_info & VMCS_IDT_VEC_VALID) { @@ -619,7 +621,8 @@ static void hvf_store_events(CPUState *cpu, uint32_t in= s_len, uint64_t idtvec_in break; case VMCS_IDT_VEC_HWEXCEPTION: case VMCS_IDT_VEC_SWEXCEPTION: - env->exception_injected =3D idtvec_info & VMCS_IDT_VEC_VECNUM; + env->exception_nr =3D idtvec_info & VMCS_IDT_VEC_VECNUM; + env->exception_injected =3D 1; break; case VMCS_IDT_VEC_PRIV_SWEXCEPTION: default: @@ -912,7 +915,8 @@ int hvf_vcpu_exec(CPUState *cpu) macvm_set_rip(cpu, rip + ins_len); break; case VMX_REASON_VMCALL: - env->exception_injected =3D EXCP0D_GPF; + env->exception_nr =3D EXCP0D_GPF; + env->exception_injected =3D 1; env->has_error_code =3D true; env->error_code =3D 0; break; diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index df8e946..e0ea02d 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -362,8 +362,8 @@ bool hvf_inject_interrupts(CPUState *cpu_state) if (env->interrupt_injected !=3D -1) { vector =3D env->interrupt_injected; intr_type =3D VMCS_INTR_T_SWINTR; - } else if (env->exception_injected !=3D -1) { - vector =3D env->exception_injected; + } else if (env->exception_nr !=3D -1) { + vector =3D env->exception_nr; if (vector =3D=3D EXCP03_INT3 || vector =3D=3D EXCP04_INTO) { intr_type =3D VMCS_INTR_T_SWEXCEPTION; } else { diff --git a/target/i386/kvm.c b/target/i386/kvm.c index e924663..ab812b5 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -104,6 +104,7 @@ static uint32_t num_architectural_pmu_fixed_counters; static int has_xsave; static int has_xcrs; static int has_pit_state2; +static int has_exception_payload; =20 static bool has_msr_mcg_ext_ctl; =20 @@ -584,15 +585,56 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, v= oid *addr) /* Hope we are lucky for AO MCE */ } =20 +static void kvm_reset_exception(CPUX86State *env) +{ + env->exception_nr =3D -1; + env->exception_pending =3D 0; + env->exception_injected =3D 0; + env->exception_has_payload =3D false; + env->exception_payload =3D 0; +} + +static void kvm_queue_exception(CPUX86State *env, + int32_t exception_nr, + uint8_t exception_has_payload, + uint64_t exception_payload) +{ + assert(env->exception_nr =3D=3D -1); + assert(!env->exception_pending); + assert(!env->exception_injected); + assert(!env->exception_has_payload); + + env->exception_nr =3D exception_nr; + + if (has_exception_payload) { + env->exception_pending =3D 1; + + env->exception_has_payload =3D exception_has_payload; + env->exception_payload =3D exception_payload; + } else { + env->exception_injected =3D 1; + + if (exception_nr =3D=3D EXCP01_DB) { + assert(exception_has_payload); + env->dr[6] =3D exception_payload; + } else if (exception_nr =3D=3D EXCP0E_PAGE) { + assert(exception_has_payload); + env->cr[2] =3D exception_payload; + } else { + assert(!exception_has_payload); + } + } +} + static int kvm_inject_mce_oldstyle(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; =20 - if (!kvm_has_vcpu_events() && env->exception_injected =3D=3D EXCP12_MC= HK) { + if (!kvm_has_vcpu_events() && env->exception_nr =3D=3D EXCP12_MCHK) { unsigned int bank, bank_num =3D env->mcg_cap & 0xff; struct kvm_x86_mce mce; =20 - env->exception_injected =3D -1; + kvm_reset_exception(env); =20 /* * There must be at least one bank in use if an MCE is pending. @@ -1943,6 +1985,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 hv_vpindex_settable =3D kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX= ); =20 + has_exception_payload =3D kvm_check_extension(s, KVM_CAP_EXCEPTION_PAY= LOAD); + if (has_exception_payload) { + ret =3D kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true); + if (ret < 0) { + error_report("kvm: Failed to enable exception payload cap: %s", + strerror(-ret)); + return ret; + } + } + ret =3D kvm_get_supported_msrs(s); if (ret < 0) { return ret; @@ -3253,8 +3305,16 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int leve= l) return 0; } =20 - events.exception.injected =3D (env->exception_injected >=3D 0); - events.exception.nr =3D env->exception_injected; + events.flags =3D 0; + + if (has_exception_payload) { + events.flags |=3D KVM_VCPUEVENT_VALID_PAYLOAD; + events.exception.pending =3D env->exception_pending; + events.exception_has_payload =3D env->exception_has_payload; + events.exception_payload =3D env->exception_payload; + } + events.exception.nr =3D env->exception_nr; + events.exception.injected =3D env->exception_injected; events.exception.has_error_code =3D env->has_error_code; events.exception.error_code =3D env->error_code; =20 @@ -3267,7 +3327,6 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level) events.nmi.masked =3D !!(env->hflags2 & HF2_NMI_MASK); =20 events.sipi_vector =3D env->sipi_vector; - events.flags =3D 0; =20 if (has_msr_smbase) { events.smi.smm =3D !!(env->hflags & HF_SMM_MASK); @@ -3317,8 +3376,19 @@ static int kvm_get_vcpu_events(X86CPU *cpu) if (ret < 0) { return ret; } - env->exception_injected =3D - events.exception.injected ? events.exception.nr : -1; + + if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) { + env->exception_pending =3D events.exception.pending; + env->exception_has_payload =3D events.exception_has_payload; + env->exception_payload =3D events.exception_payload; + } else { + env->exception_pending =3D 0; + env->exception_has_payload =3D false; + } + env->exception_injected =3D events.exception.injected; + env->exception_nr =3D + (env->exception_pending || env->exception_injected) ? + events.exception.nr : -1; env->has_error_code =3D events.exception.has_error_code; env->error_code =3D events.exception.error_code; =20 @@ -3370,12 +3440,12 @@ static int kvm_guest_debug_workarounds(X86CPU *cpu) unsigned long reinject_trap =3D 0; =20 if (!kvm_has_vcpu_events()) { - if (env->exception_injected =3D=3D EXCP01_DB) { + if (env->exception_nr =3D=3D EXCP01_DB) { reinject_trap =3D KVM_GUESTDBG_INJECT_DB; } else if (env->exception_injected =3D=3D EXCP03_INT3) { reinject_trap =3D KVM_GUESTDBG_INJECT_BP; } - env->exception_injected =3D -1; + kvm_reset_exception(env); } =20 /* @@ -3751,13 +3821,13 @@ int kvm_arch_process_async_events(CPUState *cs) =20 kvm_cpu_synchronize_state(cs); =20 - if (env->exception_injected =3D=3D EXCP08_DBLE) { + if (env->exception_nr =3D=3D EXCP08_DBLE) { /* this means triple fault */ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); cs->exit_request =3D 1; return 0; } - env->exception_injected =3D EXCP12_MCHK; + kvm_queue_exception(env, EXCP12_MCHK, 0, 0); env->has_error_code =3D 0; =20 cs->halted =3D 0; @@ -3972,14 +4042,13 @@ static int kvm_handle_debug(X86CPU *cpu, } if (ret =3D=3D 0) { cpu_synchronize_state(cs); - assert(env->exception_injected =3D=3D -1); + assert(env->exception_nr =3D=3D -1); =20 /* pass to guest */ - env->exception_injected =3D arch_info->exception; + kvm_queue_exception(env, arch_info->exception, + arch_info->exception =3D=3D EXCP01_DB, + arch_info->dr6); env->has_error_code =3D 0; - if (arch_info->exception =3D=3D EXCP01_DB) { - env->dr[6] =3D arch_info->dr6; - } } =20 return ret; diff --git a/target/i386/machine.c b/target/i386/machine.c index a6afdf8..f66f342 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -240,6 +240,41 @@ static int cpu_pre_save(void *opaque) } #endif =20 + /* + * When vCPU is running L2 and exception is still pending, + * it can potentially be intercepted by L1 hypervisor. + * In contrast to an injected exception which cannot be + * intercepted anymore. + * + * Furthermore, when a L2 exception is intercepted by L1 + * hypervisor, it's exception payload (CR2/DR6 on #PF/#DB) + * should not be set yet in the respective vCPU register. + * Thus, in case an exception is pending, it is + * important to save the exception payload seperately. + * + * Therefore, if an exception is not in a pending state + * or vCPU is not in guest-mode, it is not important to + * distinguish between a pending and injected exception + * and we don't need to store seperately the exception payload. + * + * In order to preserve better backwards-compatabile migration, + * convert a pending exception to an injected exception in + * case it is not important to distingiush between them + * as described above. + */ + if (env->exception_pending && !(env->hflags & HF_GUEST_MASK)) { + env->exception_pending =3D 0; + env->exception_injected =3D 1; + + if (env->exception_has_payload) { + if (env->exception_nr =3D=3D EXCP01_DB) { + env->dr[6] =3D env->exception_payload; + } else if (env->exception_nr =3D=3D EXCP0E_PAGE) { + env->cr[2] =3D env->exception_payload; + } + } + } + return 0; } =20 @@ -297,6 +332,23 @@ static int cpu_post_load(void *opaque, int version_id) } #endif =20 + /* + * There are cases that we can get valid exception_nr with both + * exception_pending and exception_injected being cleared. + * This can happen in one of the following scenarios: + * 1) Source is older QEMU without KVM_CAP_EXCEPTION_PAYLOAD support. + * 2) Source is running on kernel without KVM_CAP_EXCEPTION_PAYLOAD su= pport. + * 3) "cpu/exception_info" subsection not sent because there is no exc= eption + * pending or guest wasn't running L2 (See comment in cpu_pre_save()= ). + * + * In those cases, we can just deduce that a valid exception_nr means + * we can treat the exception as already injected. + */ + if ((env->exception_nr !=3D -1) && + !env->exception_pending && !env->exception_injected) { + env->exception_injected =3D 1; + } + env->fpstt =3D (env->fpus_vmstate >> 11) & 7; env->fpus =3D env->fpus_vmstate & ~0x3800; env->fptag_vmstate ^=3D 0xff; @@ -342,6 +394,35 @@ static bool steal_time_msr_needed(void *opaque) return cpu->env.steal_time_msr !=3D 0; } =20 +static bool exception_info_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + /* + * It is important to save exception-info only in case + * we need to distingiush between a pending and injected + * exception. Which is only required in case there is a + * pending exception and vCPU is running L2. + * For more info, refer to comment in cpu_pre_save(). + */ + return (env->exception_pending && (env->hflags & HF_GUEST_MASK)); +} + +static const VMStateDescription vmstate_exception_info =3D { + .name =3D "cpu/exception_info", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D exception_info_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(env.exception_pending, X86CPU), + VMSTATE_UINT8(env.exception_injected, X86CPU), + VMSTATE_UINT8(env.exception_has_payload, X86CPU), + VMSTATE_UINT64(env.exception_payload, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_steal_time_msr =3D { .name =3D "cpu/steal_time_msr", .version_id =3D 1, @@ -1251,7 +1332,7 @@ VMStateDescription vmstate_x86_cpu =3D { VMSTATE_INT32(env.interrupt_injected, X86CPU), VMSTATE_UINT32(env.mp_state, X86CPU), VMSTATE_UINT64(env.tsc, X86CPU), - VMSTATE_INT32(env.exception_injected, X86CPU), + VMSTATE_INT32(env.exception_nr, X86CPU), VMSTATE_UINT8(env.soft_interrupt, X86CPU), VMSTATE_UINT8(env.nmi_injected, X86CPU), VMSTATE_UINT8(env.nmi_pending, X86CPU), @@ -1275,6 +1356,7 @@ VMStateDescription vmstate_x86_cpu =3D { /* The above list is not sorted /wrt version numbers, watch out! */ }, .subsections =3D (const VMStateDescription*[]) { + &vmstate_exception_info, &vmstate_async_pf_msr, &vmstate_pv_eoi_msr, &vmstate_steal_time_msr, --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1561083008; cv=none; d=zoho.com; s=zohoarc; b=LbNvTdTrfWo7ZSzgX0xnZZ5P2/uUWBdTd7o3MB5RWZ1fcoMcabvlWwEim2djH7zltpzGxJZyEQ4xK3hqGU3UQHFzbSRYC1aC2FgRCONRncXyKqvxyfy6MdlFuxXo2foa/8BoWT5u7c+cbqUynjNZeyMyreX/E3W1+zQCNynY0zw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561083008; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=oxFkmD9CWtsOJOq7EBRxZJcEMw3GfGZUqh7/P684mSo=; b=JiN2z8eH73Ab6ESQ2N9h+TU/nU9HYxaE+pKUE2idUl8o9Dt91ITxFHTPQijcXXueyTut3lrMzzEU1HsWTuNkSaRiAA2/gcThEsgZnWiCocb6O7daR0cZnYufZPQZDcEcZk6eMtUeZW2NfDpfql15QEjJ5zH9bKjoqAjccUeXrzU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561083008295901.0587034598329; Thu, 20 Jun 2019 19:10:08 -0700 (PDT) Received: from localhost ([::1]:54152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he906-0008Uu-CH for importer@patchew.org; Thu, 20 Jun 2019 22:10:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41291) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1he8a6-0006fA-IM for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1he8a3-0006ge-RA for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:10 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:55301) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1he8a3-0006Ox-2g for qemu-devel@nongnu.org; Thu, 20 Jun 2019 21:43:07 -0400 Received: by mail-wm1-x334.google.com with SMTP id a15so4783864wmj.5 for ; Thu, 20 Jun 2019 18:42:55 -0700 (PDT) Received: from 640k.lan ([93.56.166.5]) by smtp.gmail.com with ESMTPSA id d1sm1123125wru.41.2019.06.20.18.42.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Jun 2019 18:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oxFkmD9CWtsOJOq7EBRxZJcEMw3GfGZUqh7/P684mSo=; b=IJQSDpvjJvprpVHFaJoLNL7fG7gAsqNuFiSziASuJkt5pmvO7EAKeTAgspohRKJS4u A4IZ2Cdxy0I8+9MPLr4yVs2HdcN6tXYcFXkgZSX+eNWLYHYZnkToonC+BWzlqMV+eRtM pchmUeu85RtRdXY0SMesnQRIbW80YNh9WwudfZW6FEtsSqtjYKCUl5tAgxm1t5WKZLfB akqHx3SSFPE7MV8ZRVsGm2GbVp529xg2s3i+tRGSgm2YZXMOqt+zOXKqEXeZpr/s7VpL UztAoxeB17ZY3n7MfQP5h7DFN257wUTzZ8CLC6GzuZVB7V9vUl2KB2UnVRzCJQYMfFeW vhFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=oxFkmD9CWtsOJOq7EBRxZJcEMw3GfGZUqh7/P684mSo=; b=GU48Yvlw+jCR8ILQqHVqTRW8vny/RopY9ANWCO2VMz88SWmAVx46COMQ44djcUghX2 4wIgrq4pvQvA26+h/FZeDgxIYpyV6iilWxml6z7KStb9QFvMkSi/V8oJUvzPncA638IL 8TtUD0LhdP44W5WI1zKnJx2V5LkpNPf7qfcbcEnlQ5Ipx5Q0jwvqFDsbzWGFLqLJKvWA NP36z6wrOdHDVsRtf9Y32eqY4JZptuLgRz/b/owOc9tT2Cxy3EC5fRee+h01O46pLMto 9nieJES3pud1up4MRka5rxupTvDVDrm6lldL0EnUlBIBnnbyEhoZUBO257AffuWqsRdD WY3g== X-Gm-Message-State: APjAAAULeEuB65xjlJtGsXS+PWg2dbA60QsbwFgDwdjMM5fbCfvuwGWT RybWoDWEcedwNsweZnCVbPucftWL X-Google-Smtp-Source: APXvYqzAh80/HgAR3Q+R237U9JPqvE2bsN2GtO/LwhxVYH14KePhcsF+uGwPxN1GMy2OrWX3S6MgmA== X-Received: by 2002:a05:600c:204c:: with SMTP id p12mr1524271wmg.121.1561081374736; Thu, 20 Jun 2019 18:42:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 21 Jun 2019 03:42:27 +0200 Message-Id: <1561081350-3723-23-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> References: <1561081350-3723-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 22/25] target/i386: kvm: Add nested migration blocker only when kernel lacks required capabilities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liran Alon Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Liran Alon Previous commits have added support for migration of nested virtualization workloads. This was done by utilising two new KVM capabilities: KVM_CAP_NESTED_STATE and KVM_CAP_EXCEPTION_PAYLOAD. Both which are required in order to correctly migrate such workloads. Therefore, change code to add a migration blocker for vCPUs exposed with Intel VMX or AMD SVM in case one of these kernel capabilities is missing. Signed-off-by: Liran Alon Reviewed-by: Maran Wilson Message-Id: <20190619162140.133674-11-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 9 +++++++-- target/i386/machine.c | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/i386/kvm.c b/target/i386/kvm.c index ab812b5..f08eab4 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1640,9 +1640,14 @@ int kvm_arch_init_vcpu(CPUState *cs) !!(c->ecx & CPUID_EXT_SMX); } =20 - if (cpu_has_nested_virt(env) && !nested_virt_mig_blocker) { + if (cpu_has_vmx(env) && !nested_virt_mig_blocker && + ((kvm_max_nested_state_length() <=3D 0) || !has_exception_payload)= ) { error_setg(&nested_virt_mig_blocker, - "Nested virtualization does not support live migration = yet"); + "Kernel do not provide required capabilities for " + "nested virtualization migration. " + "(CAP_NESTED_STATE=3D%d, CAP_EXCEPTION_PAYLOAD=3D%d)", + kvm_max_nested_state_length() > 0, + has_exception_payload); r =3D migrate_add_blocker(nested_virt_mig_blocker, &local_err); if (local_err) { error_report_err(local_err); diff --git a/target/i386/machine.c b/target/i386/machine.c index f66f342..e077989 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -233,7 +233,7 @@ static int cpu_pre_save(void *opaque) =20 #ifdef CONFIG_KVM /* Verify we have nested virtualization state from kernel if required = */ - if (cpu_has_nested_virt(env) && !env->nested_state) { + if (kvm_enabled() && cpu_has_vmx(env) && !env->nested_state) { error_report("Guest enabled nested virtualization but kernel " "does not support saving of nested state"); return -EINVAL; --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 23/25] sd: Fix out-of-bounds assertions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lidong Chen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Lidong Chen Due to an off-by-one error, the assert statements allow an out-of-bound array access. This doesn't happen in practice, but the static analyzer notices. Signed-off-by: Lidong Chen Reviewed-by: Liam Merwick Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Li Qiang Reviewed-by: Darren Kenny Message-Id: <6b19cb7359a10a6bedc3ea0fce22fed3ef93c102.1560806687.git.lidong= .chen@oracle.com> Signed-off-by: Paolo Bonzini --- hw/sd/sd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 60500ec..917195a6 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -145,7 +145,7 @@ static const char *sd_state_name(enum SDCardStates stat= e) if (state =3D=3D sd_inactive_state) { return "inactive"; } - assert(state <=3D ARRAY_SIZE(state_name)); + assert(state < ARRAY_SIZE(state_name)); return state_name[state]; } =20 @@ -166,7 +166,7 @@ static const char *sd_response_name(sd_rsp_type_t rsp) if (rsp =3D=3D sd_r1b) { rsp =3D sd_r1; } - assert(rsp <=3D ARRAY_SIZE(response_name)); + assert(rsp < ARRAY_SIZE(response_name)); return response_name[rsp]; } =20 --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PULL 24/25] util/main-loop: Fix incorrect assertion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lidong Chen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Lidong Chen The check for poll_fds in g_assert() was incorrect. The correct assertion should check "n_poll_fds + w->num <=3D ARRAY_SIZE(poll_fds)" because the subsequent for-loop is doing access to poll_fds[n_poll_fds + i] where i is in [0, w->num). This could happen with a very high number of file descriptors and/or wait objects. Signed-off-by: Lidong Chen Suggested-by: Peter Maydell Suggested-by: Liam Merwick Reviewed-by: Liran Alon Reviewed-by: Darren Kenny Reviewed-by: Li Qiang Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: Signed-off-by: Paolo Bonzini --- util/main-loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/main-loop.c b/util/main-loop.c index e1e349c..a9f4e8d 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -422,7 +422,7 @@ static int os_host_main_loop_wait(int64_t timeout) g_main_context_prepare(context, &max_priority); n_poll_fds =3D g_main_context_query(context, max_priority, &poll_timeo= ut, poll_fds, ARRAY_SIZE(poll_fds)); - g_assert(n_poll_fds <=3D ARRAY_SIZE(poll_fds)); + g_assert(n_poll_fds + w->num <=3D ARRAY_SIZE(poll_fds)); =20 for (i =3D 0; i < w->num; i++) { poll_fds[n_poll_fds + i].fd =3D (DWORD_PTR)w->events[i]; --=20 1.8.3.1 From nobody Sat Sep 27 23:43:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 25/25] hw: Nuke hw_compat_4_0_1 and pc_compat_4_0_1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greg Kurz Commit c87759ce876a fixed a regression affecting pc-q35 machines by introducing a new pc-q35-4.0.1 machine version to be used instead of pc-q35-4.0. The only purpose was to revert the default behaviour of not using split irqchip, but the change also introduced the usual hw_compat and pc_compat bits, and wired them for pc-q35 only. This raises questions when it comes to add new compat properties for 4.0* machine versions of any architecture. Where to add them ? In 4.0, 4.0.1 or both ? Error prone. Another possibility would be to teach all other architectures about 4.0.1. This solution isn't satisfying, especially since this is a pc-q35 specific issue. It turns out that the split irqchip default is handled in the machine option function and doesn't involve compat lists at all. Drop all the 4.0.1 compat lists and use the 4.0 ones instead in the 4.0.1 machine option function. Move the compat props that were added to the 4.0.1 since c87759ce876a to 4.0. Even if only hw_compat_4_0_1 had an impact on other architectures, drop pc_compat_4_0_1 as well for consistency. Fixes: c87759ce876a "q35: Revert to kernel irqchip" Suggested-by: Dr. David Alan Gilbert Signed-off-by: Greg Kurz Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Michael S. Tsirkin Message-Id: <156051774276.244890.8660277280145466396.stgit@bahia.lan> Signed-off-by: Paolo Bonzini --- hw/core/machine.c | 5 +---- hw/i386/pc.c | 3 --- hw/i386/pc_q35.c | 12 ++++++++---- include/hw/boards.h | 3 --- include/hw/i386/pc.h | 3 --- 5 files changed, 9 insertions(+), 17 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index 84ebb8d..ea5a01a 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -24,16 +24,13 @@ #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" =20 -GlobalProperty hw_compat_4_0_1[] =3D { +GlobalProperty hw_compat_4_0[] =3D { { "VGA", "edid", "false" }, { "secondary-vga", "edid", "false" }, { "bochs-display", "edid", "false" }, { "virtio-vga", "edid", "false" }, { "virtio-gpu-pci", "edid", "false" }, }; -const size_t hw_compat_4_0_1_len =3D G_N_ELEMENTS(hw_compat_4_0_1); - -GlobalProperty hw_compat_4_0[] =3D {}; const size_t hw_compat_4_0_len =3D G_N_ELEMENTS(hw_compat_4_0); =20 GlobalProperty hw_compat_3_1[] =3D { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e41192b..e96360b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -111,9 +111,6 @@ struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MA= X}; /* Physical Address of PVH entry point read from kernel ELF NOTE */ static size_t pvh_start_addr; =20 -GlobalProperty pc_compat_4_0_1[] =3D {}; -const size_t pc_compat_4_0_1_len =3D G_N_ELEMENTS(pc_compat_4_0_1); - GlobalProperty pc_compat_4_0[] =3D {}; const size_t pc_compat_4_0_len =3D G_N_ELEMENTS(pc_compat_4_0); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index dcddc64..57232ae 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -378,8 +378,13 @@ static void pc_q35_4_0_1_machine_options(MachineClass = *m) { pc_q35_4_1_machine_options(m); m->alias =3D NULL; - compat_props_add(m->compat_props, hw_compat_4_0_1, hw_compat_4_0_1_len= ); - compat_props_add(m->compat_props, pc_compat_4_0_1, pc_compat_4_0_1_len= ); + /* + * This is the default machine for the 4.0-stable branch. It is basica= lly + * a 4.0 that doesn't use split irqchip by default. It MUST hence appl= y the + * 4.0 compat props. + */ + compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); + compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); } =20 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL, @@ -390,8 +395,7 @@ static void pc_q35_4_0_machine_options(MachineClass *m) pc_q35_4_0_1_machine_options(m); m->default_kernel_irqchip_split =3D true; m->alias =3D NULL; - compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len); - compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len); + /* Compat props are applied by the 4.0.1 machine */ } =20 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL, diff --git a/include/hw/boards.h b/include/hw/boards.h index b7362af..eaa050a 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -293,9 +293,6 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 -extern GlobalProperty hw_compat_4_0_1[]; -extern const size_t hw_compat_4_0_1_len; - extern GlobalProperty hw_compat_4_0[]; extern const size_t hw_compat_4_0_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index a7d0b87..c54cc54 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -293,9 +293,6 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); =20 -extern GlobalProperty pc_compat_4_0_1[]; -extern const size_t pc_compat_4_0_1_len; - extern GlobalProperty pc_compat_4_0[]; extern const size_t pc_compat_4_0_len; =20 --=20 1.8.3.1