From nobody Tue Nov 11 03:14:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1561029196; cv=none; d=zoho.com; s=zohoarc; b=kGwDGx8uujtp9BzXwkp8l8AhS70rdZqyfp1v00RlzHz8gRjIAvIDod6SU9W9n1yhJAbkntxN02+vt3Lkzoy+M3NHDmjIUpGwy9/8t/NH+BDlDnKomOurNPZVbtoMak8wx+OrwbDf3Mos57Vb2V6OiuUZHIRrm499jkwnz7uDw0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561029196; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=deJV9TN4CD6E3nUSFFs6gkX62vz8zy5WmRwao0yEYHU=; b=gqAYs/Jch/OrdSN4pJFE1CHxVsKwBaXJKTnQoXZtudxuBIxVv5vhZ9is9E4P6m61ov7VJc8S6a4yVaS3IHvWj+RmEx4MZ2hQ4Y2cSnQ7GAUAEmbY0zVyxVViLtJWAaXDX+P3dCo/aOSgT3KVjUoIlNm6htSZ/IR2WyJxmHZkfxk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561029196797384.5281919945352; Thu, 20 Jun 2019 04:13:16 -0700 (PDT) Received: from localhost ([::1]:46262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdv06-0002nG-Mp for importer@patchew.org; Thu, 20 Jun 2019 07:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42330) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdujm-0007BQ-62 for qemu-devel@nongnu.org; Thu, 20 Jun 2019 06:56:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdujh-0005rm-RT for qemu-devel@nongnu.org; Thu, 20 Jun 2019 06:56:13 -0400 Received: from mga09.intel.com ([134.134.136.24]:2139) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hdujh-0005hh-Ix for qemu-devel@nongnu.org; Thu, 20 Jun 2019 06:56:09 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 03:55:55 -0700 Received: from liujing-dell.bj.intel.com ([10.238.145.70]) by orsmga001.jf.intel.com with ESMTP; 20 Jun 2019 03:55:54 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,396,1557212400"; d="scan'208";a="243591694" From: Jing Liu To: qemu-devel@nongnu.org, pbonzini@redhat.com Date: Thu, 20 Jun 2019 19:00:18 +0800 Message-Id: <1561028418-11248-1-git-send-email-jing2.liu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.24 Subject: [Qemu-devel] [PATCH RFC] x86: BFloat16 feature enabling on Cooper Lake X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jing2.liu@linux.intel.com, jing2.liu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Intel CooperLake cpu adds AVX512_BF16 instruction, defining as CPUID.(EAX=3D7,EXC=3D1):EAX[bit 05]. The release spec link as follows, https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jing Liu --- target/i386/cpu.c | 46 +++++++++++++++++++++++++++++++++++++++------- target/i386/cpu.h | 3 +++ target/i386/kvm.c | 3 ++- 3 files changed, 44 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c1ab86d..249f7f9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -664,6 +664,9 @@ static CPUCacheInfo legacy_l3_cache =3D { #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 =20 +/* CPUID Leaf 0x07 constants: */ +#define INTEL_LEAF_7_MAX_SUBLEAF 0x1 + /* CPUID Leaf 0x14 constants: */ #define INTEL_PT_MAX_SUBLEAF 0x1 /* @@ -767,6 +770,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_= t vendor1, /* CPUID_7_0_ECX_OSPKE is dynamic */ \ CPUID_7_0_ECX_LA57) #define TCG_7_0_EDX_FEATURES 0 +#define TCG_7_1_EAX_FEATURES 0 #define TCG_APM_FEATURES 0 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) @@ -1092,6 +1096,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D TCG_7_0_EDX_FEATURES, }, + [FEAT_7_1_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, "avx512-bf16", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, + }, + .tcg_features =3D TCG_7_1_EAX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -4343,19 +4366,28 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, break; case 7: /* Structured Extended Feature Flags Enumeration Leaf */ - if (count =3D=3D 0) { - *eax =3D 0; /* Maximum ECX value for sub-leaves */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + + switch (count) { + case 0: + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_AVX512_BF16) { + *eax =3D INTEL_LEAF_7_MAX_SUBLEAF; /* Maximum ECX value fo= r sub-leaves */ + } *ebx =3D env->features[FEAT_7_0_EBX]; /* Feature flags */ *ecx =3D env->features[FEAT_7_0_ECX]; /* Feature flags */ if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { *ecx |=3D CPUID_7_0_ECX_OSPKE; } *edx =3D env->features[FEAT_7_0_EDX]; /* Feature flags */ - } else { - *eax =3D 0; - *ebx =3D 0; - *ecx =3D 0; - *edx =3D 0; + break; + case 1: + *eax =3D env->features[FEAT_7_1_EAX]; + break; + default: + break; } break; case 9: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bd06523..40594a1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -488,6 +488,7 @@ typedef enum FeatureWord { FEAT_7_0_EBX, /* CPUID[EAX=3D7,ECX=3D0].EBX */ FEAT_7_0_ECX, /* CPUID[EAX=3D7,ECX=3D0].ECX */ FEAT_7_0_EDX, /* CPUID[EAX=3D7,ECX=3D0].EDX */ + FEAT_7_1_EAX, /* CPUID[EAX=3D7,ECX=3D1].EAX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ @@ -699,6 +700,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypa= ss Disable */ =20 +#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction= */ + #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and = do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Predicti= on Barrier */ diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 3b29ce5..977aaa5 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1110,6 +1110,7 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; + case 0x7: case 0x14: { uint32_t times; =20 @@ -1122,7 +1123,7 @@ int kvm_arch_init_vcpu(CPUState *cs) for (j =3D 1; j <=3D times; ++j) { if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { fprintf(stderr, "cpuid_data is full, no space for " - "cpuid(eax:0x14,ecx:0x%x)\n", j); + "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); abort(); } c =3D &cpuid_data.entries[cpuid_i++]; --=20 1.8.3.1