From nobody Tue Nov 11 05:03:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1561024046; cv=none; d=zoho.com; s=zohoarc; b=OSbPPgaO9zqQ/lBDyGr/4gHNN99JaT1Cn0nU2vyjjr/nt5DOsqK1ahIiTC95nbsOhCETkbHjjKh2Ju0KyOBzUcLz+XRzlF9OjytTWtPjnhTo8vdVNM0s/fAI7ClYGn9iHsM6dZy0IYF/AGFOjN3FjEaFYaPWJkgNIr12FCYWiDk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561024046; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=yoHaiMkRsomuHRC68pH2e1akFdwLjlL2suc0YxeDUbo=; b=W5rGKrirgr/awmhBbIFMLisxTopY+wH0HQ+hco1AX87WyY067P6J8Bo6yhn8QxUoGCq5I12cv7uFAml7bZ7uldgpfoivRtv3MohowuCt8f70xX7iZWqdwA+NU/6CxAJTXx9Kl6FwEtSuB1J2wa9MwwBL4mKNHA0rRfw7SmR62RQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1561024046209877.6491843715386; Thu, 20 Jun 2019 02:47:26 -0700 (PDT) Received: from localhost ([::1]:45478 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdtf9-000158-8T for importer@patchew.org; Thu, 20 Jun 2019 05:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45793) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hdtF0-0004Zt-I5 for qemu-devel@nongnu.org; Thu, 20 Jun 2019 05:20:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hdtEw-00010Y-Ng for qemu-devel@nongnu.org; Thu, 20 Jun 2019 05:20:22 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:35460 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hdtEt-0000wC-KW for qemu-devel@nongnu.org; Thu, 20 Jun 2019 05:20:17 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id CCDF61A4663; Thu, 20 Jun 2019 11:20:12 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 95AA51A23C4; Thu, 20 Jun 2019 11:20:12 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 20 Jun 2019 11:19:56 +0200 Message-Id: <1561022396-20649-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561022396-20649-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1561022396-20649-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms checkpatch errors in translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove if-else-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 106 ++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 66 insertions(+), 40 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 324b32a..3558b2e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] =3D { /* General purpose registers moves. */ static inline void gen_load_gpr(TCGv t, int reg) { - if (reg =3D=3D 0) + if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); - else + } else { tcg_gen_mov_tl(t, cpu_gpr[reg]); + } } =20 static inline void gen_store_gpr(TCGv t, int reg) { - if (reg !=3D 0) + if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); + } } =20 /* Moves to/from shadow registers. */ @@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to) { TCGv t0 =3D tcg_temp_new(); =20 - if (from =3D=3D 0) + if (from =3D=3D 0) { tcg_gen_movi_tl(t0, 0); - else { + } else { TCGv_i32 t2 =3D tcg_temp_new_i32(); TCGv_ptr addr =3D tcg_temp_new_ptr(); =20 @@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv= _i64 t, int reg) =20 static inline int get_fp_bit(int cc) { - if (cc) + if (cc) { return 24 + cc; - else + } else { return 23; + } } =20 /* Addresses computation */ @@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i= 64 arg) =20 static inline void check_cp0_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_err(ctx, EXCP_CpU, 0); + } } =20 static inline void check_cp1_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); + } } =20 /* Verify that the processor is running with COP1X instructions enabled. @@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ct= x) =20 static inline void check_cop1x(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* Verify that the processor is running with 64-bit floating-point @@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx) =20 static inline void check_cp1_64bitmode(DisasContext *ctx) { - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* @@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext *= ctx) */ static inline void check_cp1_registers(DisasContext *ctx, int regs) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* Verify that the processor is running with DSP instructions enabled. @@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx) instructions are not enabled. */ static inline void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { generate_exception_end(ctx, EXCP_RI); + } } #endif =20 @@ -3131,8 +3140,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && - !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) - { + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) { generate_exception_end(ctx, EXCP_RI); } } @@ -3882,22 +3890,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32= _t opc, uimm =3D (uint16_t)imm; switch (opc) { case OPC_ANDI: - if (likely(rs !=3D 0)) + if (likely(rs !=3D 0)) { tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], 0); + } break; case OPC_ORI: - if (rs !=3D 0) + if (rs !=3D 0) { tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_XORI: - if (likely(rs !=3D 0)) + if (likely(rs !=3D 0)) { tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_LUI: if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS32R6)) { @@ -6060,8 +6071,9 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, } =20 out: - if (insn_bytes =3D=3D 2) + if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; + } tcg_temp_free(t0); tcg_temp_free(t1); } @@ -6708,8 +6720,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS32); + } =20 switch (reg) { case CP0_REGISTER_00: @@ -7464,8 +7477,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS32); + } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -8210,8 +8224,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS64); + } =20 switch (reg) { case CP0_REGISTER_00: @@ -8920,8 +8935,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS64); + } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -10162,8 +10178,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_TLBWI: opn =3D "tlbwi"; - if (!env->tlb->helper_tlbwi) + if (!env->tlb->helper_tlbwi) { goto die; + } gen_helper_tlbwi(cpu_env); break; case OPC_TLBINV: @@ -10186,20 +10203,23 @@ static void gen_cp0(CPUMIPSState *env, DisasConte= xt *ctx, uint32_t opc, break; case OPC_TLBWR: opn =3D "tlbwr"; - if (!env->tlb->helper_tlbwr) + if (!env->tlb->helper_tlbwr) { goto die; + } gen_helper_tlbwr(cpu_env); break; case OPC_TLBP: opn =3D "tlbp"; - if (!env->tlb->helper_tlbp) + if (!env->tlb->helper_tlbp) { goto die; + } gen_helper_tlbp(cpu_env); break; case OPC_TLBR: opn =3D "tlbr"; - if (!env->tlb->helper_tlbr) + if (!env->tlb->helper_tlbr) { goto die; + } gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ @@ -10273,8 +10293,9 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, goto out; } =20 - if (cc !=3D 0) + if (cc !=3D 0) { check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + } =20 btarget =3D ctx->base.pc_next + 4 + offset; =20 @@ -10728,10 +10749,11 @@ static void gen_movci(DisasContext *ctx, int rd, = int rs, int cc, int tf) return; } =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 l1 =3D gen_new_label(); t0 =3D tcg_temp_new_i32(); @@ -10753,10 +10775,11 @@ static inline void gen_movcf_s(DisasContext *ctx,= int fs, int fd, int cc, TCGv_i32 t0 =3D tcg_temp_new_i32(); TCGLabel *l1 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10774,10 +10797,11 @@ static inline void gen_movcf_d(DisasContext *ctx,= int fs, int fd, int cc, TCGv_i64 fp0; TCGLabel *l1 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10797,10 +10821,11 @@ static inline void gen_movcf_ps(DisasContext *ctx= , int fs, int fd, TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -12096,8 +12121,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; =20 - if (ft !=3D 0) + if (ft !=3D 0) { tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); --=20 2.7.4