From nobody Tue Nov 11 00:23:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.47 as permitted sender) client-ip=209.51.188.47; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.47 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559906029; cv=none; d=zoho.com; s=zohoarc; b=B0ih8oTR8KJ6bRlXLHvfmqBXtqoHlzyOtggM0kX37cOLA56VUPHVT5w9VkmCGc0jUoKAYboTWuToKhXi1hXnnJ5RvEjp79Ud9PR2UmlKQP02KJqXKbJXB4mZkQFti5FEQf3kDHcFSCUpHFsT4Ll+5FUXGoF1Rfd/J8L9d2XWYDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559906029; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=mwHSP2aKIk/ePrpwAM9CZlycMXOf0eSC4nQx8rypyVA=; b=jPVpMyiZDo/A0s/1p213UOyhnpn8DKSLhijGq6MhsAjJRpUDSaL9dgxtt54ZouCF48vQWR+6vb6d8ZXaf7KPrTIX6KvLkk1KrAABvynq06jxYJCuisXnzglQiim22wDUDvqaueJoRIPJfDOVB/kLyiFEDei9uZIczWHx0Xxl4YY= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.47 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.47]) by mx.zohomail.com with SMTPS id 155990602896377.22212646092714; Fri, 7 Jun 2019 04:13:48 -0700 (PDT) Received: from localhost ([::1]:48482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hZCoZ-0002hp-U8 for importer@patchew.org; Fri, 07 Jun 2019 07:13:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59517) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hZBl6-0003sv-Ih for qemu-devel@nongnu.org; Fri, 07 Jun 2019 06:06:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hZBl5-0008AN-5U for qemu-devel@nongnu.org; Fri, 07 Jun 2019 06:06:04 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:50158 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hZBl3-0007v7-3a for qemu-devel@nongnu.org; Fri, 07 Jun 2019 06:06:02 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 038411A1CF9; Fri, 7 Jun 2019 12:05:50 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D56501A1D0E; Fri, 7 Jun 2019 12:05:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 7 Jun 2019 12:05:36 +0200 Message-Id: <1559901944-4578-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559901944-4578-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1559901944-4578-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 02/10] target/mips: Fix block-comment-related issues in msa_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com> --- target/mips/msa_helper.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index eacb5a4..851450c 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1975,8 +1975,10 @@ static inline int update_msacsr(CPUMIPSState *env, i= nt action, int denormal) c &=3D ~FP_UNDERFLOW; } =20 - /* Reciprocal operations set only Inexact when valid and not - divide by zero */ + /* + * Reciprocal operations set only Inexact when valid and not + * divide by zero + */ if ((action & RECIPROCAL_INEXACT) && (c & (FP_INVALID | FP_DIV0)) =3D=3D 0) { c =3D FP_INEXACT; @@ -1985,15 +1987,19 @@ static inline int update_msacsr(CPUMIPSState *env, = int action, int denormal) cause =3D c & enable; /* all current enabled exceptions */ =20 if (cause =3D=3D 0) { - /* No enabled exception, update the MSACSR Cause - with all current exceptions */ + /* + * No enabled exception, update the MSACSR Cause + * with all current exceptions + */ SET_FP_CAUSE(env->active_tc.msacsr, (GET_FP_CAUSE(env->active_tc.msacsr) | c)); } else { /* Current exceptions are enabled */ if ((env->active_tc.msacsr & MSACSR_NX_MASK) =3D=3D 0) { - /* Exception(s) will trap, update MSACSR Cause - with all enabled exceptions */ + /* + * Exception(s) will trap, update MSACSR Cause + * with all enabled exceptions + */ SET_FP_CAUSE(env->active_tc.msacsr, (GET_FP_CAUSE(env->active_tc.msacsr) | c)); } @@ -3059,9 +3065,11 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, switch (df) { case DF_WORD: for (i =3D 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee =3D 1; =20 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16); @@ -3617,9 +3625,11 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, switch (df) { case DF_WORD: for (i =3D 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee =3D 1; =20 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32); @@ -3651,9 +3661,11 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, switch (df) { case DF_WORD: for (i =3D 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee =3D 1; =20 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32); --=20 2.7.4