From nobody Mon Nov 10 22:30:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559829088; cv=none; d=zoho.com; s=zohoarc; b=i56dxS3hRJwAbwMx7qzx5+jwbofQXOYz3xf5KgWIGqKwR8c9VrZKvE/yxNGIE55XvAlJxYyc7h1J3HhXq0Dfhm7FTDPBLReiAhqid54dtBrary/0k22VnW13faUkTdIvL8IG0BMQyFjZUcyGLp0xgSMmPBRqCBrcDe1sDIQ7Pi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559829088; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=na5yikJjFlzNrpDrKNZMTSVXjMSoytgRMqsPoHNTmeU=; b=h41u3iVHO7G5+eZK+JxXQAY5I4Oj/GI4QhOxifQyxwfMlWtVnu3P/8LmFHLPwak0Z882dFoBfJSTlbNI67YWzeFvx+phFcSZdiq+dOBaiR8FG67NmtrpNFrWfUzTqClVLDuiSfpWZZPc2qXZ12Cczm9ThEKJIfttXdgHx07zkAk= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559829088064949.0544347078564; Thu, 6 Jun 2019 06:51:28 -0700 (PDT) Received: from localhost ([127.0.0.1]:60920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYsnc-0007xM-HY for importer@patchew.org; Thu, 06 Jun 2019 09:51:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:44164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYsl1-0006LM-Ej for qemu-devel@nongnu.org; Thu, 06 Jun 2019 09:48:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYsj4-0000vT-Ol for qemu-devel@nongnu.org; Thu, 06 Jun 2019 09:46:44 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:56649 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYsj4-0003UY-E9 for qemu-devel@nongnu.org; Thu, 06 Jun 2019 09:46:42 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A5DC21A21B6; Thu, 6 Jun 2019 15:45:36 +0200 (CEST) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.110]) by mail.rt-rk.com (Postfix) with ESMTPSA id 814571A21AF; Thu, 6 Jun 2019 15:45:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 15:45:32 +0200 Message-Id: <1559828732-23081-2-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559828732-23081-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1559828732-23081-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH] target/mips: Add implementation of DSPRAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, aurelien@aurel32.net, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add support for DSPRAM (Data Scratch Pad RAM). It still needs some minor fixing, but the structure is right. Signed-off-by: Mateja Marjanovic --- default-configs/mips-softmmu-common.mak | 1 + hw/mips/cps.c | 28 +++++- hw/misc/Makefile.objs | 1 + hw/misc/mips_dspram.c | 153 ++++++++++++++++++++++++++++= ++++ include/hw/mips/cps.h | 2 + include/hw/misc/mips_dspram.h | 46 ++++++++++ target/mips/cpu.h | 9 +- target/mips/internal.h | 3 +- target/mips/op_helper.c | 14 +++ target/mips/translate.c | 8 ++ target/mips/translate_init.inc.c | 2 + 11 files changed, 262 insertions(+), 5 deletions(-) create mode 100644 hw/misc/mips_dspram.c create mode 100644 include/hw/misc/mips_dspram.h diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips= -softmmu-common.mak index ded7498..d3f85b0 100644 --- a/default-configs/mips-softmmu-common.mak +++ b/default-configs/mips-softmmu-common.mak @@ -35,6 +35,7 @@ CONFIG_ISA_TESTDEV=3Dy CONFIG_EMPTY_SLOT=3Dy CONFIG_MIPS_CPS=3Dy CONFIG_MIPS_ITU=3Dy +CONFIG_MIPS_DSPRAM=3Dy CONFIG_I2C=3Dy CONFIG_R4K=3Dy CONFIG_MALTA=3Dy diff --git a/hw/mips/cps.c b/hw/mips/cps.c index fc97f59..0205556 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -90,7 +90,8 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) =20 cpu =3D MIPS_CPU(first_cpu); env =3D &cpu->env; - saar_present =3D (bool)env->saarp; + saar_present =3D env->saarp; + bool dspram_present =3D env->dspramp; =20 /* Inter-Thread Communication Unit */ if (itu_present) { @@ -102,7 +103,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", &err); if (saar_present) { - qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_S= AAR); + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", + (void *) &env->CP0_SAAR[0]); } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { @@ -113,6 +115,28 @@ static void mips_cps_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu),= 0)); } + env->dspram =3D g_new0(MIPSDSPRAMState, 1); + + /* Data Scratch Pad RAM */ + if (dspram_present) { + if (!saar_present) { + error_report("%s: DSPRAM requires SAAR registers", __func__); + return; + } + object_initialize(&s->dspram, sizeof(MIPSDSPRAMState), + TYPE_MIPS_DSPRAM); + qdev_set_parent_bus(DEVICE(&s->dspram), sysbus_get_default()); + qdev_prop_set_ptr(DEVICE(&s->dspram), "saar", + &env->CP0_SAAR[1]); + object_property_set_bool(OBJECT(&s->dspram), true, "realized", &er= r); + if (err !=3D NULL) { + error_report("%s: DSPRAM initialisation failed", __func__); + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dspram), 0)); + } =20 /* Cluster Power Controller */ object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 74c91d2..37c4108 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o obj-$(CONFIG_MIPS_ITU) +=3D mips_itu.o +obj-$(CONFIG_MIPS_DSPRAM) +=3D mips_dspram.o obj-$(CONFIG_MPS2_FPGAIO) +=3D mps2-fpgaio.o obj-$(CONFIG_MPS2_SCC) +=3D mps2-scc.o =20 diff --git a/hw/misc/mips_dspram.c b/hw/misc/mips_dspram.c new file mode 100644 index 0000000..9bc155b --- /dev/null +++ b/hw/misc/mips_dspram.c @@ -0,0 +1,153 @@ +/* + * Data Scratch Pad RAM + * + * Copyright (c) 2017 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu/log.h" +#include "exec/exec-all.h" +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "sysemu/sysemu.h" +#include "hw/misc/mips_dspram.h" + +static void raise_exception(int excp) +{ + current_cpu->exception_index =3D excp; + cpu_loop_exit(current_cpu); +} + +static uint64_t dspram_read(void *opaque, hwaddr addr, unsigned size) +{ + MIPSDSPRAMState *s =3D (MIPSDSPRAMState *)opaque; + + switch (size) { + case 1: + case 2: + raise_exception(EXCP_AdEL); + return 0; + case 4: + return *(uint32_t *) &s->ramblock[addr % (1 << s->size)]; + case 8: + return *(uint64_t *) &s->ramblock[addr % (1 << s->size)]; + } + return 0; +} + +static void dspram_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) +{ + MIPSDSPRAMState *s =3D (MIPSDSPRAMState *)opaque; + + switch (size) { + case 1: + case 2: + raise_exception(EXCP_AdES); + return; + case 4: + *(uint32_t *) &s->ramblock[addr % (1 << s->size)] =3D (uint32_t) d= ata; + break; + case 8: + *(uint64_t *) &s->ramblock[addr % (1 << s->size)] =3D data; + break; + } +} + +void dspram_reconfigure(struct MIPSDSPRAMState *dspram) +{ + MemoryRegion *mr =3D &dspram->mr; + hwaddr address; + bool is_enabled; + + address =3D ((*(uint64_t *) dspram->saar) & 0xFFFFFFFE000ULL) << 4; + is_enabled =3D *(uint64_t *) dspram->saar & 1; + + memory_region_transaction_begin(); + memory_region_set_size(mr, (1 << dspram->size)); + memory_region_set_address(mr, address); + memory_region_set_enabled(mr, is_enabled); + memory_region_transaction_commit(); +} + +static const MemoryRegionOps dspram_ops =3D { + .read =3D dspram_read, + .write =3D dspram_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .unaligned =3D false, + } +}; + +static void mips_dspram_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + MIPSDSPRAMState *s =3D MIPS_DSPRAM(obj); + + memory_region_init_io(&s->mr, OBJECT(s), &dspram_ops, s, + "mips-dspram", (1 << s->size)); + sysbus_init_mmio(sbd, &s->mr); +} + +static void mips_dspram_realize(DeviceState *dev, Error **errp) +{ + MIPSDSPRAMState *s =3D MIPS_DSPRAM(dev); + + /* some error handling here */ + + s->ramblock =3D g_malloc0(1 << s->size); +} + +static void mips_dspram_reset(DeviceState *dev) +{ + MIPSDSPRAMState *s =3D MIPS_DSPRAM(dev); + + *(uint64_t *) s->saar =3D s->size << 1; + memset(s->ramblock, 0, (1 << s->size)); +} + +static Property mips_dspram_properties[] =3D { + DEFINE_PROP_PTR("saar", MIPSDSPRAMState, saar), + /* default DSPRAM size is 64 KB */ + DEFINE_PROP_SIZE("size", MIPSDSPRAMState, size, 0x10), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mips_dspram_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D mips_dspram_properties; + dc->realize =3D mips_dspram_realize; + dc->reset =3D mips_dspram_reset; +} + +static const TypeInfo mips_dspram_info =3D { + .name =3D TYPE_MIPS_DSPRAM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MIPSDSPRAMState), + .instance_init =3D mips_dspram_init, + .class_init =3D mips_dspram_class_init, +}; + +static void mips_dspram_register_types(void) +{ + type_register_static(&mips_dspram_info); +} + +type_init(mips_dspram_register_types); diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index aab1af9..a637036 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -25,6 +25,7 @@ #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" #include "hw/misc/mips_itu.h" +#include "hw/misc/mips_dspram.h" =20 #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -41,6 +42,7 @@ typedef struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + MIPSDSPRAMState dspram; } MIPSCPSState; =20 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/include/hw/misc/mips_dspram.h b/include/hw/misc/mips_dspram.h new file mode 100644 index 0000000..ee99e17 --- /dev/null +++ b/include/hw/misc/mips_dspram.h @@ -0,0 +1,46 @@ +/* + * Data Scratch Pad RAM + * + * Copyright (c) 2017 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef MIPS_DSPRAM_H +#define MIPS_DSPRAM_H + +#include "hw/sysbus.h" + +#define TYPE_MIPS_DSPRAM "mips-dspram" +#define MIPS_DSPRAM(obj) OBJECT_CHECK(MIPSDSPRAMState, (obj), TYPE_MIPS_DS= PRAM) + +typedef struct MIPSDSPRAMState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /* 2 ^ SIZE */ + uint64_t size; + + MemoryRegion mr; + + /* SAAR */ + bool saar_present; + void *saar; + + /* ramblock */ + uint8_t *ramblock; +} MIPSDSPRAMState; + +#endif /* MIPS_DSPRAM_H */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0..8b15e6c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -445,6 +445,7 @@ struct TCState { =20 }; =20 +struct MIPSDSPRAMState; struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { @@ -1021,8 +1022,8 @@ struct CPUMIPSState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ - int saarp; - + bool saarp; + bool dspramp; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 @@ -1039,6 +1040,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ + struct MIPSDSPRAMState *dspram; target_ulong exception_base; /* ExceptionBase input to the core */ }; =20 @@ -1181,6 +1183,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); =20 +/* mips_dspram.c */ +void dspram_reconfigure(struct MIPSDSPRAMState *dspram); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index 8f6fc91..650bddd 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -61,7 +61,8 @@ struct mips_def_t { target_ulong CP0_EBaseWG_rw_bitmask; uint64_t insn_flags; enum mips_mmu_types mmu_type; - int32_t SAARP; + bool SAARP; + bool DSPRAMP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index c921032..5136e33 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1614,7 +1614,14 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } + } else { + helper_raise_exception(env, EXCP_RI); } } =20 @@ -1631,7 +1638,14 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } + } else { + helper_raise_exception(env, EXCP_RI); } } =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index c79fa1e..40584e9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31383,6 +31383,8 @@ void cpu_state_reset(CPUMIPSState *env) env->active_fpu.fcr31 =3D env->cpu_model->CP1_fcr31; env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; + env->saarp =3D env->cpu_model->SAARP; + env->dspramp =3D env->cpu_model->DSPRAMP; =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); @@ -31537,6 +31539,12 @@ void cpu_state_reset(CPUMIPSState *env) msa_reset(env); } =20 + /* DSPRAM */ + if (env->dspramp) { + /* Fixed DSPRAM size with Default Value */ + env->CP0_SAAR[1] =3D 0x10 << 1; + } + compute_hflags(env); restore_fp_status(env); restore_pamask(env); diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index bf559af..4c49a0e 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -760,6 +760,8 @@ const mips_def_t mips_defs[] =3D .PABITS =3D 48, .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, .mmu_type =3D MMU_TYPE_R4000, + .SAARP =3D 1, + .DSPRAMP =3D 1, }, { .name =3D "Loongson-2E", --=20 2.7.4