From nobody Tue Feb 10 02:43:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559816632; cv=none; d=zoho.com; s=zohoarc; b=m6seVvdNdgFQRy8hLGlweCM9gZKkiRC3NXh0InKpDlPWMhHOlAfFVtoNjKs1A6+6WdGPQFM6McPSSYx4G+rtQNZiD5nbJgP9/k4SjyjiwMS81keL7R8C6ewV0BDR71QsRepGFocLMAkyr6fwB3pxonso34K92YqVDFtuCpirHf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559816632; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XyMlCu3bJAe/gQQy7WGczY07rQ78v09ybItddONvY7Q=; b=LmP43xg86pR2geohyitiFHjPegsMwUHxHSjD9bvy9hPeCB9hKkQbg+n9OMhphDrfh3AohsjK2u7DLiKYtt0PsgQVJtTzZoSlxRPQBAPu7f367rR7KMWdIwVgdMnPqozu/eERXJfBDwhBfcE5FS0DlmN9jq6CP/i7L0Tu9AV1K8w= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559816632235705.6761925381064; Thu, 6 Jun 2019 03:23:52 -0700 (PDT) Received: from localhost ([127.0.0.1]:57861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYpYk-00080e-U8 for importer@patchew.org; Thu, 06 Jun 2019 06:23:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:50057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYpRx-0002ar-Uk for qemu-devel@nongnu.org; Thu, 06 Jun 2019 06:16:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYpRw-0001zv-Cl for qemu-devel@nongnu.org; Thu, 06 Jun 2019 06:16:49 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41537 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hYpRw-0001tp-0v for qemu-devel@nongnu.org; Thu, 06 Jun 2019 06:16:48 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1417A1A1DE5; Thu, 6 Jun 2019 12:15:37 +0200 (CEST) Received: from rtrkw870-lin.domain.local (rtrkw870-lin.domain.local [10.10.13.132]) by mail.rt-rk.com (Postfix) with ESMTPSA id EB2251A1E45; Thu, 6 Jun 2019 12:15:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Brankovic To: qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 12:15:30 +0200 Message-Id: <1559816130-17113-9-git-send-email-stefan.brankovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559816130-17113-1-git-send-email-stefan.brankovic@rt-rk.com> References: <1559816130-17113-1-git-send-email-stefan.brankovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 8/8] target/ppc: Refactor emulation of vmrgew and vmrgow instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since I found this two instructions implemented with tcg, I refactored them so they are consistent with other similar implementations that I introduced in this patch. Also had to add new dual macro GEN_VXFORM_TRANS_DUAL. We use this macro if one instruction is realized with direct translation, and second one with helper. Signed-off-by: Stefan Brankovic --- target/ppc/translate/vmx-impl.inc.c | 62 ++++++++++++++++++++-------------= ---- 1 file changed, 33 insertions(+), 29 deletions(-) diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx= -impl.inc.c index 8535a31..46c6f34 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -350,6 +350,24 @@ static void glue(gen_, name0##_##name1)(DisasContext *= ctx) \ } \ } =20 +/* + * We use this macro if one instruction is realized with direct + * translation, and second one with helper. + */ +#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\ +static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ +{ \ + if ((Rc(ctx->opcode) =3D=3D 0) && = \ + ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ + trans_##name0(ctx); \ + } else if ((Rc(ctx->opcode) =3D=3D 1) && = \ + ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ + gen_##name1(ctx); \ + } else { \ + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ + } \ +} + /* Adds support to provide invalid mask */ #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \ name1, flg1, flg2_1, inval1) \ @@ -431,20 +449,13 @@ GEN_VXFORM(vmrglb, 6, 4); GEN_VXFORM(vmrglh, 6, 5); GEN_VXFORM(vmrglw, 6, 6); =20 -static void gen_vmrgew(DisasContext *ctx) +static void trans_vmrgew(DisasContext *ctx) { - TCGv_i64 tmp; - TCGv_i64 avr; - int VT, VA, VB; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - VT =3D rD(ctx->opcode); - VA =3D rA(ctx->opcode); - VB =3D rB(ctx->opcode); - tmp =3D tcg_temp_new_i64(); - avr =3D tcg_temp_new_i64(); + int VT =3D rD(ctx->opcode); + int VA =3D rA(ctx->opcode); + int VB =3D rB(ctx->opcode); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 avr =3D tcg_temp_new_i64(); =20 get_avr64(avr, VB, true); tcg_gen_shri_i64(tmp, avr, 32); @@ -462,21 +473,14 @@ static void gen_vmrgew(DisasContext *ctx) tcg_temp_free_i64(avr); } =20 -static void gen_vmrgow(DisasContext *ctx) +static void trans_vmrgow(DisasContext *ctx) { - TCGv_i64 t0, t1; - TCGv_i64 avr; - int VT, VA, VB; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - VT =3D rD(ctx->opcode); - VA =3D rA(ctx->opcode); - VB =3D rB(ctx->opcode); - t0 =3D tcg_temp_new_i64(); - t1 =3D tcg_temp_new_i64(); - avr =3D tcg_temp_new_i64(); + int VT =3D rD(ctx->opcode); + int VA =3D rA(ctx->opcode); + int VB =3D rB(ctx->opcode); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 avr =3D tcg_temp_new_i64(); =20 get_avr64(t0, VB, true); get_avr64(t1, VA, true); @@ -1213,14 +1217,14 @@ GEN_VXFORM_ENV(vminfp, 5, 17); GEN_VXFORM_HETRO(vextublx, 6, 24) GEN_VXFORM_HETRO(vextuhlx, 6, 25) GEN_VXFORM_HETRO(vextuwlx, 6, 26) -GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, +GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, vextuwlx, PPC_NONE, PPC2_ISA300) GEN_VXFORM_HETRO(vextubrx, 6, 28) GEN_VXFORM_HETRO(vextuhrx, 6, 29) GEN_VXFORM_HETRO(vextuwrx, 6, 30) GEN_VXFORM_TRANS(lvsl, 6, 31) GEN_VXFORM_TRANS(lvsr, 6, 32) -GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \ +GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, vextuwrx, PPC_NONE, PPC2_ISA300) =20 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ --=20 2.7.4