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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:42:08 +0100 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eqC031653912 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:52 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CFF4124053; Wed, 29 May 2019 05:40:52 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8379A124054; Wed, 29 May 2019 05:40:50 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:50 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:49 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-0072-0000-0000-00000434904A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210123; UDB=6.00635758; IPR=6.00991156; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:42:10 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-0073-0000-0000-00004C6743CD Message-Id: <155910844950.13149.6460514692958589700.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=841 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 5/6] ppc: spapr: Enable FWNMI capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Enable the KVM capability KVM_CAP_PPC_FWNMI so that the KVM causes guest exit with NMI as exit reason when it encounters a machine check exception on the address belonging to a guest. Without this capability enabled, KVM redirects machine check exceptions to guest's 0x200 vector. This patch also deals with the case when a guest with the KVM_CAP_PPC_FWNMI capability enabled is attempted to migrate to a host that does not support this capability. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 24 ++++++++++++++++++++++++ hw/ppc/spapr_rtas.c | 18 ++++++++++++++++++ include/hw/ppc/spapr.h | 4 +++- target/ppc/kvm.c | 19 +++++++++++++++++++ target/ppc/kvm_ppc.h | 12 ++++++++++++ 6 files changed, 77 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c97f6a6..e8a77636 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4364,6 +4364,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_ON; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 31b4661..ef9e612 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -479,6 +479,20 @@ static void cap_ccf_assist_apply(SpaprMachineState *sp= apr, uint8_t val, } } =20 +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + if (!val) { + return; /* Disabled by default */ + } + + if (tcg_enabled()) { + error_setg(errp, "No fwnmi support in TCG, try cap-fwnmi-mce= =3Doff"); + } else if (kvm_enabled() && !kvmppc_has_cap_ppc_fwnmi()) { + error_setg(errp, "Requested fwnmi capability not support by KV= M"); + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -578,6 +592,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ccf_assist_apply, }, + [SPAPR_CAP_FWNMI_MCE] =3D { + .name =3D "fwnmi-mce", + .description =3D "Handle fwnmi machine check exceptions", + .index =3D SPAPR_CAP_FWNMI_MCE, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_fwnmi_mce_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -717,6 +740,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXP= AGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index e0bdfc8..91a7ab9 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -49,6 +49,7 @@ #include "hw/ppc/fdt.h" #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" +#include "kvm_ppc.h" =20 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -358,6 +359,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, target_ulong args, uint32_t nret, target_ulong rets) { + int ret; hwaddr rtas_addr =3D spapr_get_rtas_addr(); =20 if (!rtas_addr) { @@ -365,6 +367,22 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, return; } =20 + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D 0) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + ret =3D kvmppc_fwnmi_enable(cpu); + if (ret =3D=3D 1) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + if (ret < 0) { + rtas_st(rets, 0, RTAS_OUT_HW_ERROR); + return; + } + spapr->guest_machine_check_addr =3D rtas_ld(args, 1); rtas_st(rets, 0, RTAS_OUT_SUCCESS); } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index c717ab2..bd75d4b 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -78,8 +78,10 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* FWNMI machine check handling */ +#define SPAPR_CAP_FWNMI_MCE 0x0A /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) =20 /* * Capability Values diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 39f1a73..368ec6e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -84,6 +84,7 @@ static int cap_ppc_safe_indirect_branch; static int cap_ppc_count_cache_flush_assist; static int cap_ppc_nested_kvm_hv; static int cap_large_decr; +static int cap_ppc_fwnmi; =20 static uint32_t debug_inst_opcode; =20 @@ -152,6 +153,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) kvmppc_get_cpu_characteristics(s); cap_ppc_nested_kvm_hv =3D kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED= _HV); cap_large_decr =3D kvmppc_get_dec_bits(); + cap_ppc_fwnmi =3D kvm_check_extension(s, KVM_CAP_PPC_FWNMI); /* * Note: setting it to false because there is not such capability * in KVM at this moment. @@ -2119,6 +2121,18 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic= _proxy) } } =20 +int kvmppc_fwnmi_enable(PowerPCCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + + if (!cap_ppc_fwnmi) { + return 1; + } + + return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); +} + + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; @@ -2419,6 +2433,11 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } =20 +bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return cap_ppc_fwnmi; +} + static bool kvmppc_power8_host(void) { bool ret =3D false; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 18693f1..3d9f0b4 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -27,6 +27,8 @@ void kvmppc_enable_h_page_init(void); void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); +int kvmppc_fwnmi_enable(PowerPCCPU *cpu); +bool kvmppc_has_cap_ppc_fwnmi(void); int kvmppc_smt_threads(void); void kvmppc_hint_smt_possible(Error **errp); int kvmppc_set_smt_threads(int smt); @@ -160,6 +162,16 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *c= pu, int mpic_proxy) { } =20 +static inline int kvmppc_fwnmi_enable(PowerPCCPU *cpu) +{ + return 1; +} + +static inline bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return false; +} + static inline int kvmppc_smt_threads(void) { return 1;