From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559108698; cv=none; d=zoho.com; s=zohoarc; b=EE1NAZCOuCFrdXTo2ZaOwLfhXxHZyDcVTxQh4vSR3aslNMfZxNw5Hm//9mI5g2Yrz1TpDI/FYSfQKnueXOxLKVjKmClkdNM1UHrBAIBbDuPuD31CI6wP3Z+OTn8H3jcT6kgm35V2gGFOSiNxgD4vNgKwdMA1/qILPPFrJW3wHBo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559108698; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qJDS+gmXsQJUYMyeBOJWFRrunSc4dHe6wGoCqSWFaIo=; b=UphN+WQ3DIOanUBYBzfiSppru9s00TiT0psL0u4l+H5vx5UxpHiwNs4SKqmiZqQnFRZ42HSUsbMyCVlpjripTdL5zhaWRB2uIjGIEj1iRFOAGD+RxulQlxvSt/wPu3MbJCZDQsKMmybVT842Ww/qeTEj5KLE4F0ErdR+NRCu/ME= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559108698322628.1709199921764; Tue, 28 May 2019 22:44:58 -0700 (PDT) Received: from localhost ([127.0.0.1]:47629 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrON-0000fp-AE for importer@patchew.org; Wed, 29 May 2019 01:44:51 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrK9-0005v2-RQ for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hVrK8-0004zE-IN for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:29 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:41196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hVrK8-0004wW-89 for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:28 -0400 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4T5Xlh0079875 for ; Wed, 29 May 2019 01:40:23 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2sskw8gfh2-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 29 May 2019 01:40:23 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:40:19 +0100 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eIUr38011034 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:18 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1C74A7805C; Wed, 29 May 2019 05:40:18 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE81A7805E; Wed, 29 May 2019 05:40:15 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:15 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:14 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-0012-0000-0000-0000173CE1D6 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210122; UDB=6.00635757; IPR=6.00991155; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:40:21 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-0013-0000-0000-000057730904 Message-Id: <155910841478.13149.2830700794862210739.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 1/6] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This patch adds support in QEMU to handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls. The machine check notification address is saved when the OS issues "ibm,nmi-register" RTAS call. This patch also handles the case when multiple processors experience machine check at or about the same time by handling "ibm,nmi-interlock" call. In such cases, as per PAPR, subsequent processors serialize waiting for the first processor to issue the "ibm,nmi-interlock" call. The second processor that also received a machine check error waits till the first processor is done reading the error log. The first processor issues "ibm,nmi-interlock" call when the error log is consumed. This patch implements the releasing part of the error-log while subsequent patch (which builds error log) handles the locking part. Signed-off-by: Aravinda Prasad Reviewed-by: David Gibson --- hw/ppc/spapr.c | 7 +++++ hw/ppc/spapr_rtas.c | 65 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/spapr.h | 9 ++++++- 3 files changed, 80 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e2b33e5..fae28a9 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1808,6 +1808,11 @@ static void spapr_machine_reset(void) first_ppc_cpu->env.gpr[5] =3D 0; =20 spapr->cas_reboot =3D false; + + spapr->guest_machine_check_addr =3D -1; + + /* Signal all vCPUs waiting on this condition */ + qemu_cond_broadcast(&spapr->mc_delivery_cond); } =20 static void spapr_create_nvram(SpaprMachineState *spapr) @@ -3072,6 +3077,8 @@ static void spapr_machine_init(MachineState *machine) =20 kvmppc_spapr_enable_inkernel_multitce(); } + + qemu_cond_init(&spapr->mc_delivery_cond); } =20 static int spapr_kvm_type(MachineState *machine, const char *vm_type) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 5bc1a93..e7509cf 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -352,6 +352,38 @@ static void rtas_get_power_level(PowerPCCPU *cpu, Spap= rMachineState *spapr, rtas_st(rets, 1, 100); } =20 +static void rtas_ibm_nmi_register(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + hwaddr rtas_addr =3D spapr_get_rtas_addr(); + + if (!rtas_addr) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + spapr->guest_machine_check_addr =3D rtas_ld(args, 1); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, + SpaprMachineState *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* NMI register not called */ + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + } else { + qemu_cond_signal(&spapr->mc_delivery_cond); + rtas_st(rets, 0, RTAS_OUT_SUCCESS); + } +} + static struct rtas_call { const char *name; spapr_rtas_fn fn; @@ -470,6 +502,35 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *f= dt, hwaddr addr) } } =20 +hwaddr spapr_get_rtas_addr(void) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + int rtas_node; + const struct fdt_property *rtas_addr_prop; + void *fdt =3D spapr->fdt_blob; + uint32_t rtas_addr; + + /* fetch rtas addr from fdt */ + rtas_node =3D fdt_path_offset(fdt, "/rtas"); + if (rtas_node =3D=3D 0) { + return 0; + } + + rtas_addr_prop =3D fdt_get_property(fdt, rtas_node, "linux,rtas-base",= NULL); + if (!rtas_addr_prop) { + return 0; + } + + /* + * We assume that the OS called RTAS instantiate-rtas, but some other + * OS might call RTAS instantiate-rtas-64 instead. This fine as of now + * as SLOF only supports 32-bit variant. + */ + rtas_addr =3D fdt32_to_cpu(*(uint32_t *)rtas_addr_prop->data); + return (hwaddr)rtas_addr; +} + + static void core_rtas_register_types(void) { spapr_rtas_register(RTAS_DISPLAY_CHARACTER, "display-character", @@ -493,6 +554,10 @@ static void core_rtas_register_types(void) rtas_set_power_level); spapr_rtas_register(RTAS_GET_POWER_LEVEL, "get-power-level", rtas_get_power_level); + spapr_rtas_register(RTAS_IBM_NMI_REGISTER, "ibm,nmi-register", + rtas_ibm_nmi_register); + spapr_rtas_register(RTAS_IBM_NMI_INTERLOCK, "ibm,nmi-interlock", + rtas_ibm_nmi_interlock); } =20 type_init(core_rtas_register_types) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 4f5becf..9dc5e30 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -188,6 +188,10 @@ struct SpaprMachineState { * occurs during the unplug process. */ QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; =20 + /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ + target_ulong guest_machine_check_addr; + QemuCond mc_delivery_cond; + /*< public >*/ char *kvm_type; char *host_model; @@ -624,8 +628,10 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_u= long opcode, #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) +#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2A) +#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2B) =20 -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2C) =20 /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 @@ -876,4 +882,5 @@ void spapr_check_pagesize(SpaprMachineState *spapr, hwa= ddr pagesize, #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform = */ =20 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); +uint64_t spapr_get_rtas_addr(void); #endif /* HW_SPAPR_H */ From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559108813; cv=none; d=zoho.com; s=zohoarc; b=n3up0m88Jqah12zXJCxg/H2nVtCPLeK4GlVURBt/yL7NEkK3vO4UBOJUiwBJ85UJpAtlFS0CODNAP0ORWmIrzclPM+/cseoSGSwwO6+d3DlqvSmqclNQ84sF7X1VK6XQHmOgEUKY8LW+hhR2nvW8mMd3MVkkafYg9MgfeJZ7rjU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559108813; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=JkuGV8Zzpdo2fdTM27ScxAB6CcB45nRF9q+IBn17YW4=; b=ixBXANX+OyEXTWprkDElemyTTTOZyltaIuio8txqfJeDlLl1AZvS0/Q3rbFdv8Sj/biGmf5OGXJmLN9d6o4TIv3uKtm8nFL0TsL+reweip8Uf7LaN+3+NFSFB15s+DMLQ2PykU91ZUKpPh2ugB460sq0pDKW/Eo5O2T0CO5dSg4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559108813383806.3634829471242; Tue, 28 May 2019 22:46:53 -0700 (PDT) Received: from localhost ([127.0.0.1]:47678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrQF-00020I-F7 for importer@patchew.org; Wed, 29 May 2019 01:46:47 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrKD-00060f-H0 for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hVrKC-00057y-HO for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:33 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:41852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hVrKC-00055Q-6b for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:32 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4T5XOKJ042559 for ; Wed, 29 May 2019 01:40:31 -0400 Received: from e31.co.us.ibm.com (e31.co.us.ibm.com [32.97.110.149]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ssk4s9w5r-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 29 May 2019 01:40:30 -0400 Received: from localhost by e31.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:40:27 +0100 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eQiC12648894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:26 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B185DBE051; Wed, 29 May 2019 05:40:26 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8FD0DBE04F; Wed, 29 May 2019 05:40:24 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:24 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:23 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-8235-0000-0000-00000E9FBB27 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210123; UDB=6.00635758; IPR=6.00991155; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:40:29 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-8236-0000-0000-000045C34D72 Message-Id: <155910842340.13149.1753970249353896871.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=908 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 2/6] Wrapper function to wait on condition for the main loop mutex X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Introduce a wrapper function to wait on condition for the main loop mutex. This function atomically releases the main loop mutex and causes the calling thread to block on the condition. This wrapper is required because qemu_global_mutex is a static variable. Signed-off-by: Aravinda Prasad Reviewed-by: David Gibson Reviewed-by: Greg Kurz --- cpus.c | 5 +++++ include/qemu/main-loop.h | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/cpus.c b/cpus.c index ffc5711..14cb24b 100644 --- a/cpus.c +++ b/cpus.c @@ -1867,6 +1867,11 @@ void qemu_mutex_unlock_iothread(void) qemu_mutex_unlock(&qemu_global_mutex); } =20 +void qemu_cond_wait_iothread(QemuCond *cond) +{ + qemu_cond_wait(cond, &qemu_global_mutex); +} + static bool all_vcpus_paused(void) { CPUState *cpu; diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h index f6ba78e..a6d20b0 100644 --- a/include/qemu/main-loop.h +++ b/include/qemu/main-loop.h @@ -295,6 +295,14 @@ void qemu_mutex_lock_iothread_impl(const char *file, i= nt line); */ void qemu_mutex_unlock_iothread(void); =20 +/* + * qemu_cond_wait_iothread: Wait on condition for the main loop mutex + * + * This function atomically releases the main loop mutex and causes + * the calling thread to block on the condition. + */ +void qemu_cond_wait_iothread(QemuCond *cond); + /* internal interfaces */ =20 void qemu_fd_register(int fd); From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559108571; cv=none; d=zoho.com; s=zohoarc; b=Wig9DzKATf1q1nSGCc5G+KSOiJhbt6DsMHHJ4Fno7zrR2C3EO7ybqZqdhnRPiUwu5K+HxQwUDp5tcsSL9kH9dLJV8nZtD8hufObpvAs2cwXhNigAMcDj8Ud9t5c9h+Vtb9NRl5vETjhXh4ZJbAF6P+FLPIrsr1rOfgEOWYDh3fM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559108571; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=zmB0nbaeI2Nn0x3cMpxchIv8IzdoaFcaNu5hyVHaX+g=; b=NSI92E5ksplgnKnsl3EY0K+aoUctcpRtbSAP7jbfrVa09OJfnJT4M7NhN0yMytCXZyTuf9cFtaTmSgUZfZhDrBoi+eP1cBIAmlYnmFky4xMMm75SQthLa4LJmvLDK+q1pr8wVO77MJ+M1rdJsThsyXhOsx0XJ6kYyN/F6VbP0Jg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559108571361960.998738295991; Tue, 28 May 2019 22:42:51 -0700 (PDT) Received: from localhost ([127.0.0.1]:47603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrML-0007Tk-8e for importer@patchew.org; Wed, 29 May 2019 01:42:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrKO-00067f-Ml for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hVrKL-0005De-Ec for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:44 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:44162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hVrKK-0005Ce-G8 for qemu-devel@nongnu.org; Wed, 29 May 2019 01:40:41 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4T5XjQG043163 for ; Wed, 29 May 2019 01:40:39 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2sskuu8hd3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 29 May 2019 01:40:39 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:40:36 +0100 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eZuo17170826 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:35 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4899CC6055; Wed, 29 May 2019 05:40:35 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2E2C7C605F; Wed, 29 May 2019 05:40:33 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:32 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:32 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-0012-0000-0000-0000173CE1DA X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210123; UDB=6.00635758; IPR=6.00991155; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:40:38 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-0013-0000-0000-00005773092A Message-Id: <155910843201.13149.14968680567084380259.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 3/6] target/ppc: Handle NMI guest exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Memory error such as bit flips that cannot be corrected by hardware are passed on to the kernel for handling. If the memory address in error belongs to guest then the guest kernel is responsible for taking suitable action. Patch [1] enhances KVM to exit guest with exit reason set to KVM_EXIT_NMI in such cases. This patch handles KVM_EXIT_NMI exit. [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html (e20bbd3d and related commits) Signed-off-by: Aravinda Prasad Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_events.c | 23 +++++++++++++++++++++++ hw/ppc/spapr_rtas.c | 5 +++++ include/hw/ppc/spapr.h | 6 ++++++ target/ppc/kvm.c | 16 ++++++++++++++++ target/ppc/kvm_ppc.h | 2 ++ target/ppc/trace-events | 1 + 7 files changed, 54 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index fae28a9..6b6c962 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1809,6 +1809,7 @@ static void spapr_machine_reset(void) =20 spapr->cas_reboot =3D false; =20 + spapr->mc_status =3D -1; spapr->guest_machine_check_addr =3D -1; =20 /* Signal all vCPUs waiting on this condition */ diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index ae0f093..a18446b 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -620,6 +620,29 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprDr= cType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + + while (spapr->mc_status !=3D -1) { + /* + * Check whether the same CPU got machine check error + * while still handling the mc error (i.e., before + * that CPU called "ibm,nmi-interlock") + */ + if (spapr->mc_status =3D=3D cpu->vcpu_id) { + qemu_system_guest_panicked(NULL); + return; + } + qemu_cond_wait_iothread(&spapr->mc_delivery_cond); + /* Meanwhile if the system is reset, then just return */ + if (spapr->guest_machine_check_addr =3D=3D -1) { + return; + } + } + spapr->mc_status =3D cpu->vcpu_id; +} + static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, target_ulong args, diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index e7509cf..e0bdfc8 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -379,6 +379,11 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, /* NMI register not called */ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); } else { + /* + * vCPU issuing "ibm,nmi-interlock" is done with NMI handling, + * hence unset mc_status. + */ + spapr->mc_status =3D -1; qemu_cond_signal(&spapr->mc_delivery_cond); rtas_st(rets, 0, RTAS_OUT_SUCCESS); } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9dc5e30..fc3a776 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -190,6 +190,11 @@ struct SpaprMachineState { =20 /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */ target_ulong guest_machine_check_addr; + /* + * mc_status is set to -1 if mc is not in progress, else is set to the= CPU + * handling the mc. + */ + int mc_status; QemuCond mc_delivery_cond; =20 /*< public >*/ @@ -793,6 +798,7 @@ void spapr_clear_pending_events(SpaprMachineState *spap= r); int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); +void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 3bf0a46..39f1a73 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1761,6 +1761,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_ru= n *run) ret =3D 0; break; =20 + case KVM_EXIT_NMI: + trace_kvm_handle_nmi_exception(); + ret =3D kvm_handle_nmi(cpu, run); + break; + default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); ret =3D -1; @@ -2844,6 +2849,17 @@ int kvm_arch_msi_data_to_gsi(uint32_t data) return data & 0xffff; } =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run) +{ + bool recovered =3D run->flags & KVM_RUN_PPC_NMI_DISP_FULLY_RECOV; + + cpu_synchronize_state(CPU(cpu)); + + spapr_mce_req_event(cpu, recovered); + + return 0; +} + int kvmppc_enable_hwrng(void) { if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRN= G)) { diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 45776ca..18693f1 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -81,6 +81,8 @@ bool kvmppc_hpt_needs_host_contiguous_pages(void); void kvm_check_mmu(PowerPCCPU *cpu, Error **errp); void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online); =20 +int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); + #else =20 static inline uint32_t kvmppc_get_tbfreq(void) diff --git a/target/ppc/trace-events b/target/ppc/trace-events index 3dc6740..6d15aa9 100644 --- a/target/ppc/trace-events +++ b/target/ppc/trace-events @@ -28,3 +28,4 @@ kvm_handle_papr_hcall(void) "handle PAPR hypercall" kvm_handle_epr(void) "handle epr" kvm_handle_watchdog_expiry(void) "handle watchdog expiry" kvm_handle_debug_exception(void) "handle debug exception" +kvm_handle_nmi_exception(void) "handle NMI exception" From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:40:45 +0100 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eiLm23396730 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:44 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FE286E04E; Wed, 29 May 2019 05:40:44 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D14FA6E04C; Wed, 29 May 2019 05:40:41 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:41 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:40 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-0020-0000-0000-00000EF17AB6 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210123; UDB=6.00635758; IPR=6.00991155; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:40:47 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-0021-0000-0000-000066024C82 Message-Id: <155910844057.13149.1476616524987244293.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v9 4/6] target/ppc: Build rtas error log upon an MCE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Upon a machine check exception (MCE) in a guest address space, KVM causes a guest exit to enable QEMU to build and pass the error to the guest in the PAPR defined rtas error log format. This patch builds the rtas error log, copies it to the rtas_addr and then invokes the guest registered machine check handler. The handler in the guest takes suitable action(s) depending on the type and criticality of the error. For example, if an error is unrecoverable memory corruption in an application inside the guest, then the guest kernel sends a SIGBUS to the application. For recoverable errors, the guest performs recovery actions and logs the error. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 5 + hw/ppc/spapr_events.c | 236 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/spapr.h | 4 + 3 files changed, 245 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6b6c962..c97f6a6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2910,6 +2910,11 @@ static void spapr_machine_init(MachineState *machine) error_report("Could not get size of LPAR rtas '%s'", filename); exit(1); } + + /* Resize blob to accommodate error log. */ + g_assert(spapr->rtas_size < RTAS_ERROR_LOG_OFFSET); + spapr->rtas_size =3D RTAS_ERROR_LOG_MAX; + spapr->rtas_blob =3D g_malloc(spapr->rtas_size); if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0)= { error_report("Could not load LPAR rtas '%s'", filename); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index a18446b..573c0b7 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -212,6 +212,106 @@ struct hp_extended_log { struct rtas_event_log_v6_hp hp; } QEMU_PACKED; =20 +struct rtas_event_log_v6_mc { +#define RTAS_LOG_V6_SECTION_ID_MC 0x4D43 /* MC */ + struct rtas_event_log_v6_section_header hdr; + uint32_t fru_id; + uint32_t proc_id; + uint8_t error_type; +#define RTAS_LOG_V6_MC_TYPE_UE 0 +#define RTAS_LOG_V6_MC_TYPE_SLB 1 +#define RTAS_LOG_V6_MC_TYPE_ERAT 2 +#define RTAS_LOG_V6_MC_TYPE_TLB 4 +#define RTAS_LOG_V6_MC_TYPE_D_CACHE 5 +#define RTAS_LOG_V6_MC_TYPE_I_CACHE 7 + uint8_t sub_err_type; +#define RTAS_LOG_V6_MC_UE_INDETERMINATE 0 +#define RTAS_LOG_V6_MC_UE_IFETCH 1 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH 2 +#define RTAS_LOG_V6_MC_UE_LOAD_STORE 3 +#define RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE 4 +#define RTAS_LOG_V6_MC_SLB_PARITY 0 +#define RTAS_LOG_V6_MC_SLB_MULTIHIT 1 +#define RTAS_LOG_V6_MC_SLB_INDETERMINATE 2 +#define RTAS_LOG_V6_MC_ERAT_PARITY 1 +#define RTAS_LOG_V6_MC_ERAT_MULTIHIT 2 +#define RTAS_LOG_V6_MC_ERAT_INDETERMINATE 3 +#define RTAS_LOG_V6_MC_TLB_PARITY 1 +#define RTAS_LOG_V6_MC_TLB_MULTIHIT 2 +#define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3 + uint8_t reserved_1[6]; + uint64_t effective_address; + uint64_t logical_address; +} QEMU_PACKED; + +struct mc_extended_log { + struct rtas_event_log_v6 v6hdr; + struct rtas_event_log_v6_mc mc; +} QEMU_PACKED; + +struct MC_ierror_table { + unsigned long srr1_mask; + unsigned long srr1_value; + bool nip_valid; /* nip is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_ierror_table mc_ierror_table[] =3D { +{ 0x00000000081c0000, 0x0000000000040000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000080000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x00000000000c0000, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000100000, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000140000, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000000081c0000, 0x0000000000180000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_IFETCH, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0, 0, 0, 0, 0, 0 } }; + +struct MC_derror_table { + unsigned long dsisr_value; + bool dar_valid; /* dar is a valid indicator of faulting address */ + uint8_t error_type; + uint8_t error_subtype; + unsigned int initiator; + unsigned int severity; +}; + +static const struct MC_derror_table mc_derror_table[] =3D { +{ 0x00008000, false, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00004000, true, + RTAS_LOG_V6_MC_TYPE_UE, RTAS_LOG_V6_MC_UE_PAGE_TABLE_WALK_LOAD_STORE, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000800, true, + RTAS_LOG_V6_MC_TYPE_ERAT, RTAS_LOG_V6_MC_ERAT_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000400, true, + RTAS_LOG_V6_MC_TYPE_TLB, RTAS_LOG_V6_MC_TLB_MULTIHIT, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000080, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_MULTIHIT, /* Before PARITY = */ + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0x00000100, true, + RTAS_LOG_V6_MC_TYPE_SLB, RTAS_LOG_V6_MC_SLB_PARITY, + RTAS_LOG_INITIATOR_CPU, RTAS_LOG_SEVERITY_ERROR_SYNC, }, +{ 0, false, 0, 0, 0, 0 } }; + +#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) + typedef enum EventClass { EVENT_CLASS_INTERNAL_ERRORS =3D 0, EVENT_CLASS_EPOW =3D 1, @@ -620,6 +720,138 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprD= rcType drc_type, RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_i= d); } =20 +static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered, + struct mc_extended_log *ext_elog) +{ + int i; + CPUPPCState *env =3D &cpu->env; + uint32_t summary; + uint64_t dsisr =3D env->spr[SPR_DSISR]; + + summary =3D RTAS_LOG_VERSION_6 | RTAS_LOG_OPTIONAL_PART_PRESENT; + if (recovered) { + summary |=3D RTAS_LOG_DISPOSITION_FULLY_RECOVERED; + } else { + summary |=3D RTAS_LOG_DISPOSITION_NOT_RECOVERED; + } + + if (SRR1_MC_LOADSTORE(env->spr[SPR_SRR1])) { + for (i =3D 0; mc_derror_table[i].dsisr_value; i++) { + if (!(dsisr & mc_derror_table[i].dsisr_value)) { + continue; + } + + ext_elog->mc.error_type =3D mc_derror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_derror_table[i].error_subtype; + if (mc_derror_table[i].dar_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->spr[SP= R_DAR]); + } + + summary |=3D mc_derror_table[i].initiator + | mc_derror_table[i].severity; + + return summary; + } + } else { + for (i =3D 0; mc_ierror_table[i].srr1_mask; i++) { + if ((env->spr[SPR_SRR1] & mc_ierror_table[i].srr1_mask) !=3D + mc_ierror_table[i].srr1_value) { + continue; + } + + ext_elog->mc.error_type =3D mc_ierror_table[i].error_type; + ext_elog->mc.sub_err_type =3D mc_ierror_table[i].error_subtype; + if (mc_ierror_table[i].nip_valid) { + ext_elog->mc.effective_address =3D cpu_to_be64(env->nip); + } + + summary |=3D mc_ierror_table[i].initiator + | mc_ierror_table[i].severity; + + return summary; + } + } + + summary |=3D RTAS_LOG_INITIATOR_CPU; + return summary; +} + +static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, bool recovered) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + CPUState *cs =3D CPU(cpu); + uint64_t rtas_addr; + CPUPPCState *env =3D &cpu->env; + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong r3, msr =3D 0; + struct rtas_error_log log; + struct mc_extended_log *ext_elog; + uint32_t summary; + + /* + * Properly set bits in MSR before we invoke the handler. + * SRR0/1, DAR and DSISR are properly set by KVM + */ + if (!(*pcc->interrupts_big_endian)(cpu)) { + msr |=3D (1ULL << MSR_LE); + } + + if (env->msr & (1ULL << MSR_SF)) { + msr |=3D (1ULL << MSR_SF); + } + + msr |=3D (1ULL << MSR_ME); + + if (spapr->guest_machine_check_addr =3D=3D -1) { + /* + * This implies that we have hit a machine check between system + * reset and "ibm,nmi-register". Fall back to the old machine + * check behavior in such cases. + */ + env->spr[SPR_SRR0] =3D env->nip; + env->spr[SPR_SRR1] =3D env->msr; + env->msr =3D msr; + env->nip =3D 0x200; + return; + } + + ext_elog =3D g_malloc0(sizeof(*ext_elog)); + summary =3D spapr_mce_get_elog_type(cpu, recovered, ext_elog); + + log.summary =3D cpu_to_be32(summary); + log.extended_length =3D cpu_to_be32(sizeof(*ext_elog)); + + /* r3 should be in BE always */ + r3 =3D cpu_to_be64(env->gpr[3]); + env->msr =3D msr; + + spapr_init_v6hdr(&ext_elog->v6hdr); + ext_elog->mc.hdr.section_id =3D cpu_to_be16(RTAS_LOG_V6_SECTION_ID_MC); + ext_elog->mc.hdr.section_length =3D + cpu_to_be16(sizeof(struct rtas_event_log_v6_mc)); + ext_elog->mc.hdr.section_version =3D 1; + + /* get rtas addr from fdt */ + rtas_addr =3D spapr_get_rtas_addr(); + if (!rtas_addr) { + /* Unable to fetch rtas_addr. Hence reset the guest */ + ppc_cpu_do_system_reset(cs); + } + + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET, &r3, + sizeof(r3)); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + sizeof(r= 3), + &log, sizeof(log)); + cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET + sizeof(r= 3) + + sizeof(log), ext_elog, + sizeof(*ext_elog)); + + env->gpr[3] =3D rtas_addr + RTAS_ERROR_LOG_OFFSET; + env->nip =3D spapr->guest_machine_check_addr; + + g_free(ext_elog); +} + void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); @@ -641,6 +873,10 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool recover= ed) } } spapr->mc_status =3D cpu->vcpu_id; + + spapr_mce_dispatch_elog(cpu, recovered); + + return; } =20 static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr, diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index fc3a776..c717ab2 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -710,6 +710,9 @@ void spapr_load_rtas(SpaprMachineState *spapr, void *fd= t, hwaddr addr); =20 #define RTAS_ERROR_LOG_MAX 2048 =20 +/* Offset from rtas-base where error log is placed */ +#define RTAS_ERROR_LOG_OFFSET 0x30 + #define RTAS_EVENT_SCAN_RATE 1 =20 /* This helper should be used to encode interrupt specifiers when the rela= ted @@ -799,6 +802,7 @@ int spapr_max_server_number(SpaprMachineState *spapr); void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte0, uint64_t pte1); void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); +ssize_t spapr_get_rtas_size(ssize_t old_rtas_sizea); =20 /* DRC callbacks. */ void spapr_core_release(DeviceState *dev); From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1559108824; cv=none; d=zoho.com; s=zohoarc; b=PvJVuG1NdMDVqhs5lqEjEqkmPGsWr0plZfuOXJF/tV3s6BQRzOTkI4WiNbmy4UexQ+zlzLAr5kPF4xgP9P0/AXncr6TVB80Iby1AGtvPGQD1B80OHjc94OVpqlaXLi5OacdO4YCvCyk8/6b9EeqaMmoupoCAqojrdVili865AQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559108824; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=XIY2Qf/lvcbOmQwVysMBQ8oJV6vfydAKu5pudeWxrcU=; b=Dp21ie58MBFGxZKdU8RwV3EWByClBKTvR+OOqg1z6FCaTn4LLPeAK/X8hLir22PG4ydt5rijvbxPHP+wUTSO8r4TM74DxHwMlOK2NW9A8v3nN3CzcehdWscaR43R87cWNL1YVZJaXxwMBAwUWw1q8HZ+kHILExew1ZxJsYJ53ek= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559108824420597.5300172487944; Tue, 28 May 2019 22:47:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:47680 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrQP-00029I-Vx for importer@patchew.org; Wed, 29 May 2019 01:46:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:33741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hVrLr-0007Wm-I5 for qemu-devel@nongnu.org; Wed, 29 May 2019 01:42:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hVrLq-0006FP-2W for qemu-devel@nongnu.org; Wed, 29 May 2019 01:42:15 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:50948) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hVrLp-0006Ek-Oa for qemu-devel@nongnu.org; Wed, 29 May 2019 01:42:14 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4T5XiHY043153 for ; Wed, 29 May 2019 01:42:12 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2sskuu8jnr-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 29 May 2019 01:42:12 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 29 May 2019 06:42:08 +0100 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4T5eqC031653912 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 May 2019 05:40:52 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CFF4124053; Wed, 29 May 2019 05:40:52 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8379A124054; Wed, 29 May 2019 05:40:50 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:50 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:49 +0530 In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19052905-0072-0000-0000-00000434904A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011177; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01210123; UDB=6.00635758; IPR=6.00991156; MB=3.00027096; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-29 05:42:10 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19052905-0073-0000-0000-00004C6743CD Message-Id: <155910844950.13149.6460514692958589700.stgit@aravinda> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=841 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 5/6] ppc: spapr: Enable FWNMI capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Enable the KVM capability KVM_CAP_PPC_FWNMI so that the KVM causes guest exit with NMI as exit reason when it encounters a machine check exception on the address belonging to a guest. Without this capability enabled, KVM redirects machine check exceptions to guest's 0x200 vector. This patch also deals with the case when a guest with the KVM_CAP_PPC_FWNMI capability enabled is attempted to migrate to a host that does not support this capability. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 24 ++++++++++++++++++++++++ hw/ppc/spapr_rtas.c | 18 ++++++++++++++++++ include/hw/ppc/spapr.h | 4 +++- target/ppc/kvm.c | 19 +++++++++++++++++++ target/ppc/kvm_ppc.h | 12 ++++++++++++ 6 files changed, 77 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c97f6a6..e8a77636 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4364,6 +4364,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] =3D SPAPR_CAP_ON; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_dual; smc->dr_phb_enabled =3D true; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 31b4661..ef9e612 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -479,6 +479,20 @@ static void cap_ccf_assist_apply(SpaprMachineState *sp= apr, uint8_t val, } } =20 +static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val, + Error **errp) +{ + if (!val) { + return; /* Disabled by default */ + } + + if (tcg_enabled()) { + error_setg(errp, "No fwnmi support in TCG, try cap-fwnmi-mce= =3Doff"); + } else if (kvm_enabled() && !kvmppc_has_cap_ppc_fwnmi()) { + error_setg(errp, "Requested fwnmi capability not support by KV= M"); + } +} + SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] =3D { [SPAPR_CAP_HTM] =3D { .name =3D "htm", @@ -578,6 +592,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_ccf_assist_apply, }, + [SPAPR_CAP_FWNMI_MCE] =3D { + .name =3D "fwnmi-mce", + .description =3D "Handle fwnmi machine check exceptions", + .index =3D SPAPR_CAP_FWNMI_MCE, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_fwnmi_mce_apply, + }, }; =20 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr, @@ -717,6 +740,7 @@ SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXP= AGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); +SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE); =20 void spapr_caps_init(SpaprMachineState *spapr) { diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index e0bdfc8..91a7ab9 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -49,6 +49,7 @@ #include "hw/ppc/fdt.h" #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" +#include "kvm_ppc.h" =20 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -358,6 +359,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, target_ulong args, uint32_t nret, target_ulong rets) { + int ret; hwaddr rtas_addr =3D spapr_get_rtas_addr(); =20 if (!rtas_addr) { @@ -365,6 +367,22 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, return; } =20 + if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) =3D=3D 0) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + ret =3D kvmppc_fwnmi_enable(cpu); + if (ret =3D=3D 1) { + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + if (ret < 0) { + rtas_st(rets, 0, RTAS_OUT_HW_ERROR); + return; + } + spapr->guest_machine_check_addr =3D rtas_ld(args, 1); rtas_st(rets, 0, RTAS_OUT_SUCCESS); } diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index c717ab2..bd75d4b 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -78,8 +78,10 @@ typedef enum { #define SPAPR_CAP_LARGE_DECREMENTER 0x08 /* Count Cache Flush Assist HW Instruction */ #define SPAPR_CAP_CCF_ASSIST 0x09 +/* FWNMI machine check handling */ +#define SPAPR_CAP_FWNMI_MCE 0x0A /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1) =20 /* * Capability Values diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 39f1a73..368ec6e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -84,6 +84,7 @@ static int cap_ppc_safe_indirect_branch; static int cap_ppc_count_cache_flush_assist; static int cap_ppc_nested_kvm_hv; static int cap_large_decr; +static int cap_ppc_fwnmi; =20 static uint32_t debug_inst_opcode; =20 @@ -152,6 +153,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s) kvmppc_get_cpu_characteristics(s); cap_ppc_nested_kvm_hv =3D kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED= _HV); cap_large_decr =3D kvmppc_get_dec_bits(); + cap_ppc_fwnmi =3D kvm_check_extension(s, KVM_CAP_PPC_FWNMI); /* * Note: setting it to false because there is not such capability * in KVM at this moment. @@ -2119,6 +2121,18 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic= _proxy) } } =20 +int kvmppc_fwnmi_enable(PowerPCCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + + if (!cap_ppc_fwnmi) { + return 1; + } + + return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0); +} + + int kvmppc_smt_threads(void) { return cap_ppc_smt ? cap_ppc_smt : 1; @@ -2419,6 +2433,11 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } =20 +bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return cap_ppc_fwnmi; +} + static bool kvmppc_power8_host(void) { bool ret =3D false; diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 18693f1..3d9f0b4 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -27,6 +27,8 @@ void kvmppc_enable_h_page_init(void); void kvmppc_set_papr(PowerPCCPU *cpu); int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr); void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy); +int kvmppc_fwnmi_enable(PowerPCCPU *cpu); +bool kvmppc_has_cap_ppc_fwnmi(void); int kvmppc_smt_threads(void); void kvmppc_hint_smt_possible(Error **errp); int kvmppc_set_smt_threads(int smt); @@ -160,6 +162,16 @@ static inline void kvmppc_set_mpic_proxy(PowerPCCPU *c= pu, int mpic_proxy) { } =20 +static inline int kvmppc_fwnmi_enable(PowerPCCPU *cpu) +{ + return 1; +} + +static inline bool kvmppc_has_cap_ppc_fwnmi(void) +{ + return false; +} + static inline int kvmppc_smt_threads(void) { return 1; From nobody Thu May 2 14:40:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 29 May 2019 05:41:00 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94EF2B2066; Wed, 29 May 2019 05:41:00 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B241DB2065; Wed, 29 May 2019 05:40:58 +0000 (GMT) Received: from [127.0.1.1] (unknown [9.124.31.56]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 29 May 2019 05:40:58 +0000 (GMT) From: Aravinda Prasad To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 29 May 2019 11:10:57 +0530 Message-ID: <155910845769.13149.8097972239187020170.stgit@aravinda> In-Reply-To: <155910829070.13149.5215948335633966328.stgit@aravinda> References: <155910829070.13149.5215948335633966328.stgit@aravinda> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-29_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905290037 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v9 6/6] migration: Include migration support for machine check handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulus@ozlabs.org, aravinda@linux.vnet.ibm.com, groug@kaod.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This patch includes migration support for machine check handling. Especially this patch blocks VM migration requests until the machine check error handling is complete as (i) these errors are specific to the source hardware and is irrelevant on the target hardware, (ii) these errors cause data corruption and should be handled before migration. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr.c | 20 ++++++++++++++++++++ hw/ppc/spapr_events.c | 17 +++++++++++++++++ hw/ppc/spapr_rtas.c | 4 ++++ include/hw/ppc/spapr.h | 2 ++ 4 files changed, 43 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e8a77636..31c4850 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2104,6 +2104,25 @@ static const VMStateDescription vmstate_spapr_dtb = =3D { }, }; =20 +static bool spapr_fwnmi_needed(void *opaque) +{ + SpaprMachineState *spapr =3D (SpaprMachineState *)opaque; + + return (spapr->guest_machine_check_addr =3D=3D -1) ? 0 : 1; +} + +static const VMStateDescription vmstate_spapr_machine_check =3D { + .name =3D "spapr_machine_check", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D spapr_fwnmi_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState), + VMSTATE_INT32(mc_status, SpaprMachineState), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_spapr =3D { .name =3D "spapr", .version_id =3D 3, @@ -2137,6 +2156,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_dtb, &vmstate_spapr_cap_large_decr, &vmstate_spapr_cap_ccf_assist, + &vmstate_spapr_machine_check, NULL } }; diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 573c0b7..35e21e4 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -41,6 +41,7 @@ #include "qemu/bcd.h" #include "hw/ppc/spapr_ovec.h" #include +#include "migration/blocker.h" =20 #define RTAS_LOG_VERSION_MASK 0xff000000 #define RTAS_LOG_VERSION_6 0x06000000 @@ -855,6 +856,22 @@ static void spapr_mce_dispatch_elog(PowerPCCPU *cpu, b= ool recovered) void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + int ret; + Error *local_err =3D NULL; + + error_setg(&spapr->fwnmi_migration_blocker, + "Live migration not supported during machine check handling"); + ret =3D migrate_add_blocker(spapr->fwnmi_migration_blocker, &local_err= ); + if (ret < 0) { + /* + * We don't want to abort and let the migration to continue. In a + * rare case, the machine check handler will run on the target + * hardware. Though this is not preferable, it is better than abor= ting + * the migration or killing the VM. + */ + error_free(spapr->fwnmi_migration_blocker); + warn_report_err(local_err); + } =20 while (spapr->mc_status !=3D -1) { /* diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 91a7ab9..c849223 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -50,6 +50,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "kvm_ppc.h" +#include "migration/blocker.h" =20 static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spa= pr, uint32_t token, uint32_t nargs, @@ -404,6 +405,9 @@ static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, spapr->mc_status =3D -1; qemu_cond_signal(&spapr->mc_delivery_cond); rtas_st(rets, 0, RTAS_OUT_SUCCESS); + migrate_del_blocker(spapr->fwnmi_migration_blocker); + error_free(spapr->fwnmi_migration_blocker); + spapr->fwnmi_migration_blocker =3D NULL; } } =20 diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index bd75d4b..6c0cfd8 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -214,6 +214,8 @@ struct SpaprMachineState { SpaprCapabilities def, eff, mig; =20 unsigned gpu_numa_id; + + Error *fwnmi_migration_blocker; }; =20 #define H_SUCCESS 0