From nobody Tue Feb 10 06:43:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558888191; cv=none; d=zoho.com; s=zohoarc; b=JKF2RkAOZLcPCL8XF9ZvRUAPJJ1aQfkVoflTF3kPiQHKk8GYFxXsKExsU6YMUdtDCsElGUV0NX2+AUCTRtd16kF4bu8fXME6naJmsRcrOKMp7gvWMGUkP2dkwyI76RPiZSKCTfpJT4AgvfuWiXxhVnyEy5Swio4VdSFigBtKIgA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558888191; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=U72iX5mh8JGFtkBI4Ux+m3kxYnXrjg+mTvIY7PacVCk=; b=f1G+2cOWUz1HqwIrKtQ8wiXsgLS0fEwBh9WnHrpCO8+mPIrCuN0SLbYEb1y5lpDzfeovvr4uAuvFJOURxhoiO3Fy/5wmfTpeU4laykpUkSftY/VegtQ2uOFLiSBLMpQcdN+ilVQwJFt8RB8bVaaLTNuaLnYd3WCYuFesI2d7E88= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558888191195223.2700329176264; Sun, 26 May 2019 09:29:51 -0700 (PDT) Received: from localhost ([127.0.0.1]:57225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUw1s-0006nq-CV for importer@patchew.org; Sun, 26 May 2019 12:29:48 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hUvwv-0002p3-J0 for qemu-devel@nongnu.org; Sun, 26 May 2019 12:24:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hUvsk-0007Pb-Gl for qemu-devel@nongnu.org; Sun, 26 May 2019 12:20:23 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:36573 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hUvsk-0007OA-5T for qemu-devel@nongnu.org; Sun, 26 May 2019 12:20:22 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 964751A4BC5; Sun, 26 May 2019 18:19:16 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 725391A4BB3; Sun, 26 May 2019 18:19:16 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Sun, 26 May 2019 18:19:06 +0200 Message-Id: <1558887551-32137-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558887551-32137-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558887551-32137-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 07/12] target/mips: Refactor and fix INSERT. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the INSERT. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/helper.h | 5 +++- target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++++++--------= ---- target/mips/translate.c | 19 +++++++++++++- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index c4a77e2..2863f60 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_2(msa_cfcmsa, tl, env, i32) @@ -944,6 +943,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 52680fe..ee1b1fa 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1340,28 +1340,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 -void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, +void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd, uint32_t rs_num, uint32_t n) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + pwd->b[n] =3D (int8_t)rs; +} =20 - switch (df) { - case DF_BYTE: - pwd->b[n] =3D (int8_t)rs; - break; - case DF_HALF: - pwd->h[n] =3D (int16_t)rs; - break; - case DF_WORD: - pwd->w[n] =3D (int32_t)rs; - break; - case DF_DOUBLE: - pwd->d[n] =3D (int64_t)rs; - break; - default: - assert(0); +void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } +#endif + pwd->h[n] =3D (int16_t)rs; +} + +void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + pwd->w[n] =3D (int32_t)rs; +} + +void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 2; + pwd->d[n] =3D (int64_t)rs; } =20 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index 68ea6ee..dd706ad 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28346,7 +28346,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, } break; case OPC_INSERT_df: - gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } break; } break; --=20 2.7.4