From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558552462; cv=none; d=zoho.com; s=zohoarc; b=N3OboDFOEjuDueLC+52UZ5oKntVEHlAOcF9BcSTuZt9Xst7ljqd2gUApscrxirHKvol37pIT8TStNUh78erhyMHZsXB98Tn24JsEt5DcbcufWIjviXTv68FV8vCrqKPyjodVbhEHO1Pq5nPyIBP5dn0uVEmNRDImaw7SzF7Qu70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558552462; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kovNixE2CBHwIo8Z294ismDIlDSf0Tf9XXayHY4tTKk=; b=WiXwcQVczTkLRQAEizd0qJ69rve/oikZseXDi098hy1vc2EsU8YPPN0X4fMZ49djXnHxEXgTbIrexOmWo1en/qhkl8qbiFKp3DVApgzDAUKGAc1ZS22nJmfc03a9lS8zqtqRyn/XNXjNRewjq+4QBJiMsmviRUkaIUfcoKzzaM4= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558552462259187.55737466353753; Wed, 22 May 2019 12:14:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:49891 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWgp-0007jq-8i for importer@patchew.org; Wed, 22 May 2019 15:14:15 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36539) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRx-0003DK-Ox for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRw-0000Mp-OM for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60454 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRw-0000Ll-H0 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 65CB01A2453; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4B9111A2238; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:32 +0200 Message-Id: <1558551522-24147-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 01/11] target/mips: Make the results of DIV_. the same as on hardware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic MSA instructions DIV_. when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 141, 142). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/msa_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c74e3cd..596190b 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -641,14 +641,15 @@ static inline int64_t msa_div_s_df(uint32_t df, int64= _t arg1, int64_t arg2) if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { return DF_MIN_INT(df); } - return arg2 ? arg1 / arg2 : 0; + return arg2 ? arg1 / arg2 + : arg1 >=3D 0 ? -1 : 1; } =20 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2) { uint64_t u_arg1 =3D UNSIGNED(arg1, df); uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg2 ? u_arg1 / u_arg2 : 0; + return arg2 ? u_arg1 / u_arg2 : -1; } =20 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553410; cv=none; d=zoho.com; s=zohoarc; b=bF17mk5DFKMAv/gFZTcUESHwyvyvkMCOS0vcU3IXvQZVGhxMzcTNLIWDWtJ8ue0KAzYesGC7J8NnPIW4tAU50l69rmCM1OEE9dVdELDFqvBTjMj+OXmYPbY9CMLLRBVd+f9I3y5YSc03Z3CCw+zKgXumEJaCIHUJQIAuWM5R1Oc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558553410; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=8ck2H7NO+4mXyKAvYW7brEm1+WIfJNgD4Kje57kFdIA=; b=BpuZjrR3q/w+0BfYj8WUM52G8/L5foSMVORrKDBLZUl1gk0ALg7jHXYQrBfrQsPy7g/+pCrBbPU5wPv8qs7YapOHvVWlAezYkPV/Wwr/QZcvV2AuyU2EZRaWGrZWih9oQ2HHd4fsf7twYI+CaB10dBvHN86jRNOpxoTCnXQbg7I= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558553410068243.4375299078473; Wed, 22 May 2019 12:30:10 -0700 (PDT) Received: from localhost ([127.0.0.1]:50152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWw6-0004ly-UG for importer@patchew.org; Wed, 22 May 2019 15:30:02 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRx-0003DU-T7 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRw-0000NB-Ul for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60458 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRw-0000Lw-N2 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 73EA21A452D; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 542E41A2287; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:33 +0200 Message-Id: <1558551522-24147-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 02/11] target/mips: Make the results of MOD_. the same as on hardware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic MSA instructions MOD_. when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 255, 256). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/msa_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 596190b..274c6ca 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -657,14 +657,14 @@ static inline int64_t msa_mod_s_df(uint32_t df, int64= _t arg1, int64_t arg2) if (arg1 =3D=3D DF_MIN_INT(df) && arg2 =3D=3D -1) { return 0; } - return arg2 ? arg1 % arg2 : 0; + return arg2 ? arg1 % arg2 : arg1; } =20 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) { uint64_t u_arg1 =3D UNSIGNED(arg1, df); uint64_t u_arg2 =3D UNSIGNED(arg2, df); - return u_arg2 ? u_arg1 % u_arg2 : 0; + return u_arg2 ? u_arg1 % u_arg2 : u_arg1; } =20 #define SIGNED_EVEN(a, df) \ --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553513; cv=none; d=zoho.com; s=zohoarc; b=Si3IqavNR24IwfrpIpg15rP0hlE10PqVeayo+V+niDESs8zwuJgTW3v289iBK6HjEkRaHHs7ri1sbiNuhompmMBAdpfjeLHM3XHOQXooZTNrWn5AdXclVKS0QyBQa3WAbPRYa/44VYS+PVQgL09NbM4morzvvTG/zgRfCi23JDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558553513; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=IRxQiFXIHC56ZVyXdPBDPsHkniRHbjA/fPeF4SqyaL0=; b=LFzX9lBX2VkXW0HlqKIibR09TAWTesLRNtqDwG/VOao0g5VxyRQSDeTsAGhPl4WoGEDsvj8NEgnIbuV033vvdJmq8plQ6/ubJRx/yzz0fU+wC/NWFydoKU7unIzmrJtFS+lk/z2XBxbWX2G5HgSKV2B+q6EYK7Zh878plwWKxnc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1558553513837553.9976044252737; Wed, 22 May 2019 12:31:53 -0700 (PDT) Received: from localhost ([127.0.0.1]:50202 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWxm-00068Q-OI for importer@patchew.org; Wed, 22 May 2019 15:31:46 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36573) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRy-0003EM-Rv for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRw-0000NH-Vc for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60465 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRw-0000Lx-JK for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 80B4C1A4168; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5CD2E1A4167; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:34 +0200 Message-Id: <1558551522-24147-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 03/11] target/mips: Fix MSA instructions LD. on big endian host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Fix the case when the host is a big endian machine, and change the approach toward LD. instruction helpers. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/op_helper.c | 188 ++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 168 insertions(+), 20 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 6d86912..a8ae438 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4356,31 +4356,179 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->ac= tive_fpu.fp_status) #define MEMOP_IDX(DF) #endif =20 -#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \ -void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t wx; \ - int i; \ - MEMOP_IDX(DF) \ - for (i =3D 0; i < DF_ELEMENTS(DF); i++) { \ - wx.TYPE[i] =3D LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \ - } \ - memcpy(pwd, &wx, sizeof(wr_t)); \ +void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); +#else + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); +#else + pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); +#endif +#endif } =20 +void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) #if !defined(CONFIG_USER_ONLY) -MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC()) -MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC()) -MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC()) -MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC()) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); +#else + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); #else -MSA_LD_DF(DF_BYTE, b, cpu_ldub_data) -MSA_LD_DF(DF_HALF, h, cpu_lduw_data) -MSA_LD_DF(DF_WORD, w, cpu_ldl_data) -MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data) + pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); #endif +#endif +} + +void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); +#else + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); +#else + pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); +#endif +#endif +} + +void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); + pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); +#else + pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); + pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); +#endif +} =20 #define MSA_PAGESPAN(x) \ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >=3D TARGET_PAGE_SI= ZE) --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558552710; cv=none; d=zoho.com; s=zohoarc; b=FcTgeeMpcFf4VOFnKGQP+6FAKX45+0Hv0luOc/3o5NkB/JtwRTqQQJILdKeRRMQmBO2SXOTjLsjCcIenV9gqeaJAcQg9W01KU/hq+2sEbnOPC9PSNFlEGjCiwn+jToxKaVWnyH4Q34BpOUmkeoS3iN3AvD0ZlOftkf3BgxJQbv4= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 22 May 2019 14:58:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRw-0000N6-UK for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60468 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRw-0000M0-JJ for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8F40A1A4531; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 68EC01A2160; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:35 +0200 Message-Id: <1558551522-24147-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 04/11] target/mips: Fix MSA instructions ST. on big endian host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Fix the case when the host is a big endian machine, and change the approach toward ST. instruction helpers. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/op_helper.c | 200 +++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 180 insertions(+), 20 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index a8ae438..3918027 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4550,31 +4550,191 @@ static inline void ensure_writable_pages(CPUMIPSSt= ate *env, #endif } =20 -#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \ -void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - int mmu_idx =3D cpu_mmu_index(env, false); \ - int i; \ - MEMOP_IDX(DF) \ - ensure_writable_pages(env, addr, mmu_idx, GETPC()); \ - for (i =3D 0; i < DF_ELEMENTS(DF); i++) { \ - ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ - } \ +void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_BYTE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#else + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); +#else + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); +#endif +#endif +} + +void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_HALF) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); +#else + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); +#else + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); +#endif +#endif } =20 +void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_WORD) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); #if !defined(CONFIG_USER_ONLY) -MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC()) -MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC()) -MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC()) -MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC()) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]); + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]); #else -MSA_ST_DF(DF_BYTE, b, cpu_stb_data) -MSA_ST_DF(DF_HALF, h, cpu_stw_data) -MSA_ST_DF(DF_WORD, w, cpu_stl_data) -MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data) + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]); + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]); #endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); +#else + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); +#endif +#endif +} + +void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_DOUBLE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) + helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); + helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); +#else + cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); + cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); +#endif +} =20 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558552884; cv=none; d=zoho.com; s=zohoarc; b=LmZ/WYBymzwaWCrBrz3toMtJXkdLthBm5vsiG7MzU4BqzbYS4CN6mUBUd/EPat7NCp3xo25/O6QVQoaSCrHMGuBt3DCPwMsUWda2HwSjL6DVrtRc1gQHf1nE8IyYr1DSWFIittKhjrWiKyhX8CpE0TISTmHQxntA70gheztdLVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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Wed, 22 May 2019 14:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRy-0000Om-9C for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:55 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60491 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000NL-Sq for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 955D11A4167; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 739FF1A4516; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:36 +0200 Message-Id: <1558551522-24147-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 05/11] target/mips: Refactor and fix COPY_S. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the COPY_S. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/helper.h | 7 +++++- target/mips/msa_helper.c | 62 +++++++++++++++++++++++++++++++++-----------= ---- target/mips/translate.c | 19 ++++++++++++++- 3 files changed, 67 insertions(+), 21 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index a6d687e..de3a9e0 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -876,7 +876,7 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) =20 DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32) + DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) @@ -938,6 +938,11 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 274c6ca..89b3be9 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1249,29 +1249,53 @@ void helper_msa_splati_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, msa_splat_df(df, pwd, pws, n); } =20 -void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %=3D DF_ELEMENTS(df); + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + env->active_tc.gpr[rd] =3D (int8_t)env->active_fpu.fpr[ws].wr.b[n]; +} =20 - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] =3D (int8_t)env->active_fpu.fpr[ws].wr.b[n]; - break; - case DF_HALF: - env->active_tc.gpr[rd] =3D (int16_t)env->active_fpu.fpr[ws].wr.h[n= ]; - break; - case DF_WORD: - env->active_tc.gpr[rd] =3D (int32_t)env->active_fpu.fpr[ws].wr.w[n= ]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n= ]; - break; +void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } #endif - default: - assert(0); + env->active_tc.gpr[rd] =3D (int16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + env->active_tc.gpr[rd] =3D (int32_t)env->active_fpu.fpr[ws].wr.w[n]; +} + +void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 2; + env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } =20 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, diff --git a/target/mips/translate.c b/target/mips/translate.c index f96c0d0..c65d19e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28301,7 +28301,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: if (likely(wd !=3D 0)) { - gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_COPY_U_df: --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553648; cv=none; d=zoho.com; s=zohoarc; b=BQ57z7tXnzvR5Y4UvMDgx1tZSelm2HZ3SRSbnL9/4sYI5jXZgkMG8NK97i3NOdjpevXKRyEAMDWRiotONjhKC+BgTkyK7L0oBsiQIHrErr5qJlDFfH2pdGqxtn2bW6w4wV7GS4GxODwnGZ4dSqNnddsGJ7OeWqsVZHeUvplkv/M= ARC-Message-Signature: i=1; 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Wed, 22 May 2019 15:34:02 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36597) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRz-0003FF-K5 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRy-0000Ob-8E for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:55 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60490 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000NM-S9 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9CBA41A2287; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7C2741A2238; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:37 +0200 Message-Id: <1558551522-24147-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 06/11] target/mips: Refactor and fix COPY_U. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the COPY_U. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/helper.h | 4 +++- target/mips/msa_helper.c | 55 +++++++++++++++++++++++++++++++-------------= ---- target/mips/translate.c | 21 +++++++++++++++++- 3 files changed, 59 insertions(+), 21 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index de3a9e0..c4a77e2 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) @@ -942,6 +941,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 89b3be9..52680fe 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1298,29 +1298,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } =20 -void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %=3D DF_ELEMENTS(df); + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + env->active_tc.gpr[rd] =3D (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; +} =20 - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] =3D (uint8_t)env->active_fpu.fpr[ws].wr.b[n= ]; - break; - case DF_HALF: - env->active_tc.gpr[rd] =3D (uint16_t)env->active_fpu.fpr[ws].wr.h[= n]; - break; - case DF_WORD: - env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[= n]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] =3D (uint64_t)env->active_fpu.fpr[ws].wr.d[= n]; - break; +void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } #endif - default: - assert(0); + env->active_tc.gpr[rd] =3D (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index c65d19e..68ea6ee 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28297,6 +28297,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, generate_exception_end(ctx, EXCP_RI); break; } + if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && + (df =3D=3D DF_WORD)) { + generate_exception_end(ctx, EXCP_RI); + break; + } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -28323,7 +28328,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, break; case OPC_COPY_U_df: if (likely(wd !=3D 0)) { - gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_INSERT_df: --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553031; cv=none; d=zoho.com; s=zohoarc; b=gKWCDH7ITV2MYC+84BM0DyCkm/bqrzEzJcgK3Bw3/JaoDdNh3kFNEdjtDDKgXyOiOHL9gT0Farlc+tcCFUfBY8Y7pkljnZvEfSGIw21RYhJmH9bqsqR1WPZf1yDHJSJVpRETQRuYvYAqo/p4Xl/GItj9PmLLKMCrXmdkm2j12nQ= ARC-Message-Signature: i=1; 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Wed, 22 May 2019 15:23:42 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRz-0003FR-PV for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRy-0000Oi-9A for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:55 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60492 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000NP-SZ for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ACE3C1A4516; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 852CD1A453C; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:38 +0200 Message-Id: <1558551522-24147-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 07/11] target/mips: Refactor and fix INSERT. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the INSERT. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com> --- target/mips/helper.h | 5 +++- target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++++++--------= ---- target/mips/translate.c | 19 +++++++++++++- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index c4a77e2..2863f60 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_2(msa_cfcmsa, tl, env, i32) @@ -944,6 +943,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 52680fe..ee1b1fa 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1340,28 +1340,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 -void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, +void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd, uint32_t rs_num, uint32_t n) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + pwd->b[n] =3D (int8_t)rs; +} =20 - switch (df) { - case DF_BYTE: - pwd->b[n] =3D (int8_t)rs; - break; - case DF_HALF: - pwd->h[n] =3D (int16_t)rs; - break; - case DF_WORD: - pwd->w[n] =3D (int32_t)rs; - break; - case DF_DOUBLE: - pwd->d[n] =3D (int64_t)rs; - break; - default: - assert(0); +void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } +#endif + pwd->h[n] =3D (int16_t)rs; +} + +void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + pwd->w[n] =3D (int32_t)rs; +} + +void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 2; + pwd->d[n] =3D (int64_t)rs; } =20 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index 68ea6ee..dd706ad 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28346,7 +28346,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, } break; case OPC_INSERT_df: - gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } break; } break; --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553759; cv=none; d=zoho.com; s=zohoarc; b=itsw0IJZc0a8dxFkyhCmn6DY40tw7XNdOrm7z6dM+IYjFzXK9u6QfPegu9uVHoHGXbIkG+Sr+PPGNmPaLZmBTlhV2MJud7CptTSKKl3WTbAj0x7b+8xDixOAn/HdqJXnaGskgkHzbD72t5cOJLN6pr8TNzrT7PbWcTEPpGDB+Fc= ARC-Message-Signature: i=1; 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Wed, 22 May 2019 15:35:50 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWRz-0003FG-K9 for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRy-0000OW-7t for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:55 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60493 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000NR-RP for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id BEF151A453C; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 995BB1A2160; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:39 +0200 Message-Id: <1558551522-24147-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 08/11] hw/mips: Use object_initialize() on MIPSCPSState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 Initialize the MIPSCPSState with object_initialize() instead of object_new(). This will allow us to add it as children of the machine container. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Aleksandar Markovic Reviewed-by: Paolo Bonzini Message-Id: <20190507163416.24647-10-philmd@redhat.com> --- hw/mips/boston.c | 25 ++++++++++++------------- hw/mips/mips_malta.c | 17 ++++++++--------- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a8b29f6..cb3ea85 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -49,7 +49,7 @@ typedef struct { SysBusDevice parent_obj; =20 MachineState *mach; - MIPSCPSState *cps; + MIPSCPSState cps; SerialState *uart; =20 CharBackend lcd_display; @@ -188,7 +188,7 @@ static uint64_t boston_platreg_read(void *opaque, hwadd= r addr, case PLAT_DDR3_STATUS: return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED; case PLAT_MMCM_DIV: - gic_freq =3D mips_gictimer_get_freq(s->cps->gic.gic_timer) / 10000= 00; + gic_freq =3D mips_gictimer_get_freq(s->cps.gic.gic_timer) / 100000= 0; val =3D gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT; val |=3D 1 << PLAT_MMCM_DIV_MUL_SHIFT; val |=3D 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT; @@ -455,20 +455,19 @@ static void boston_mach_init(MachineState *machine) =20 is_64b =3D cpu_supports_isa(machine->cpu_type, ISA_MIPS64); =20 - s->cps =3D MIPS_CPS(object_new(TYPE_MIPS_CPS)); - qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); - - object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type", + object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS); + qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default()); + object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", &err); - object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); - object_property_set_bool(OBJECT(s->cps), true, "realized", &err); + object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); + object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); =20 if (err !=3D NULL) { error_report("%s", error_get_pretty(err)); exit(1); } =20 - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); =20 flash =3D g_new(MemoryRegion, 1); memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); @@ -487,17 +486,17 @@ static void boston_mach_init(MachineState *machine) xilinx_pcie_init(sys_mem, 0, 0x10000000, 32 * MiB, 0x40000000, 1 * GiB, - get_cps_irq(s->cps, 2), false); + get_cps_irq(&s->cps, 2), false); =20 xilinx_pcie_init(sys_mem, 1, 0x12000000, 32 * MiB, 0x20000000, 512 * MiB, - get_cps_irq(s->cps, 1), false); + get_cps_irq(&s->cps, 1), false); =20 pcie2 =3D xilinx_pcie_init(sys_mem, 2, 0x14000000, 32 * MiB, 0x16000000, 1 * MiB, - get_cps_irq(s->cps, 0), true); + get_cps_irq(&s->cps, 0), true); =20 platreg =3D g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, @@ -505,7 +504,7 @@ static void boston_mach_init(MachineState *machine) memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); =20 s->uart =3D serial_mm_init(sys_mem, 0x17ffe000, 2, - get_cps_irq(s->cps, 3), 10000000, + get_cps_irq(&s->cps, 3), 10000000, serial_hd(0), DEVICE_NATIVE_ENDIAN); =20 lcd =3D g_new(MemoryRegion, 1); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 439665a..04f2117 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -94,7 +94,7 @@ typedef struct { typedef struct { SysBusDevice parent_obj; =20 - MIPSCPSState *cps; + MIPSCPSState cps; qemu_irq *i8259; } MaltaState; =20 @@ -1151,20 +1151,19 @@ static void create_cps(MaltaState *s, const char *c= pu_type, { Error *err =3D NULL; =20 - s->cps =3D MIPS_CPS(object_new(TYPE_MIPS_CPS)); - qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); - - object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err); - object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); - object_property_set_bool(OBJECT(s->cps), true, "realized", &err); + object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS); + qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default()); + object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err); + object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); + object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); if (err !=3D NULL) { error_report("%s", error_get_pretty(err)); exit(1); } =20 - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); =20 - *i8259_irq =3D get_cps_irq(s->cps, 3); + *i8259_irq =3D get_cps_irq(&s->cps, 3); *cbus_irq =3D NULL; } =20 --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553651; cv=none; d=zoho.com; s=zohoarc; b=Dbn02iQcq2G4+McCZDfRQHrppBj7Bu/L2Wn9/BANtsUsmgs3KsmYJks+UkdShGxbj7ms16pxLjx2a3nBfjtJOaXFIPvjD9EfG1aHOz0k/8D0L66pWWIALj/u8CXGwF0P5YfahoWy8+zvoRp7Z6LPKv3SS3GHULzUz+gijT/SUNQ= ARC-Message-Signature: i=1; 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Wed, 22 May 2019 15:34:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWS0-0003G8-CA for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWRy-0000P0-AG for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:56 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60496 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000NX-To for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D03E21A4561; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id A48711A2238; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:40 +0200 Message-Id: <1558551522-24147-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 09/11] hw/mips: Use object_initialize_child for correct reference counting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script: @use_sysbus_init_child_obj_missing_parent@ expression child_ptr; expression child_type; expression child_size; @@ - object_initialize(child_ptr, child_size, child_type); ... - qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default()); ... ?- object_unref(OBJECT(child_ptr)); + sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr, + child_size, child_type); We let the Malta/Boston machines adopt the CPS child, and similarly the CPS adopts the ITU/CPC/GIC/GCR children. While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. This choice also matches when using sysbus_init_child_obj(), since its code is: void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); } Suggested-by: Eduardo Habkost Inspired-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Aleksandar Markovic Reviewed-by: Paolo Bonzini Message-Id: <20190507163416.24647-11-philmd@redhat.com> --- hw/mips/boston.c | 4 ++-- hw/mips/cps.c | 20 ++++++++------------ hw/mips/mips_malta.c | 4 ++-- 3 files changed, 12 insertions(+), 16 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index cb3ea85..1ffccc8 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -455,8 +455,8 @@ static void boston_mach_init(MachineState *machine) =20 is_64b =3D cpu_supports_isa(machine->cpu_type, ISA_MIPS64); =20 - object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS); - qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default()); + sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps), + sizeof(s->cps), TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", &err); object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index fc97f59..649b35a 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -94,9 +94,8 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) =20 /* Inter-Thread Communication Unit */ if (itu_present) { - object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); - qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); - + sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu), + TYPE_MIPS_ITU); object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &er= r); object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", @@ -115,9 +114,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) } =20 /* Cluster Power Controller */ - object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); - qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); - + sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc), + TYPE_MIPS_CPC); object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); @@ -130,9 +128,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc)= , 0)); =20 /* Global Interrupt Controller */ - object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC); - qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); - + sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic), + TYPE_MIPS_GIC); object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); @@ -147,9 +144,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) /* Global Configuration Registers */ gcr_base =3D env->CP0_CMGCRBase << 4; =20 - object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); - qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); - + sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr), + TYPE_MIPS_GCR); object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 04f2117..aff8464 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1151,8 +1151,8 @@ static void create_cps(MaltaState *s, const char *cpu= _type, { Error *err =3D NULL; =20 - object_initialize(&s->cps, sizeof(s->cps), TYPE_MIPS_CPS); - qdev_set_parent_bus(DEVICE(&s->cps), sysbus_get_default()); + sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps= ), + TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err); object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err); object_property_set_bool(OBJECT(&s->cps), true, "realized", &err); --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553510; cv=none; d=zoho.com; s=zohoarc; b=Dqjbt9u74EwWSbFi10XkZSSdDPEVDL/TgQmfaBBIYOyHOYu5JEQYRlKz6gz/vd+I1YQlJI95vb91XECyPUjvnTjMq/XmIJgQ2ZxUqDP4QINnO+5AEGXjQmb1YaTdiwTrd+6cE1zFcwm/F2Ub4Gqi+c7Lv1COcQoecLrkZTWbIEs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558553510; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Wed, 22 May 2019 14:58:55 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60497 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWRx-0000Nb-UQ for qemu-devel@nongnu.org; Wed, 22 May 2019 14:58:54 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D41181A2160; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id AEB7C1A4545; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:41 +0200 Message-Id: <1558551522-24147-11-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 10/11] mips: Decide to map PAGE_EXEC in map_address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Jakub Jerm=C3=A1=C5=99 This commit addresses QEMU Bug #1825311: mips_cpu_handle_mmu_fault renders all accessed pages executable It allows finer-grained control over whether the accessed page should be executable by moving the decision to the underlying map_address function, which has more information for this. As a result, pages that have the XI bit set in the TLB and are accessed for read/write, don't suddenly end up being executable. Fixes: https://bugs.launchpad.net/qemu/+bug/1825311 Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry') Signed-off-by: Jakub Jerm=C3=A1=C5=99 Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com> --- target/mips/helper.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 9799f2e..68e44df 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -43,7 +43,7 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physic= al, int *prot, target_ulong address, int rw, int access_type) { *physical =3D address; - *prot =3D PAGE_READ | PAGE_WRITE; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 @@ -61,7 +61,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *phy= sical, int *prot, else *physical =3D address; =20 - *prot =3D PAGE_READ | PAGE_WRITE; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } =20 @@ -101,6 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physica= l, int *prot, *prot =3D PAGE_READ; if (n ? tlb->D1 : tlb->D0) *prot |=3D PAGE_WRITE; + if (!(n ? tlb->XI1 : tlb->XI0)) { + *prot |=3D PAGE_EXEC; + } return TLBRET_MATCH; } return TLBRET_DIRTY; @@ -182,7 +185,7 @@ static int get_seg_physical_address(CPUMIPSState *env, = hwaddr *physical, } else { /* The segment is unmapped */ *physical =3D physical_base | (real_address & segmask); - *prot =3D PAGE_READ | PAGE_WRITE; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } } @@ -907,7 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, } if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } @@ -927,7 +930,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, access_type, mips_access_type, mmu_= idx); if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } --=20 2.7.4 From nobody Mon May 6 17:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1558553763; cv=none; d=zoho.com; s=zohoarc; b=YcLV9dTYKjT1Ppjr+OmpFqxR4K8x4dIEIowafLwBLWm09gYk1jPbL9D1dS1PAdr7KTOTNJbwSSqVeJnIbGb85NdaPS0WnQHux4l6HG7fvB26cIY38lNFrH66qaQuShieAIu6eYBhlK7Rn8oEctPSEJ/rt0QsCLMGmSsGQpWVNa8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558553763; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NLYtGiDoUHOCsh4YJZmFFDoLITy8z/RKGtLjy5xxjMo=; b=hF4D8G/HkZIGWikk70i/fa/KzRBxJ5t1+s9KJNp9gMfnntwmY12MsESo+1AHtDILcOniEzSBpsIsdDlV65W6FP0vnmeyENsWDTUKw112exsl3ZfF4EVLPzp0BXgnfWRRh4hvA90iID7D1jSTIKa1RytxU0FedQqt0wj+k45uxgQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 155855376365480.15003013308683; Wed, 22 May 2019 12:36:03 -0700 (PDT) Received: from localhost ([127.0.0.1]:50276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTX1g-0000p9-RX for importer@patchew.org; Wed, 22 May 2019 15:35:48 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hTWSA-0003O4-3P for qemu-devel@nongnu.org; Wed, 22 May 2019 14:59:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hTWS8-0000Ua-AZ for qemu-devel@nongnu.org; Wed, 22 May 2019 14:59:06 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:60499 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hTWS7-0000Nd-Vq for qemu-devel@nongnu.org; Wed, 22 May 2019 14:59:04 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DF4461A2238; Wed, 22 May 2019 20:58:49 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id B94641A4554; Wed, 22 May 2019 20:58:49 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 22 May 2019 20:58:42 +0200 Message-Id: <1558551522-24147-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1558551522-24147-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 11/11] BootLinuxSshTest: Test some userspace commands on Malta X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 This tests boot a full VM and check the serial console until the SSH daemon is running, then start a SSH session and run some commands. This test can be run using: $ avocado --show=3Dssh run -t arch:mips tests/acceptance/linux_ssh_mips_m= alta.py ssh: Entering interactive session. ssh: # uname -a ssh: Linux debian-mips 3.2.0-4-4kc-malta #1 Debian 3.2.51-1 mips GNU/Linux ssh: # lspci -d 11ab:4620 ssh: 00:00.0 Host bridge: Marvell Technology Group Ltd. GT-64120/64120A/6= 4121A System Controller (rev 10) ssh: # cat /sys/bus/i2c/devices/i2c-0/name ssh: SMBus PIIX4 adapter at 1100 ssh: # cat /proc/mtd ssh: dev: size erasesize name ssh: mtd0: 00100000 00010000 "YAMON" ssh: mtd1: 002e0000 00010000 "User FS" ssh: mtd2: 00020000 00010000 "Board Config" ssh: # md5sum /dev/mtd2ro ssh: 0dfbe8aa4c20b52e1b8bf3cb6cbdf193 /dev/mtd2ro ssh: # poweroff Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic Acked-by: Eduardo Habkost Message-Id: <20190520231910.12184-5-f4bug@amsat.org> --- MAINTAINERS | 1 + tests/acceptance/linux_ssh_mips_malta.py | 229 +++++++++++++++++++++++++++= ++++ tests/requirements.txt | 1 + 3 files changed, 231 insertions(+) create mode 100644 tests/acceptance/linux_ssh_mips_malta.py diff --git a/MAINTAINERS b/MAINTAINERS index a6948eb..75f6544 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -934,6 +934,7 @@ M: Aurelien Jarno R: Aleksandar Rikalo S: Maintained F: hw/mips/mips_malta.c +F: tests/acceptance/linux_ssh_mips_malta.py =20 Mipssim M: Aleksandar Markovic diff --git a/tests/acceptance/linux_ssh_mips_malta.py b/tests/acceptance/li= nux_ssh_mips_malta.py new file mode 100644 index 0000000..ceb530f --- /dev/null +++ b/tests/acceptance/linux_ssh_mips_malta.py @@ -0,0 +1,229 @@ +# Functional test that boots a VM and run commands via a SSH session +# +# Copyright (c) Philippe Mathieu-Daud=C3=A9 +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +import os +import re +import base64 +import logging +import paramiko +import time + +from avocado_qemu import Test +from avocado.utils import process +from avocado.utils import archive + + +class LinuxSSH(Test): + + timeout =3D 150 # Not for 'configure --enable-debug --enable-debug-tcg' + + KERNEL_COMMON_COMMAND_LINE =3D 'printk.time=3D0 ' + VM_IP =3D '127.0.0.1' + + IMAGE_INFO =3D { + 'be': { + 'image_url': 'https://people.debian.org/~aurel32/qemu/mips/' + 'debian_wheezy_mips_standard.qcow2', + 'image_hash': '8987a63270df67345b2135a6b7a4885a35e392d5', + 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQCca1VitiyLAdQOl= d' + b'zT43IOEVJZ0wHD78GJi8wDAjMiYWUzNSSn0rXGQsINHuH= 5' + b'IlF+kBZsHinb/FtKCAyS9a8uCHhQI4SuB4QhAb0+39MlU= w' + b'Mm0CLkctgM2eUUZ6MQMQvDlqnue6CCkxN62EZYbaxmby7= j' + b'CQa1125o1HRKBvdGm2zrJWxXAfA+f1v6jHLyE8Jnu83eQ= +' + b'BFY25G+Vzx1PVc3zQBwJ8r0NGTRqy2//oWQP0h+bMsgeF= e' + b'KH/J3RJM22vg6+I4JAdBFcxnK+l781h1FuRxOn4O/Xslb= g' + b'go6WtB4V4TOsw2E/KfxI5IZ/icxF+swVcnvF46Hf3uQc/= 0' + b'BBqb', + }, + 'le': { + 'image_url': 'https://people.debian.org/~aurel32/qemu/mipsel/' + 'debian_wheezy_mipsel_standard.qcow2', + 'image_hash': '7866764d9de3ef536ffca24c9fb9f04ffdb45802', + 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQClXJlBT71HL5yKv= v' + b'gfC7jmxSWx5zSBCzET6CLZczwAafSIs7YKfNOy/dQTxhu= k' + b'yIGFUugZFoF3E9PzdhunuyvyTd56MPoNIqFbb5rGokwU5= I' + b'TOx3dBHZR0mClypL6MVrwe0bsiIb8GhF1zioNwcsaAZnA= i' + b'KfXStVDtXvn/kLLq+xLABYt48CC5KYWoFaCoICskLAY+q= o' + b'L+LWyAnQisj4jAH8VSaSKIImFpfkHWEXPhHcC4ZBlDKtn= H' + b'po9vhfCHgnfW3Pzrqmk8BI4HysqPFVmJWkJGlGUL+sGeg= 3' + b'ZZolAYuDXGuBrw8ooPJq2v2dOH+z6dyD2q/ypmAbyPqj5= C' + b'rc8H', + }, + } + + def wait_for_console_pattern(self, success_message, + failure_message=3D'Oops'): + console =3D self.vm.console_socket.makefile() + console_logger =3D logging.getLogger('console') + while True: + msg =3D console.readline() + console_logger.debug(msg.strip()) + if success_message in msg: + break + if failure_message in msg: + fail =3D 'Failure message found in console: %s' % failure_= message + self.fail(fail) + + def get_portfwd(self): + res =3D self.vm.command('human-monitor-command', + command_line=3D'info usernet') + line =3D res.split('\r\n')[2] + port =3D re.split(r'.*TCP.HOST_FORWARD.*127\.0\.0\.1 (\d+)\s+10\..= *', + line)[1] + self.log.debug("sshd listening on port:" + port) + return port + + def ssh_connect(self, username, password, rsa_hostkey_b64=3DNone): + self.ssh_logger =3D logging.getLogger('ssh') + self.ssh_username =3D username + self.ssh_ps1 =3D '# ' if username is 'root' else '$ ' + self.ssh_client =3D paramiko.SSHClient() + port =3D self.get_portfwd() + if rsa_hostkey_b64: + rsa_hostkey_bin =3D base64.b64decode(rsa_hostkey_b64) + rsa_hostkey =3D paramiko.RSAKey(data =3D rsa_hostkey_bin) + ipport =3D '[%s]:%s' % (self.VM_IP, port) + self.ssh_logger.debug('ipport ' + ipport) + self.ssh_client.get_host_keys().add(ipport, 'ssh-rsa', rsa_hos= tkey) + for i in range(10): + try: + self.ssh_client.connect(self.VM_IP, int(port), + username, password, banner_timeout= =3D90) + self.ssh_logger.info("Entering interactive session.") + return + except: + time.sleep(4) + pass + self.fail("sshd timeout") + + def ssh_disconnect_vm(self): + self.ssh_client.close() + + def ssh_command(self, command, is_root=3DTrue): + self.ssh_logger.info(self.ssh_ps1 + command) + stdin, stdout, stderr =3D self.ssh_client.exec_command(command) + stdout_lines =3D [line.strip('\n') for line in stdout] + for line in stdout_lines: + self.ssh_logger.info(line) + stderr_lines =3D [line.strip('\n') for line in stderr] + for line in stderr_lines: + self.ssh_logger.warning(line) + return stdout_lines, stderr_lines + + def boot_debian_wheezy_image_and_ssh_login(self, endianess, kernel_pat= h): + image_url =3D self.IMAGE_INFO[endianess]['image_url'] + image_hash =3D self.IMAGE_INFO[endianess]['image_hash'] + image_path =3D self.fetch_asset(image_url, asset_hash=3Dimage_hash) + rsa_hostkey_b64 =3D self.IMAGE_INFO[endianess]['rsa_hostkey'] + + self.vm.set_machine('malta') + self.vm.set_console() + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + + 'console=3DttyS0 root=3D/dev/sda1') + self.vm.add_args('-no-reboot', + '-kernel', kernel_path, + '-append', kernel_command_line, + '-hda', image_path, + '-netdev', 'user,id=3Dvnet,hostfwd=3D:127.0.0.1:0= -:22', + '-device', 'pcnet,netdev=3Dvnet') + self.vm.launch() + + self.log.info('VM launched, waiting for sshd') + console_pattern =3D 'Starting OpenBSD Secure Shell server: sshd' + self.wait_for_console_pattern(console_pattern) + self.log.info('sshd ready') + + self.ssh_connect('root', 'root', rsa_hostkey_b64=3Drsa_hostkey_b64) + + def shutdown_via_ssh(self): + self.ssh_command('poweroff') + self.ssh_disconnect_vm() + self.wait_for_console_pattern('Power down') + + def run_common_commands(self): + stdout, stderr =3D self.ssh_command('lspci -d 11ab:4620') + self.assertIn(True, ["GT-64120" in line for line in stdout]) + + stdout, stderr =3D self.ssh_command('cat /sys/bus/i2c/devices/i2c-= 0/name') + self.assertIn(True, ["SMBus PIIX4 adapter" in line + for line in stdout]) + + stdout, stderr =3D self.ssh_command('cat /proc/mtd') + self.assertIn(True, ["YAMON" in line + for line in stdout]) + + # Empty 'Board Config' + stdout, stderr =3D self.ssh_command('md5sum /dev/mtd2ro') + self.assertIn(True, ["0dfbe8aa4c20b52e1b8bf3cb6cbdf193" in line + for line in stdout]) + + def do_test_mips_malta(self, endianess, kernel_path, uname_m): + self.boot_debian_wheezy_image_and_ssh_login(endianess, kernel_path) + + stdout, stderr =3D self.ssh_command('uname -a') + self.assertIn(True, [uname_m + " GNU/Linux" in line for line in st= dout]) + + self.run_common_commands() + self.shutdown_via_ssh() + + def test_mips_malta32eb_kernel3_2_0(self): + """ + :avocado: tags=3Dslow + :avocado: tags=3Darch:mips + :avocado: tags=3Dmachine:malta + :avocado: tags=3Dendian:big + :avocado: tags=3Ddevice:pcnet32 + """ + kernel_url =3D ('https://people.debian.org/~aurel32/qemu/mips/' + 'vmlinux-3.2.0-4-4kc-malta') + kernel_hash =3D '592e384a4edc16dade52a6cd5c785c637bcbc9ad' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + self.do_test_mips_malta('be', kernel_path, 'mips') + + def test_mips_malta32el_kernel3_2_0(self): + """ + :avocado: tags=3Dslow + :avocado: tags=3Darch:mipsel + :avocado: tags=3Dmachine:malta + :avocado: tags=3Dendian:little + :avocado: tags=3Ddevice:pcnet32 + """ + kernel_url =3D ('https://people.debian.org/~aurel32/qemu/mipsel/' + 'vmlinux-3.2.0-4-4kc-malta') + kernel_hash =3D 'a66bea5a8adaa2cb3d36a1d4e0ccdb01be8f6c2a' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + self.do_test_mips_malta('le', kernel_path, 'mips') + + def test_mips_malta64eb_kernel3_2_0(self): + """ + :avocado: tags=3Dslow + :avocado: tags=3Darch:mips64 + :avocado: tags=3Dmachine:malta + :avocado: tags=3Dendian:big + :avocado: tags=3Ddevice:pcnet32 + """ + kernel_url =3D ('https://people.debian.org/~aurel32/qemu/mips/' + 'vmlinux-3.2.0-4-5kc-malta') + kernel_hash =3D 'db6eea7de35d36c77d8c165b6bcb222e16eb91db' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + self.do_test_mips_malta('be', kernel_path, 'mips64') + + def test_mips_malta64el_kernel3_2_0(self): + """ + :avocado: tags=3Dslow + :avocado: tags=3Darch:mips64el + :avocado: tags=3Dmachine:malta + :avocado: tags=3Dendian:little + :avocado: tags=3Ddevice:pcnet32 + """ + kernel_url =3D ('https://people.debian.org/~aurel32/qemu/mipsel/' + 'vmlinux-3.2.0-4-5kc-malta') + kernel_hash =3D '6a7f77245acf231415a0e8b725d91ed2f3487794' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + self.do_test_mips_malta('le', kernel_path, 'mips64') diff --git a/tests/requirements.txt b/tests/requirements.txt index 002ded6..3ae0e29 100644 --- a/tests/requirements.txt +++ b/tests/requirements.txt @@ -2,3 +2,4 @@ # in the tests/venv Python virtual environment. For more info, # refer to: https://pip.pypa.io/en/stable/user_guide/#id1 avocado-framework=3D=3D68.0 +paramiko --=20 2.7.4