From nobody Sun Feb 8 18:43:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1557132101; cv=none; d=zoho.com; s=zohoarc; b=ZNfkQVqgAET1rX+GoMA2uJle03/SeUXq1BKbGEPrB3All1aYMRy91yUdvIOu3G7HuhyN8b5tMPubjzRyE3k1NO39zyJ9eYSfQee4w60gM2KMngo2i0oe1kiz9eVTFxVmA6U9j1Bwo0nkzfFdEAJhUxPUxGE0giq7y6mnKmAxgFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557132101; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=AxUiKS+7UwH7AvvtjReTUEzpR8dOJsn6JGqpJRrRWeM=; b=NcrtyZWC5J2J2e7CnmWEiyP5ROQv4laK4MQe7apyvBMO0QRHMrqMUHp9sl1a/hdjk6zSP5z8qeW9wmAT3knmV8SiuKH1JO4U07zK5wDTOfI32Anb4enFps+OcQLeIcPF4LFw8lGily2tFoNgQiiJ5hHtNdcV2eivQC4/avDkUZc= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1557132101472827.123729347019; Mon, 6 May 2019 01:41:41 -0700 (PDT) Received: from localhost ([127.0.0.1]:52574 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNZBq-0000BX-8p for importer@patchew.org; Mon, 06 May 2019 04:41:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hNZ5P-0002qM-Ci for qemu-devel@nongnu.org; Mon, 06 May 2019 04:35:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hNZ5M-0007JW-NQ for qemu-devel@nongnu.org; Mon, 06 May 2019 04:34:59 -0400 Received: from mga14.intel.com ([192.55.52.115]:60066) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hNZ5M-0007EJ-2e for qemu-devel@nongnu.org; Mon, 06 May 2019 04:34:56 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 May 2019 01:34:51 -0700 Received: from xulike-server.sh.intel.com ([10.239.48.134]) by FMSMGA003.fm.intel.com with ESMTP; 06 May 2019 01:34:49 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,437,1549958400"; d="scan'208";a="155407097" From: Like Xu To: qemu-devel@nongnu.org Date: Mon, 6 May 2019 16:33:11 +0800 Message-Id: <1557131596-25403-6-git-send-email-like.xu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1557131596-25403-1-git-send-email-like.xu@linux.intel.com> References: <1557131596-25403-1-git-send-email-like.xu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH v2 05/10] cpu/topology: add hw/ppc support for smp machine properties X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Dr. David Alan Gilbert" , Paolo Bonzini , Alistair Francis , Igor Mammedov , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Following the replace rules, the global smp variables in ppc are replaced with smp machine properties. No semantic changes. Signed-off-by: Like Xu --- hw/ppc/e500.c | 3 +++ hw/ppc/mac_newworld.c | 3 ++- hw/ppc/mac_oldworld.c | 3 ++- hw/ppc/pnv.c | 6 ++++-- hw/ppc/prep.c | 4 ++-- hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++-------- hw/ppc/spapr_rtas.c | 4 +++- 7 files changed, 42 insertions(+), 15 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index beb2efd..5e42e5a 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -307,6 +307,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, bool dry_run) { MachineState *machine =3D MACHINE(pms); + unsigned int smp_cpus =3D machine->smp.cpus; const PPCE500MachineClass *pmc =3D PPCE500_MACHINE_GET_CLASS(pms); CPUPPCState *env =3D first_cpu->env_ptr; int ret =3D -1; @@ -734,6 +735,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500Machi= neState *pms, SysBusDevice *s; int i, j, k; MachineState *machine =3D MACHINE(pms); + unsigned int smp_cpus =3D machine->smp.cpus; const PPCE500MachineClass *pmc =3D PPCE500_MACHINE_GET_CLASS(pms); =20 dev =3D qdev_create(NULL, TYPE_OPENPIC); @@ -846,6 +848,7 @@ void ppce500_init(MachineState *machine) struct boot_info *boot_info; int dt_size; int i; + unsigned int smp_cpus =3D machine->smp.cpus; /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and * 4 respectively */ unsigned int pci_irq_nrs[PCI_NUM_PINS] =3D {1, 2, 3, 4}; diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 02d8559..257b26e 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -135,6 +135,7 @@ static void ppc_core99_init(MachineState *machine) DeviceState *dev, *pic_dev; hwaddr nvram_addr =3D 0xFFF04000; uint64_t tbfreq; + unsigned int smp_cpus =3D machine->smp.cpus; =20 linux_boot =3D (kernel_filename !=3D NULL); =20 @@ -464,7 +465,7 @@ static void ppc_core99_init(MachineState *machine) sysbus_mmio_map(s, 1, CFG_ADDR + 2); =20 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpu= s); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 460cbc7..1968f05 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -99,6 +99,7 @@ static void ppc_heathrow_init(MachineState *machine) DeviceState *dev, *pic_dev; BusState *adb_bus; int bios_size; + unsigned int smp_cpus =3D machine->smp.cpus; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; @@ -322,7 +323,7 @@ static void ppc_heathrow_init(MachineState *machine) sysbus_mmio_map(s, 1, CFG_ADDR + 2); =20 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpu= s); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1e8c505..3bb1533 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -678,7 +678,8 @@ static void pnv_init(MachineState *machine) object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fat= al); object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", &error_fatal); - object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); + object_property_set_int(chip, machine->smp.cores, + "nr-cores", &error_fatal); object_property_set_bool(chip, true, "realized", &error_fatal); } g_free(chip_typename); @@ -1134,6 +1135,7 @@ static void pnv_chip_instance_init(Object *obj) =20 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { + MachineState *ms =3D MACHINE(qdev_get_machine()); Error *error =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); const char *typename =3D pnv_chip_core_typename(chip); @@ -1168,7 +1170,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Erro= r **errp) snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core= ), &error_fatal); - object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads= ", + object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-thr= eads", &error_fatal); object_property_set_int(OBJECT(pnv_core), core_hwid, CPU_CORE_PROP_CORE_ID, &error_fatal); diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index b7f459d..968fd3a 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -428,7 +428,7 @@ static void ppc_prep_init(MachineState *machine) linux_boot =3D (kernel_filename !=3D NULL); =20 /* init CPUs */ - for (i =3D 0; i < smp_cpus; i++) { + for (i =3D 0; i < machine->smp.cpus; i++) { cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); env =3D &cpu->env; =20 @@ -765,7 +765,7 @@ static void ibm_40p_init(MachineState *machine) boot_device =3D machine->boot_order[0]; } =20 - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpu= s); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7fb34de..25da337 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -105,6 +105,9 @@ */ static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) { + MachineState *ms =3D MACHINE(spapr); + unsigned int smp_threads =3D ms->smp.threads; + assert(spapr->vsmt); return (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; @@ -152,8 +155,10 @@ static void pre_2_10_vmstate_unregister_dummy_icp(int = i) =20 int spapr_max_server_number(SpaprMachineState *spapr) { + MachineState *ms =3D MACHINE(spapr); + assert(spapr->vsmt); - return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); + return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); } =20 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, @@ -286,6 +291,7 @@ static void spapr_populate_pa_features(SpaprMachineStat= e *spapr, =20 static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr) { + MachineState *ms =3D MACHINE(spapr); int ret =3D 0, offset, cpus_offset; CPUState *cs; char cpu_model[32]; @@ -295,7 +301,7 @@ static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineSt= ate *spapr) PowerPCCPU *cpu =3D POWERPC_CPU(cs); DeviceClass *dc =3D DEVICE_GET_CLASS(cs); int index =3D spapr_get_vcpu_id(cpu); - int compat_smt =3D MIN(smp_threads, ppc_compat_max_vthreads(cpu)); + int compat_smt =3D MIN(ms->smp.threads, ppc_compat_max_vthreads(cp= u)); =20 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { continue; @@ -441,6 +447,7 @@ static int spapr_populate_memory(SpaprMachineState *spa= pr, void *fdt) static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, SpaprMachineState *spapr) { + MachineState *ms =3D MACHINE(spapr); PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); @@ -452,7 +459,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, uint32_t cpufreq =3D kvm_enabled() ? kvmppc_get_clockfreq() : 10000000= 00; uint32_t page_sizes_prop[64]; size_t page_sizes_prop_size; - uint32_t vcpus_per_socket =3D smp_threads * smp_cores; + unsigned int smp_threads =3D ms->smp.threads; + uint32_t vcpus_per_socket =3D smp_threads * ms->smp.cores; uint32_t pft_size_prop[] =3D {0, cpu_to_be32(spapr->htab_shift)}; int compat_smt =3D MIN(smp_threads, ppc_compat_max_vthreads(cpu)); SpaprDrc *drc; @@ -1022,6 +1030,7 @@ int spapr_h_cas_compose_response(SpaprMachineState *s= papr, =20 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) { + MachineState *ms =3D MACHINE(spapr); int rtas; GString *hypertas =3D g_string_sized_new(256); GString *qemu_hypertas =3D g_string_sized_new(256); @@ -1032,7 +1041,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, v= oid *fdt) cpu_to_be32(max_device_addr >> 32), cpu_to_be32(max_device_addr & 0xffffffff), 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), - cpu_to_be32(max_cpus / smp_threads), + cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), }; uint32_t maxdomain =3D cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0); uint32_t maxdomains[] =3D { @@ -2540,7 +2549,7 @@ static void spapr_validate_node_memory(MachineState *= machine, Error **errp) /* find cpu slot in machine->possible_cpus by core_id */ static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *= idx) { - int index =3D id / smp_threads; + int index =3D id / ms->smp.threads; =20 if (index >=3D ms->possible_cpus->len) { return NULL; @@ -2553,10 +2562,12 @@ static CPUArchId *spapr_find_cpu_slot(MachineState = *ms, uint32_t id, int *idx) =20 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) { + MachineState *ms =3D MACHINE(spapr); Error *local_err =3D NULL; bool vsmt_user =3D !!spapr->vsmt; int kvm_smt =3D kvmppc_smt_threads(); int ret; + unsigned int smp_threads =3D ms->smp.threads; =20 if (!kvm_enabled() && (smp_threads > 1)) { error_setg(&local_err, "TCG cannot support more than 1 thread/core= " @@ -2630,6 +2641,9 @@ static void spapr_init_cpus(SpaprMachineState *spapr) SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(machine); const char *type =3D spapr_get_cpu_core_type(machine->cpu_type); const CPUArchIdList *possible_cpus; + unsigned int smp_cpus =3D machine->smp.cpus; + unsigned int smp_threads =3D machine->smp.threads; + unsigned int max_cpus =3D machine->smp.max_cpus; int boot_cores_nr =3D smp_cpus / smp_threads; int i; =20 @@ -3856,6 +3870,7 @@ static void spapr_core_pre_plug(HotplugHandler *hotpl= ug_dev, DeviceState *dev, const char *type =3D object_get_typename(OBJECT(dev)); CPUArchId *core_slot; int index; + unsigned int smp_threads =3D machine->smp.threads; =20 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { error_setg(&local_err, "CPU hotplug not supported for this machine= "); @@ -4110,14 +4125,16 @@ spapr_cpu_index_to_props(MachineState *machine, uns= igned cpu_index) =20 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int i= dx) { - return idx / smp_cores % nb_numa_nodes; + return idx / ms->smp.cores % nb_numa_nodes; } =20 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *mach= ine) { int i; + unsigned int smp_threads =3D machine->smp.threads; + unsigned int smp_cpus =3D machine->smp.cpus; const char *core_type; - int spapr_max_cores =3D max_cpus / smp_threads; + int spapr_max_cores =3D machine->smp.max_cpus / smp_threads; MachineClass *mc =3D MACHINE_GET_CLASS(machine); =20 if (!mc->has_hotpluggable_cpus) { @@ -4240,6 +4257,7 @@ int spapr_get_vcpu_id(PowerPCCPU *cpu) void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) { SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + MachineState *ms =3D MACHINE(spapr); int vcpu_id; =20 vcpu_id =3D spapr_vcpu_id(spapr, cpu_index); @@ -4248,7 +4266,7 @@ void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index= , Error **errp) error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); error_append_hint(errp, "Adjust the number of cpus to %d " "or try to raise the number of threads per core\= n", - vcpu_id * smp_threads / spapr->vsmt); + vcpu_id * ms->smp.threads / spapr->vsmt); return; } =20 diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index ee24212..c9ffe97 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -231,6 +231,8 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *c= pu, target_ulong args, uint32_t nret, target_ulong rets) { + MachineState *ms =3D MACHINE(qdev_get_machine()); + unsigned int max_cpus =3D ms->smp.max_cpus; target_ulong parameter =3D rtas_ld(args, 0); target_ulong buffer =3D rtas_ld(args, 1); target_ulong length =3D rtas_ld(args, 2); @@ -244,7 +246,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *c= pu, "MaxPlatProcs=3D%d", max_cpus, current_machine->ram_size / MiB, - smp_cpus, + ms->smp.cpus, max_cpus); ret =3D sysparm_st(buffer, length, param_val, strlen(param_val) + = 1); g_free(param_val); --=20 1.8.3.1