From nobody Mon Nov 10 11:20:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556194920; cv=none; d=zoho.com; s=zohoarc; b=I93QxbqqyWNaLY9brrZ8HylF+K7qb6ShRlJI6V/jJfns1aGaVA+nxVkctzIs8efDdw9B9dJXrlaKwN3Lm8OUWji5L/XcxMdxeMxj6p62RS4Jj5ip+Np067Rng3r5GSQvWFkdEshZrA6SPRLictEtbCrwJK0CcmewdIc/aXR6R5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556194920; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=LJMQfjNhJICi06CxhEB1p2h7e3KDvGDXWO9sqc7TYIE=; b=Obs4dQp9S1oFiQkq006K/Cus3n0gsZiPVcdtkihSNgxgffIV/aExxxnKSktre0fqUUhrR7Ksyd7buS4N6Ogi2+HUX8hLUxgMuU/XJ+dACrPVij29c23VCOhGhwqQvzHLzFOGJLaM0hQmawVsw1Y9sg8x5OwZZsnD3FyFmQMtneo= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556194920802756.2974413216392; Thu, 25 Apr 2019 05:22:00 -0700 (PDT) Received: from localhost ([127.0.0.1]:56387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hJdO1-0006qW-Rr for importer@patchew.org; Thu, 25 Apr 2019 08:21:57 -0400 Received: from eggs.gnu.org ([209.51.188.92]:43425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hJdL5-0004IN-7w for qemu-devel@nongnu.org; Thu, 25 Apr 2019 08:18:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hJdL3-0005xO-CF for qemu-devel@nongnu.org; Thu, 25 Apr 2019 08:18:55 -0400 Received: from mel.act-europe.fr ([2a02:2ab8:224:1::a0a:d2]:49055 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hJdKz-0005of-Os for qemu-devel@nongnu.org; Thu, 25 Apr 2019 08:18:51 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 2DA65813A0; Thu, 25 Apr 2019 14:18:44 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3zT0ZcBvF3fx; Thu, 25 Apr 2019 14:18:44 +0200 (CEST) Received: from localhost.localdomain.localdomain (apoitiers-155-1-191-106.w109-220.abo.wanadoo.fr [109.220.154.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id EA4C281392; Thu, 25 Apr 2019 14:18:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: qemu-devel@nongnu.org Date: Thu, 25 Apr 2019 14:18:33 +0200 Message-Id: <1556194715-24427-2-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> References: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 2a02:2ab8:224:1::a0a:d2 Subject: [Qemu-devel] [PATCH v2 1/3] leon3: add a little bootloader X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, chouteau@adacore.com, frederic.konrad@adacore.com, philmd@redhat.com, atar4qemu@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This adds a little bootloader to the leon3_machine when a ram image is given through the kernel parameter and no bios are provided: * The UART transmiter is enabled. * The TIMER is initialized. Reviewed-by: Fabien Chouteau Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: KONRAD Frederic Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc/leon3.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 74 insertions(+), 10 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 774639a..f25432c 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -1,7 +1,7 @@ /* * QEMU Leon3 System Emulator * - * Copyright (c) 2010-2011 AdaCore + * Copyright (c) 2010-2019 AdaCore * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -44,6 +44,8 @@ #define CPU_CLK (40 * 1000 * 1000) =20 #define PROM_FILENAME "u-boot.bin" +#define LEON3_PROM_OFFSET (0x00000000) +#define LEON3_RAM_OFFSET (0x40000000) =20 #define MAX_PILS 16 =20 @@ -53,6 +55,59 @@ typedef struct ResetData { target_ulong sp; /* initial stack pointer */ } ResetData; =20 +static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) +{ + stl_p(code++, 0x82100000); /* mov %g0, %g1 */ + stl_p(code++, 0x84100000); /* mov %g0, %g2 */ + stl_p(code++, 0x03000000 + + extract32(addr, 10, 22)); + /* sethi %hi(addr), %g1 */ + stl_p(code++, 0x82106000 + + extract32(addr, 0, 10)); + /* or %g1, addr, %g1 */ + stl_p(code++, 0x05000000 + + extract32(val, 10, 22)); + /* sethi %hi(val), %g2 */ + stl_p(code++, 0x8410a000 + + extract32(val, 0, 10)); + /* or %g2, val, %g2 */ + stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */ + + return code; +} + +/* + * When loading a kernel in RAM the machine is expected to be in a differe= nt + * state (eg: initialized by the bootloader). This little code reproduces + * this behavior. + */ +static void write_bootloader(CPUSPARCState *env, uint8_t *base, + hwaddr kernel_addr) +{ + uint32_t *p =3D (uint32_t *) base; + + /* Initialize the UARTs */ + /* *UART_CONTROL =3D UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ + p =3D gen_store_u32(p, 0x80000108, 3); + + /* Initialize the TIMER 0 */ + /* *GPTIMER_SCALER_RELOAD =3D 40 - 1; */ + p =3D gen_store_u32(p, 0x80000304, 39); + /* *GPTIMER0_COUNTER_RELOAD =3D 0xFFFE; */ + p =3D gen_store_u32(p, 0x80000314, 0xFFFFFFFE); + /* *GPTIMER0_CONFIG =3D GPTIMER_ENABLE | GPTIMER_RESTART; */ + p =3D gen_store_u32(p, 0x80000318, 3); + + /* JUMP to the entry point */ + stl_p(p++, 0x82100000); /* mov %g0, %g1 */ + stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); + /* sethi %hi(kernel_addr), %g1 */ + stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10)); + /* or kernel_addr, %g1 */ + stl_p(p++, 0x81c04000); /* jmp %g1 */ + stl_p(p++, 0x01000000); /* nop */ +} + static void main_cpu_reset(void *opaque) { ResetData *s =3D (ResetData *)opaque; @@ -131,11 +186,12 @@ static void leon3_generic_hw_init(MachineState *machi= ne) /* Reset data */ reset_info =3D g_malloc0(sizeof(ResetData)); reset_info->cpu =3D cpu; - reset_info->sp =3D 0x40000000 + ram_size; + reset_info->sp =3D LEON3_RAM_OFFSET + ram_size; qemu_register_reset(main_cpu_reset, reset_info); =20 /* Allocate IRQ manager */ - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pi= l_in); + grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, + &leon3_set_pil_in); =20 env->qemu_irq_ack =3D leon3_irq_manager; =20 @@ -148,13 +204,13 @@ static void leon3_generic_hw_init(MachineState *machi= ne) } =20 memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size); - memory_region_add_subregion(address_space_mem, 0x40000000, ram); + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram); =20 /* Allocate BIOS */ prom_size =3D 8 * MiB; memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fat= al); memory_region_set_readonly(prom, true); - memory_region_add_subregion(address_space_mem, 0x00000000, prom); + memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom= ); =20 /* Load boot prom */ if (bios_name =3D=3D NULL) { @@ -174,7 +230,7 @@ static void leon3_generic_hw_init(MachineState *machine) } =20 if (bios_size > 0) { - ret =3D load_image_targphys(filename, 0x00000000, bios_size); + ret =3D load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size= ); if (ret < 0 || ret > prom_size) { error_report("could not load prom '%s'", filename); exit(1); @@ -198,10 +254,18 @@ static void leon3_generic_hw_init(MachineState *machi= ne) exit(1); } if (bios_size <=3D 0) { - /* If there is no bios/monitor, start the application. */ - env->pc =3D entry; - env->npc =3D entry + 4; - reset_info->entry =3D entry; + /* + * If there is no bios/monitor just start the application but = put + * the machine in an initialized state through a little + * bootloader. + */ + uint8_t *bootloader_entry; + + bootloader_entry =3D memory_region_get_ram_ptr(prom); + write_bootloader(env, bootloader_entry, entry); + env->pc =3D LEON3_PROM_OFFSET; + env->npc =3D LEON3_PROM_OFFSET + 4; + reset_info->entry =3D LEON3_PROM_OFFSET; } } =20 --=20 1.8.3.1 From nobody Mon Nov 10 11:20:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556195007; cv=none; d=zoho.com; s=zohoarc; b=Hub4geiFkvj20zNGszIvLKaP+fzQTROh0spXc/mY3iOfe2QM0W0HSW9DLdS8U64tYaBtFbVbVVrVqlJiOV1rgmPg3jL3gRkRoaInXhmXASrU1RKUPJLKJUyId19D91pFe2+qJbVE15XBetkgyK5uiTznmaqVEcs0zrHQnyu348E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556195007; 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Thu, 25 Apr 2019 14:18:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: qemu-devel@nongnu.org Date: Thu, 25 Apr 2019 14:18:34 +0200 Message-Id: <1556194715-24427-3-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> References: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 194.98.77.210 Subject: [Qemu-devel] [PATCH v2 2/3] leon3: introduce the plug and play mecanism X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, chouteau@adacore.com, frederic.konrad@adacore.com, philmd@redhat.com, atar4qemu@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds the AHB and APB plug and play devices. They are scanned during the linux boot to discover the various peripheral. Reviewed-by: Fabien Chouteau Signed-off-by: KONRAD Frederic --- hw/misc/Makefile.objs | 2 + hw/misc/grlib_ahb_apb_pnp.c | 269 ++++++++++++++++++++++++++++++++= ++++ hw/sparc/leon3.c | 34 ++++- include/hw/misc/grlib_ahb_apb_pnp.h | 60 ++++++++ include/hw/sparc/grlib.h | 35 +++-- 5 files changed, 382 insertions(+), 18 deletions(-) create mode 100644 hw/misc/grlib_ahb_apb_pnp.c create mode 100644 include/hw/misc/grlib_ahb_apb_pnp.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c71e07a..77b9df9 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -77,3 +77,5 @@ obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o obj-$(CONFIG_NRF51_SOC) +=3D nrf51_rng.o + +obj-$(CONFIG_GRLIB) +=3D grlib_ahb_apb_pnp.o diff --git a/hw/misc/grlib_ahb_apb_pnp.c b/hw/misc/grlib_ahb_apb_pnp.c new file mode 100644 index 0000000..90d5f6e --- /dev/null +++ b/hw/misc/grlib_ahb_apb_pnp.c @@ -0,0 +1,269 @@ +/* + * GRLIB AHB APB PNP + * + * Copyright (C) 2019 AdaCore + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/misc/grlib_ahb_apb_pnp.h" + +#define GRLIB_PNP_VENDOR_SHIFT (24) +#define GRLIB_PNP_VENDOR_SIZE (8) +#define GRLIB_PNP_DEV_SHIFT (12) +#define GRLIB_PNP_DEV_SIZE (12) +#define GRLIB_PNP_VER_SHIFT (5) +#define GRLIB_PNP_VER_SIZE (5) +#define GRLIB_PNP_IRQ_SHIFT (0) +#define GRLIB_PNP_IRQ_SIZE (5) +#define GRLIB_PNP_ADDR_SHIFT (20) +#define GRLIB_PNP_ADDR_SIZE (12) +#define GRLIB_PNP_MASK_SHIFT (4) +#define GRLIB_PNP_MASK_SIZE (12) + +#define GRLIB_AHB_DEV_ADDR_SHIFT (20) +#define GRLIB_AHB_DEV_ADDR_SIZE (12) +#define GRLIB_AHB_ENTRY_SIZE (0x20) +#define GRLIB_AHB_MAX_DEV (64) +#define GRLIB_AHB_SLAVE_OFFSET (0x800) + +#define GRLIB_APB_DEV_ADDR_SHIFT (8) +#define GRLIB_APB_DEV_ADDR_SIZE (12) +#define GRLIB_APB_ENTRY_SIZE (0x08) +#define GRLIB_APB_MAX_DEV (512) + +#define GRLIB_PNP_MAX_REGS (0x1000) + +typedef struct AHBPnp { + SysBusDevice parent_obj; + MemoryRegion iomem; + + uint32_t regs[GRLIB_PNP_MAX_REGS >> 2]; + uint8_t master_count; + uint8_t slave_count; +} AHBPnp; + +void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask, + uint8_t vendor, uint16_t device, int slave, + int type) +{ + unsigned int reg_start; + + /* + * AHB entries look like this: + * + * 31 -------- 23 -------- 11 ----- 9 -------- 4 --- 0 + * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ | + * -------------------------------------------------- + * | USER | + * -------------------------------------------------- + * | USER | + * -------------------------------------------------- + * | USER | + * -------------------------------------------------- + * | USER | + * -------------------------------------------------- + * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 + * | ADDR[31..12] | 00PC | MASK | TYPE | + * -------------------------------------------------- + * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 + * | ADDR[31..12] | 00PC | MASK | TYPE | + * -------------------------------------------------- + * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 + * | ADDR[31..12] | 00PC | MASK | TYPE | + * -------------------------------------------------- + * 31 ----------- 20 --- 15 ----------------- 3 ---- 0 + * | ADDR[31..12] | 00PC | MASK | TYPE | + * -------------------------------------------------- + */ + + if (slave) { + assert(dev->slave_count < GRLIB_AHB_MAX_DEV); + reg_start =3D (GRLIB_AHB_SLAVE_OFFSET + + (dev->slave_count * GRLIB_AHB_ENTRY_SIZE)) >> 2; + dev->slave_count++; + } else { + assert(dev->master_count < GRLIB_AHB_MAX_DEV); + reg_start =3D (dev->master_count * GRLIB_AHB_ENTRY_SIZE) >> 2; + dev->master_count++; + } + + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_VENDOR_SHIFT, + GRLIB_PNP_VENDOR_SIZE, + vendor); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_DEV_SHIFT, + GRLIB_PNP_DEV_SIZE, + device); + reg_start +=3D 4; + /* AHB Memory Space */ + dev->regs[reg_start] =3D type; + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_ADDR_SHIFT, + GRLIB_PNP_ADDR_SIZE, + extract32(address, + GRLIB_AHB_DEV_ADDR_SHIFT, + GRLIB_AHB_DEV_ADDR_SIZE)); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_MASK_SHIFT, + GRLIB_PNP_MASK_SIZE, + mask); +} + +static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + AHBPnp *ahb_pnp =3D GRLIB_AHB_PNP(opaque); + + return ahb_pnp->regs[offset >> 2]; +} + +static const MemoryRegionOps grlib_ahb_pnp_ops =3D { + .read =3D grlib_ahb_pnp_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp) +{ + AHBPnp *ahb_pnp =3D GRLIB_AHB_PNP(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&ahb_pnp->iomem, OBJECT(dev), &grlib_ahb_pnp_ops, + ahb_pnp, TYPE_GRLIB_AHB_PNP, GRLIB_PNP_MAX_REGS); + sysbus_init_mmio(sbd, &ahb_pnp->iomem); +} + +static void grlib_ahb_pnp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D grlib_ahb_pnp_realize; +} + +static const TypeInfo grlib_ahb_pnp_info =3D { + .name =3D TYPE_GRLIB_AHB_PNP, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AHBPnp), + .class_init =3D grlib_ahb_pnp_class_init, +}; + +/* APBPnp */ + +typedef struct APBPnp { + SysBusDevice parent_obj; + MemoryRegion iomem; + + uint32_t regs[GRLIB_PNP_MAX_REGS >> 2]; + uint32_t entry_count; +} APBPnp; + +void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask, + uint8_t vendor, uint16_t device, uint8_t vers= ion, + uint8_t irq, int type) +{ + unsigned int reg_start; + + /* + * APB entries look like this: + * + * 31 -------- 23 -------- 11 ----- 9 ------- 4 --- 0 + * | VENDOR ID | DEVICE ID | IRQ ? | VERSION | IRQ | + * + * 31 ---------- 20 --- 15 ----------------- 3 ---- 0 + * | ADDR[20..8] | 0000 | MASK | TYPE | + */ + + assert(dev->entry_count < GRLIB_APB_MAX_DEV); + reg_start =3D (dev->entry_count * GRLIB_APB_ENTRY_SIZE) >> 2; + dev->entry_count++; + + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_VENDOR_SHIFT, + GRLIB_PNP_VENDOR_SIZE, + vendor); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_DEV_SHIFT, + GRLIB_PNP_DEV_SIZE, + device); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_VER_SHIFT, + GRLIB_PNP_VER_SIZE, + version); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_IRQ_SHIFT, + GRLIB_PNP_IRQ_SIZE, + irq); + reg_start +=3D 1; + dev->regs[reg_start] =3D type; + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_ADDR_SHIFT, + GRLIB_PNP_ADDR_SIZE, + extract32(address, + GRLIB_APB_DEV_ADDR_SHIFT, + GRLIB_APB_DEV_ADDR_SIZE)); + dev->regs[reg_start] =3D deposit32(dev->regs[reg_start], + GRLIB_PNP_MASK_SHIFT, + GRLIB_PNP_MASK_SIZE, + mask); +} + +static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + APBPnp *apb_pnp =3D GRLIB_APB_PNP(opaque); + + return apb_pnp->regs[offset >> 2]; +} + +static const MemoryRegionOps grlib_apb_pnp_ops =3D { + .read =3D grlib_apb_pnp_read, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp) +{ + APBPnp *apb_pnp =3D GRLIB_APB_PNP(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&apb_pnp->iomem, OBJECT(dev), &grlib_apb_pnp_ops, + apb_pnp, TYPE_GRLIB_APB_PNP, GRLIB_PNP_MAX_REGS); + sysbus_init_mmio(sbd, &apb_pnp->iomem); +} + +static void grlib_apb_pnp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D grlib_apb_pnp_realize; +} + +static const TypeInfo grlib_apb_pnp_info =3D { + .name =3D TYPE_GRLIB_APB_PNP, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(APBPnp), + .class_init =3D grlib_apb_pnp_class_init, +}; + +static void grlib_ahb_apb_pnp_register_types(void) +{ + type_register_static(&grlib_ahb_pnp_info); + type_register_static(&grlib_apb_pnp_info); +} + +type_init(grlib_ahb_apb_pnp_register_types) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index f25432c..03ff163 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -46,6 +46,13 @@ #define PROM_FILENAME "u-boot.bin" #define LEON3_PROM_OFFSET (0x00000000) #define LEON3_RAM_OFFSET (0x40000000) +#define LEON3_APBUART_OFFSET (0x80000100) +#define LEON3_APBUART_IRQ (0x3) +#define LEON3_IRQMP_OFFSET (0x80000200) +#define LEON3_GPTIMER_OFFSET (0x80000300) +#define LEON3_GPTIMER_IRQ (0x6) +#define LEON3_APB_PNP_OFFSET (0x800FF000) +#define LEON3_AHB_PNP_OFFSET (0xFFFFF000) =20 #define MAX_PILS 16 =20 @@ -176,6 +183,8 @@ static void leon3_generic_hw_init(MachineState *machine) int bios_size; int prom_size; ResetData *reset_info; + AHBPnp *ahb_pnp; + APBPnp *apb_pnp; =20 /* Init CPU */ cpu =3D SPARC_CPU(cpu_create(machine->cpu_type)); @@ -189,9 +198,23 @@ static void leon3_generic_hw_init(MachineState *machin= e) reset_info->sp =3D LEON3_RAM_OFFSET + ram_size; qemu_register_reset(main_cpu_reset, reset_info); =20 + ahb_pnp =3D GRLIB_AHB_PNP(object_new(TYPE_GRLIB_AHB_PNP)); + object_property_set_bool(OBJECT(ahb_pnp), true, "realized", &error_fat= al); + sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET); + grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER, + GRLIB_LEON3_DEV, GRLIB_AHB_MASTER, + GRLIB_CPU_AREA); + + apb_pnp =3D GRLIB_APB_PNP(object_new(TYPE_GRLIB_APB_PNP)); + object_property_set_bool(OBJECT(apb_pnp), true, "realized", &error_fat= al); + sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET); + grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF, + GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV, + GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA); + /* Allocate IRQ manager */ - grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, - &leon3_set_pil_in); + grlib_irqmp_create(LEON3_IRQMP_OFFSET, env, &cpu_irqs, MAX_PILS, + &leon3_set_pil_in, apb_pnp); =20 env->qemu_irq_ack =3D leon3_irq_manager; =20 @@ -270,11 +293,14 @@ static void leon3_generic_hw_init(MachineState *machi= ne) } =20 /* Allocate timers */ - grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6); + grlib_gptimer_create(LEON3_GPTIMER_OFFSET, 2, CPU_CLK, cpu_irqs, + LEON3_GPTIMER_IRQ, + apb_pnp); =20 /* Allocate uart */ if (serial_hd(0)) { - grlib_apbuart_create(0x80000100, serial_hd(0), cpu_irqs[3]); + grlib_apbuart_create(LEON3_APBUART_OFFSET, serial_hd(0), cpu_irqs, + LEON3_APBUART_IRQ, apb_pnp); } } =20 diff --git a/include/hw/misc/grlib_ahb_apb_pnp.h b/include/hw/misc/grlib_ah= b_apb_pnp.h new file mode 100644 index 0000000..a0f6dcf --- /dev/null +++ b/include/hw/misc/grlib_ahb_apb_pnp.h @@ -0,0 +1,60 @@ +/* + * GRLIB AHB APB PNP + * + * Copyright (C) 2019 AdaCore + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef GRLIB_AHB_APB_PNP_H +#define GRLIB_AHB_APB_PNP_H + +#define TYPE_GRLIB_AHB_PNP "grlib,ahbpnp" +#define GRLIB_AHB_PNP(obj) \ + OBJECT_CHECK(AHBPnp, (obj), TYPE_GRLIB_AHB_PNP) +typedef struct AHBPnp AHBPnp; + +#define TYPE_GRLIB_APB_PNP "grlib,apbpnp" +#define GRLIB_APB_PNP(obj) \ + OBJECT_CHECK(APBPnp, (obj), TYPE_GRLIB_APB_PNP) +typedef struct APBPnp APBPnp; + +void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask, + uint8_t vendor, uint16_t device, int slave, + int type); +void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask, + uint8_t vendor, uint16_t device, uint8_t vers= ion, + uint8_t irq, int type); + +/* VENDORS */ +#define GRLIB_VENDOR_GAISLER (0x01) +/* DEVICES */ +#define GRLIB_LEON3_DEV (0x03) +#define GRLIB_APBMST_DEV (0x06) +#define GRLIB_APBUART_DEV (0x0C) +#define GRLIB_IRQMP_DEV (0x0D) +#define GRLIB_GPTIMER_DEV (0x11) +/* TYPE */ +#define GRLIB_CPU_AREA (0x00) +#define GRLIB_APBIO_AREA (0x01) +#define GRLIB_AHBMEM_AREA (0x02) + +#define GRLIB_AHB_MASTER (0x00) +#define GRLIB_AHB_SLAVE (0x01) + +#endif /* GRLIB_AHB_APB_PNP_H */ diff --git a/include/hw/sparc/grlib.h b/include/hw/sparc/grlib.h index 61a345c..28320ab 100644 --- a/include/hw/sparc/grlib.h +++ b/include/hw/sparc/grlib.h @@ -27,6 +27,7 @@ =20 #include "hw/qdev.h" #include "hw/sysbus.h" +#include "hw/misc/grlib_ahb_apb_pnp.h" =20 /* Emulation of GrLib device is base on the GRLIB IP Core User's Manual: * http://www.gaisler.com/products/grlib/grip.pdf @@ -41,11 +42,9 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int leve= l); void grlib_irqmp_ack(DeviceState *dev, int intno); =20 static inline -DeviceState *grlib_irqmp_create(hwaddr base, - CPUSPARCState *env, - qemu_irq **cpu_irqs, - uint32_t nr_irqs, - set_pil_in_fn set_pil_in) +DeviceState *grlib_irqmp_create(hwaddr base, CPUSPARCState *env, + qemu_irq **cpu_irqs, uint32_t nr_irqs, + set_pil_in_fn set_pil_in, APBPnp *apb_pnp) { DeviceState *dev; =20 @@ -65,17 +64,18 @@ DeviceState *grlib_irqmp_create(hwaddr base, dev, nr_irqs); =20 + /* Register this device in the APB PNP device */ + grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER, + GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA); return dev; } =20 /* GPTimer */ =20 static inline -DeviceState *grlib_gptimer_create(hwaddr base, - uint32_t nr_timers, - uint32_t freq, - qemu_irq *cpu_irqs, - int base_irq) +DeviceState *grlib_gptimer_create(hwaddr base, uint32_t nr_timers, + uint32_t freq, qemu_irq *cpu_irqs, + int base_irq, APBPnp *apb_pnp) { DeviceState *dev; int i; @@ -93,15 +93,18 @@ DeviceState *grlib_gptimer_create(hwaddr base, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]); } =20 + /* Register this device in the APB PNP device */ + grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER, + GRLIB_GPTIMER_DEV, 0, base_irq, GRLIB_APBIO_AR= EA); return dev; } =20 /* APB UART */ =20 static inline -DeviceState *grlib_apbuart_create(hwaddr base, - Chardev *serial, - qemu_irq irq) +DeviceState *grlib_apbuart_create(hwaddr base, Chardev *serial, + qemu_irq *cpu_irqs, int base_irq, + APBPnp *apb_pnp) { DeviceState *dev; =20 @@ -112,7 +115,11 @@ DeviceState *grlib_apbuart_create(hwaddr base, =20 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); =20 - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[base_irq]); + + /* Register this device in the APB PNP device */ + grlib_apb_pnp_add_entry(apb_pnp, base, 0xFFF, GRLIB_VENDOR_GAISLER, + GRLIB_APBUART_DEV, 1, base_irq, GRLIB_APBIO_AR= EA); =20 return dev; } --=20 1.8.3.1 From nobody Mon Nov 10 11:20:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 25 Apr 2019 08:18:51 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id B3D0B81390; Thu, 25 Apr 2019 14:18:44 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xYo6_VBuWFfX; Thu, 25 Apr 2019 14:18:44 +0200 (CEST) Received: from localhost.localdomain.localdomain (apoitiers-155-1-191-106.w109-220.abo.wanadoo.fr [109.220.154.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 686AB81392; Thu, 25 Apr 2019 14:18:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: qemu-devel@nongnu.org Date: Thu, 25 Apr 2019 14:18:35 +0200 Message-Id: <1556194715-24427-4-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> References: <1556194715-24427-1-git-send-email-frederic.konrad@adacore.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 194.98.77.210 Subject: [Qemu-devel] [PATCH v2 3/3] MAINTAINERS: add myself for leon3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, chouteau@adacore.com, frederic.konrad@adacore.com, philmd@redhat.com, atar4qemu@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Fabien Chouteau Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: KONRAD Frederic Reviewed-by: Mark Cave-Ayland --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 23db6f8..6f7d237 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1151,6 +1151,7 @@ F: include/hw/timer/sun4v-rtc.h =20 Leon3 M: Fabien Chouteau +M: KONRAD Frederic S: Maintained F: hw/sparc/leon3.c F: hw/*/grlib* --=20 1.8.3.1