From nobody Tue Feb 10 00:59:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019206; cv=none; d=zoho.com; s=zohoarc; b=JWiJHYpTMWqSQRtGGtuIiBZMOVrwUGJR5LXWpiF1jIyz21nXXRTyWMjZLP3UIRGIvQBAmbG3f926tmSRVgv7PxeY7Lm50pzqhQUrz4/EtxWssEVA5BAsCe7Fx3ejppvb09BcyM/7Z5fMZ3+hnexTRdjFHkTB8xpmXg0e1dknl4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019206; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Rp+NsZuOscmRrApZSi4dQJUVx3HO64VIsxkMJ99W9UE=; b=chL7cyD7m63TX2t+LMW1BrvtIwmErI4DD242Y28X5aO5LlkMO8LZdU7Z4ONPfSb+uxir0zdNOqqDfkFTTRXnKNEzyBAfeFnbQ4LSMNg7HqFYQlygTNwfpdShEJbOjcq1ddXX/FqXorX61vlOokj8j7sEaMltYQYWyHGJ07KO+hs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556019206641190.7443251126665; Tue, 23 Apr 2019 04:33:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:52078 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItfs-0002r2-Kj for importer@patchew.org; Tue, 23 Apr 2019 07:33:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItdb-0001e1-Ti for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:31:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItda-0005YI-FH for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:59 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45019 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItda-0005WP-3V for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8A4DA1A2460; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5FC951A2447; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:39 +0200 Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 5/8] target/mips: Clean up dsp_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/dsp_helper.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/target/mips/dsp_helper.c b/target/mips/dsp_helper.c index 739b69d..8c58eeb 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/dsp_helper.c @@ -22,8 +22,10 @@ #include "exec/helper-proto.h" #include "qemu/bitops.h" =20 -/* As the byte ordering doesn't matter, i.e. all columns are treated - identically, these unions can be used directly. */ +/* + * As the byte ordering doesn't matter, i.e. all columns are treated + * identically, these unions can be used directly. + */ typedef union { uint8_t ub[4]; int8_t sb[4]; @@ -1445,9 +1447,15 @@ target_ulong helper_precr_ob_qh(target_ulong rs, tar= get_ulong rt) return temp; } =20 -#define PRECR_QH_PW(name, var) \ -target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt,= \ - uint32_t sa) \ + +/* + * In case sa =3D=3D 0, use rt2, rt0, rs2, rs0. + * In case sa !=3D 0, use rt3, rt1, rs3, rs1. + */ +#define PRECR_QH_PW(name, var) \ +target_ulong helper_precr_##name##_qh_pw(target_ulong rs, \ + target_ulong rt, \ + uint32_t sa) \ { \ uint16_t rs3, rs2, rs1, rs0; \ uint16_t rt3, rt2, rt1, rt0; \ @@ -1456,8 +1464,6 @@ target_ulong helper_precr_##name##_qh_pw(target_ulong= rs, target_ulong rt, \ MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ \ - /* When sa =3D 0, we use rt2, rt0, rs2, rs0; \ - * when sa !=3D 0, we use rt3, rt1, rs3, rs1. */ \ if (sa =3D=3D 0) { \ tempD =3D rt2 << var; \ tempC =3D rt0 << var; \ @@ -1965,7 +1971,8 @@ SHIFT_PH(shra_r, rnd16_rashift); #undef SHIFT_PH =20 /** DSP Multiply Sub-class insns **/ -/* Return value made up by two 16bits value. +/* + * Return value made up by two 16bits value. * FIXME give the macro a better name. */ #define MUL_RETURN32_16_PH(name, func, \ @@ -3274,11 +3281,15 @@ target_ulong helper_dextr_l(target_ulong ac, target= _ulong shift, CPUMIPSState *env) { uint64_t temp[3]; + target_ulong ret; =20 shift =3D shift & 0x3F; =20 mipsdsp_rndrashift_acc(temp, ac, shift, env); - return (temp[1] << 63) | (temp[0] >> 1); + + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } =20 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, @@ -3286,6 +3297,7 @@ target_ulong helper_dextr_r_l(target_ulong ac, target= _ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; =20 shift =3D shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3305,7 +3317,9 @@ target_ulong helper_dextr_r_l(target_ulong ac, target= _ulong shift, set_DSPControl_overflow_flag(1, 23, env); } =20 - return (temp[1] << 63) | (temp[0] >> 1); + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } =20 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, @@ -3313,6 +3327,7 @@ target_ulong helper_dextr_rs_l(target_ulong ac, targe= t_ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; =20 shift =3D shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3338,7 +3353,10 @@ target_ulong helper_dextr_rs_l(target_ulong ac, targ= et_ulong shift, } set_DSPControl_overflow_flag(1, 23, env); } - return (temp[1] << 63) | (temp[0] >> 1); + + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } #endif =20 --=20 2.7.4