From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019453; cv=none; d=zoho.com; s=zohoarc; b=StZPL/hvwDEgbx6FFM0OVjD3JviLIWb+Q7r1q80chohmtSnOFpWhYvg8/GQn/APEuYaDju4xjkfhHBs0/NRAmgoAWxQcSSD2plcAgQO5HsgNNlVFPwhqaoht/cPOO8xgnwWqajqp2slOAhG1NQRrCcXbCrNdQSB2CAISFFjI2Ds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019453; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=d6k8JSt5KXe+fVTCUuchkWRHyVrCovEpUSHhpejkjWs=; b=eOJdM+PBH07PNbVK+p23XivJIXCqp27tua/scnJXdFw42iWn0BnrMb9YIyB3JxCOos+hAjl89OfaZX3YA3kXaK4aINTWTUA7X6kelibbcEyZiwEY2jBgbERp1FJrb/C2iNlCeXHdYq0rJc9L8DyND0YKX8kDkwFHr/q9IlczVyQ= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556019453416147.1639624784916; Tue, 23 Apr 2019 04:37:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:52146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItjw-00068J-EI for importer@patchew.org; Tue, 23 Apr 2019 07:37:32 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36454) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItda-0001dM-SH for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:31:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItdZ-0005WL-9C for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41167 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItdY-0004Av-TP for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5621E1A2435; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 324861A242D; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:35 +0200 Message-Id: <1556018982-3715-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 1/8] target/mips: Add or remove space to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jules Irenge Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" "ERROR: line over 90 characters" within target/mips/cpu.h file. Signed-off-by: Jules Irenge Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com> --- target/mips/cpu.h | 177 +++++++++++++++++++++++++++++---------------------= ---- 1 file changed, 95 insertions(+), 82 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0..469f3ef 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 typedef union wr_t wr_t; union wr_t { - int8_t b[MSA_WRLEN/8]; - int16_t h[MSA_WRLEN/16]; - int32_t w[MSA_WRLEN/32]; - int64_t d[MSA_WRLEN/64]; + int8_t b[MSA_WRLEN / 8]; + int16_t h[MSA_WRLEN / 16]; + int32_t w[MSA_WRLEN / 32]; + int64_t d[MSA_WRLEN / 64]; }; =20 typedef union fpr_t fpr_t; @@ -71,16 +71,29 @@ struct CPUMIPSFPUContext { #define FCR31_FS 24 #define FCR31_ABS2008 19 #define FCR31_NAN2008 18 -#define SET_FP_COND(num,env) do { ((env).fcr31) |=3D ((num) ? (1 << ((= num) + 24)) : (1 << 23)); } while(0) -#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &=3D ~((num) ? (1 << (= (num) + 24)) : (1 << 23)); } while(0) -#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).f= cr31 >> 23) & 0x1)) +#define SET_FP_COND(num, env) do { ((env).fcr31) |=3D \ + ((num) ? (1 << ((num) + 24)) : \ + (1 << 23)); \ + } while (0) +#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &=3D \ + ~((num) ? (1 << ((num) + 24)) : \ + (1 << 23)); \ + } while (0) +#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ + (((env).fcr31 >> 23) & 0x1)) #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) -#define SET_FP_CAUSE(reg,v) do { (reg) =3D ((reg) & ~(0x3f << 12)) | = ((v & 0x3f) << 12); } while(0) -#define SET_FP_ENABLE(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 7)) | = ((v & 0x1f) << 7); } while(0) -#define SET_FP_FLAGS(reg,v) do { (reg) =3D ((reg) & ~(0x1f << 2)) | = ((v & 0x1f) << 2); } while(0) -#define UPDATE_FP_FLAGS(reg,v) do { (reg) |=3D ((v & 0x1f) << 2); } whil= e(0) +#define SET_FP_CAUSE(reg, v) do { (reg) =3D ((reg) & ~(0x3f << 12)) |= \ + ((v & 0x3f) << 12); \ + } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 7)) |= \ + ((v & 0x1f) << 7); \ + } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) =3D ((reg) & ~(0x1f << 2)) |= \ + ((v & 0x1f) << 2); \ + } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |=3D ((v & 0x1f) << 2); } whi= le (0) #define FP_INEXACT 1 #define FP_UNDERFLOW 2 #define FP_OVERFLOW 4 @@ -95,25 +108,25 @@ struct CPUMIPSFPUContext { typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; -#define CP0MVPCo_CPA 3 -#define CP0MVPCo_STLB 2 -#define CP0MVPCo_VPC 1 -#define CP0MVPCo_EVP 0 +#define CP0MVPCo_CPA 3 +#define CP0MVPCo_STLB 2 +#define CP0MVPCo_VPC 1 +#define CP0MVPCo_EVP 0 int32_t CP0_MVPConf0; -#define CP0MVPC0_M 31 -#define CP0MVPC0_TLBS 29 -#define CP0MVPC0_GS 28 -#define CP0MVPC0_PCP 27 -#define CP0MVPC0_PTLBE 16 -#define CP0MVPC0_TCA 15 -#define CP0MVPC0_PVPE 10 -#define CP0MVPC0_PTC 0 +#define CP0MVPC0_M 31 +#define CP0MVPC0_TLBS 29 +#define CP0MVPC0_GS 28 +#define CP0MVPC0_PCP 27 +#define CP0MVPC0_PTLBE 16 +#define CP0MVPC0_TCA 15 +#define CP0MVPC0_PVPE 10 +#define CP0MVPC0_PTC 0 int32_t CP0_MVPConf1; -#define CP0MVPC1_CIM 31 -#define CP0MVPC1_CIF 30 -#define CP0MVPC1_PCX 20 -#define CP0MVPC1_PCP2 10 -#define CP0MVPC1_PCP1 0 +#define CP0MVPC1_CIM 31 +#define CP0MVPC1_CIF 30 +#define CP0MVPC1_PCX 20 +#define CP0MVPC1_PCP2 10 +#define CP0MVPC1_PCP1 0 }; =20 typedef struct mips_def_t mips_def_t; @@ -481,44 +494,44 @@ struct CPUMIPSState { */ int32_t CP0_Random; int32_t CP0_VPEControl; -#define CP0VPECo_YSI 21 -#define CP0VPECo_GSI 20 -#define CP0VPECo_EXCPT 16 -#define CP0VPECo_TE 15 -#define CP0VPECo_TargTC 0 +#define CP0VPECo_YSI 21 +#define CP0VPECo_GSI 20 +#define CP0VPECo_EXCPT 16 +#define CP0VPECo_TE 15 +#define CP0VPECo_TargTC 0 int32_t CP0_VPEConf0; -#define CP0VPEC0_M 31 -#define CP0VPEC0_XTC 21 -#define CP0VPEC0_TCS 19 -#define CP0VPEC0_SCS 18 -#define CP0VPEC0_DSC 17 -#define CP0VPEC0_ICS 16 -#define CP0VPEC0_MVP 1 -#define CP0VPEC0_VPA 0 +#define CP0VPEC0_M 31 +#define CP0VPEC0_XTC 21 +#define CP0VPEC0_TCS 19 +#define CP0VPEC0_SCS 18 +#define CP0VPEC0_DSC 17 +#define CP0VPEC0_ICS 16 +#define CP0VPEC0_MVP 1 +#define CP0VPEC0_VPA 0 int32_t CP0_VPEConf1; -#define CP0VPEC1_NCX 20 -#define CP0VPEC1_NCP2 10 -#define CP0VPEC1_NCP1 0 +#define CP0VPEC1_NCX 20 +#define CP0VPEC1_NCP2 10 +#define CP0VPEC1_NCP1 0 target_ulong CP0_YQMask; target_ulong CP0_VPESchedule; target_ulong CP0_VPEScheFBack; int32_t CP0_VPEOpt; -#define CP0VPEOpt_IWX7 15 -#define CP0VPEOpt_IWX6 14 -#define CP0VPEOpt_IWX5 13 -#define CP0VPEOpt_IWX4 12 -#define CP0VPEOpt_IWX3 11 -#define CP0VPEOpt_IWX2 10 -#define CP0VPEOpt_IWX1 9 -#define CP0VPEOpt_IWX0 8 -#define CP0VPEOpt_DWX7 7 -#define CP0VPEOpt_DWX6 6 -#define CP0VPEOpt_DWX5 5 -#define CP0VPEOpt_DWX4 4 -#define CP0VPEOpt_DWX3 3 -#define CP0VPEOpt_DWX2 2 -#define CP0VPEOpt_DWX1 1 -#define CP0VPEOpt_DWX0 0 +#define CP0VPEOpt_IWX7 15 +#define CP0VPEOpt_IWX6 14 +#define CP0VPEOpt_IWX5 13 +#define CP0VPEOpt_IWX4 12 +#define CP0VPEOpt_IWX3 11 +#define CP0VPEOpt_IWX2 10 +#define CP0VPEOpt_IWX1 9 +#define CP0VPEOpt_IWX0 8 +#define CP0VPEOpt_DWX7 7 +#define CP0VPEOpt_DWX6 6 +#define CP0VPEOpt_DWX5 5 +#define CP0VPEOpt_DWX4 4 +#define CP0VPEOpt_DWX3 3 +#define CP0VPEOpt_DWX2 2 +#define CP0VPEOpt_DWX1 1 +#define CP0VPEOpt_DWX0 0 /* * CP0 Register 2 */ @@ -625,33 +638,33 @@ struct CPUMIPSState { #define CP0PC_PSN 0 /* 5..0 */ int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; -#define CP0SRSC0_M 31 -#define CP0SRSC0_SRS3 20 -#define CP0SRSC0_SRS2 10 -#define CP0SRSC0_SRS1 0 +#define CP0SRSC0_M 31 +#define CP0SRSC0_SRS3 20 +#define CP0SRSC0_SRS2 10 +#define CP0SRSC0_SRS1 0 int32_t CP0_SRSConf1_rw_bitmask; int32_t CP0_SRSConf1; -#define CP0SRSC1_M 31 -#define CP0SRSC1_SRS6 20 -#define CP0SRSC1_SRS5 10 -#define CP0SRSC1_SRS4 0 +#define CP0SRSC1_M 31 +#define CP0SRSC1_SRS6 20 +#define CP0SRSC1_SRS5 10 +#define CP0SRSC1_SRS4 0 int32_t CP0_SRSConf2_rw_bitmask; int32_t CP0_SRSConf2; -#define CP0SRSC2_M 31 -#define CP0SRSC2_SRS9 20 -#define CP0SRSC2_SRS8 10 -#define CP0SRSC2_SRS7 0 +#define CP0SRSC2_M 31 +#define CP0SRSC2_SRS9 20 +#define CP0SRSC2_SRS8 10 +#define CP0SRSC2_SRS7 0 int32_t CP0_SRSConf3_rw_bitmask; int32_t CP0_SRSConf3; -#define CP0SRSC3_M 31 -#define CP0SRSC3_SRS12 20 -#define CP0SRSC3_SRS11 10 -#define CP0SRSC3_SRS10 0 +#define CP0SRSC3_M 31 +#define CP0SRSC3_SRS12 20 +#define CP0SRSC3_SRS11 10 +#define CP0SRSC3_SRS10 0 int32_t CP0_SRSConf4_rw_bitmask; int32_t CP0_SRSConf4; -#define CP0SRSC4_SRS15 20 -#define CP0SRSC4_SRS14 10 -#define CP0SRSC4_SRS13 0 +#define CP0SRSC4_SRS15 20 +#define CP0SRSC4_SRS14 10 +#define CP0SRSC4_SRS13 0 /* * CP0 Register 7 */ @@ -1065,7 +1078,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState = *env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); +void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list @@ -1090,7 +1103,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } =20 -static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) +static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) { return hflags_mmu_index(env->hflags); } @@ -1182,7 +1195,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); void itc_reconfigure(struct MIPSITUState *tag); =20 /* helper.c */ -target_ulong exception_resume_pc (CPUMIPSState *env); +target_ulong exception_resume_pc(CPUMIPSState *env); =20 static inline void restore_snan_bit_mode(CPUMIPSState *env) { --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019347; cv=none; d=zoho.com; s=zohoarc; b=cctdlSbPKbIWqJrqtIOPhFzzZA6dYbcnfCS6X5TlCBgG1pWO+Mo4X07u5f2FsgYqNsKOeN5fxFpFldpjWDyfqUuOv2vmCGnoSm1oo1i9rJQPxXf4608Bls5c+vnjw2Opo8pboaOuDKG0TvKqFHQM87/hMZxx2pRQ5fiYrxWrGl4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019347; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 23 Apr 2019 07:30:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41178 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItdY-0004B0-TN for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 627081A244E; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3FB101A2434; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:36 +0200 Message-Id: <1556018982-3715-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 2/8] target/mips: Realign comments to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jules Irenge Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within target/mips/cpu.h file. Signed-off-by: Jules Irenge Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com> --- target/mips/cpu.h | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 469f3ef..5819cb9 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + *define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -976,9 +977,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -988,18 +991,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping= */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1086,8 +1093,10 @@ void mips_cpu_list(FILE *f, fprintf_function cpu_fpr= intf); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); =20 -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1110,7 +1119,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) =20 #include "exec/cpu-all.h" =20 -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019440; cv=none; d=zoho.com; s=zohoarc; b=Di0FVR2W2YXukHFzqSW3nd2miSplsTMKGPSN0OlHPcZOKRNVHUkUa2Rnd9MxBzB20tsNIu+diUYraPg75QfKlpHZ/kXlsjMVrjaZ9XzDE22qg/O4KeuAGEnXyz/S6ybMBlA4vWOiKhQ7uodBm9fk3iBB+/+W8FOZvWkB2ng3Gks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019440; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=LUe1F0do0669Ic+XOD8QQi+ENeLfrBOCUKG2RnPuAVs=; b=KhFFZJcA1VzjeDD9Wi66TSo0USzpnv5VOeG2RSHe3qNO6NK3J+bfN9eWKBBF603i0Z3GfIcbge9IwCqunvaHn4tGcjItfWkvJ9InYPpLwsYA+4rEeZwdGu54H7eUwe7himWuJuFiSl0ke7EjjguHsP9GbxtMG1ZX3AEDVU54Jlg= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556019440416621.843047086244; Tue, 23 Apr 2019 04:37:20 -0700 (PDT) Received: from localhost ([127.0.0.1]:52144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItjd-0005uG-AB for importer@patchew.org; Tue, 23 Apr 2019 07:37:13 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItda-0001d2-7u for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItdZ-0005W7-5h for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41183 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItdY-0004B6-TN for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 770E01A2434; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4A2E81A243B; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:37 +0200 Message-Id: <1556018982-3715-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 3/8] target/mips: Remove a space before open parenthesis to fix checkpatch errors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jules Irenge Remove a space before open parenthesis to fix errors reported by checkpatch.pl tool "ERROR: space prohibited between function name and open parenthesis" within the file target/mips/cp0_timer.c. Signed-off-by: Jules Irenge Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <20190327145308.17838-1-jbi.octave@gmail.com> --- target/mips/cp0_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index f471639..742f4b2 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -29,7 +29,7 @@ #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ =20 /* XXX: do not use a global */ -uint32_t cpu_mips_get_random (CPUMIPSState *env) +uint32_t cpu_mips_get_random(CPUMIPSState *env) { static uint32_t seed =3D 1; static uint32_t prev_idx =3D 0; @@ -73,7 +73,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env) qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } =20 -uint32_t cpu_mips_get_count (CPUMIPSState *env) +uint32_t cpu_mips_get_count(CPUMIPSState *env) { if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; @@ -91,7 +91,7 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env) } } =20 -void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) +void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) { /* * This gets called from cpu_state_reset(), potentially before timer i= nit. @@ -109,7 +109,7 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t = count) } } =20 -void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value) +void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value) { env->CP0_Compare =3D value; if (!(env->CP0_Cause & (1 << CP0Ca_DC))) @@ -131,7 +131,7 @@ void cpu_mips_stop_count(CPUMIPSState *env) TIMER_PERIOD); } =20 -static void mips_timer_cb (void *opaque) +static void mips_timer_cb(void *opaque) { CPUMIPSState *env; =20 @@ -151,7 +151,7 @@ static void mips_timer_cb (void *opaque) env->CP0_Count--; } =20 -void cpu_mips_clock_init (MIPSCPU *cpu) +void cpu_mips_clock_init(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019323; cv=none; d=zoho.com; s=zohoarc; b=UKDzr2afrjHZvN5TXRhscpex5VHFPEaCVNVA2ZZ2dtJxLVwMpnN8oRHizj+sucIIpPH/7iTHlltIR5ZQTD+CE2PPmosJ2wyQEQi8jEZsEQENOE/9F2+Q46eZmVdXvwjfBKeOWbRh/e+zFt8Svw86MpvlJ/TzYcpnD5TvmEsQ8v4= ARC-Message-Signature: i=1; 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Tue, 23 Apr 2019 07:35:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36429) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItda-0001cx-7P for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItdZ-0005Vv-3l for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41186 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItdY-0004BG-TK for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8175E1A245B; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 549CA1A1E4D; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:38 +0200 Message-Id: <1556018982-3715-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/8] target/mips: Add * to comments and realign them to fix checkpatch warnings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jules Irenge Add * to comments and realign to fix warnings issued by checkpatch.pl tool "WARNING: Block comments use a leading /* on a separate line" within the file target/mips/cp0_timer.c. Signed-off-by: Jules Irenge Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Markovic Message-Id: <20190327181650.23992-1-jbi.octave@gmail.com> --- target/mips/cp0_timer.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 742f4b2..d80b007 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -42,8 +42,10 @@ uint32_t cpu_mips_get_random(CPUMIPSState *env) =20 /* Don't return same value twice, so get another value */ do { - /* Use a simple algorithm of Linear Congruential Generator - * from ISO/IEC 9899 standard. */ + /* + * Use a simple algorithm of Linear Congruential Generator + * from ISO/IEC 9899 standard. + */ seed =3D 1103515245 * seed + 12345; idx =3D (seed >> 16) % nb_rand_tlb + env->CP0_Wired; } while (idx =3D=3D prev_idx); @@ -143,9 +145,11 @@ static void mips_timer_cb(void *opaque) if (env->CP0_Cause & (1 << CP0Ca_DC)) return; =20 - /* ??? This callback should occur when the counter is exactly equal to - the comparator value. Offset the count by one to avoid immediately - retriggering the callback before any virtual time has passed. */ + /* + * ??? This callback should occur when the counter is exactly equal to + * the comparator value. Offset the count by one to avoid immediately + * retriggering the callback before any virtual time has passed. + */ env->CP0_Count++; cpu_mips_timer_expire(env); env->CP0_Count--; --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019206; cv=none; d=zoho.com; s=zohoarc; b=JWiJHYpTMWqSQRtGGtuIiBZMOVrwUGJR5LXWpiF1jIyz21nXXRTyWMjZLP3UIRGIvQBAmbG3f926tmSRVgv7PxeY7Lm50pzqhQUrz4/EtxWssEVA5BAsCe7Fx3ejppvb09BcyM/7Z5fMZ3+hnexTRdjFHkTB8xpmXg0e1dknl4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019206; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=Rp+NsZuOscmRrApZSi4dQJUVx3HO64VIsxkMJ99W9UE=; b=chL7cyD7m63TX2t+LMW1BrvtIwmErI4DD242Y28X5aO5LlkMO8LZdU7Z4ONPfSb+uxir0zdNOqqDfkFTTRXnKNEzyBAfeFnbQ4LSMNg7HqFYQlygTNwfpdShEJbOjcq1ddXX/FqXorX61vlOokj8j7sEaMltYQYWyHGJ07KO+hs= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556019206641190.7443251126665; Tue, 23 Apr 2019 04:33:26 -0700 (PDT) Received: from localhost ([127.0.0.1]:52078 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItfs-0002r2-Kj for importer@patchew.org; Tue, 23 Apr 2019 07:33:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItdb-0001e1-Ti for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:31:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItda-0005YI-FH for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:59 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45019 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItda-0005WP-3V for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8A4DA1A2460; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5FC951A2447; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:39 +0200 Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 5/8] target/mips: Clean up dsp_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/dsp_helper.c | 40 +++++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/target/mips/dsp_helper.c b/target/mips/dsp_helper.c index 739b69d..8c58eeb 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/dsp_helper.c @@ -22,8 +22,10 @@ #include "exec/helper-proto.h" #include "qemu/bitops.h" =20 -/* As the byte ordering doesn't matter, i.e. all columns are treated - identically, these unions can be used directly. */ +/* + * As the byte ordering doesn't matter, i.e. all columns are treated + * identically, these unions can be used directly. + */ typedef union { uint8_t ub[4]; int8_t sb[4]; @@ -1445,9 +1447,15 @@ target_ulong helper_precr_ob_qh(target_ulong rs, tar= get_ulong rt) return temp; } =20 -#define PRECR_QH_PW(name, var) \ -target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt,= \ - uint32_t sa) \ + +/* + * In case sa =3D=3D 0, use rt2, rt0, rs2, rs0. + * In case sa !=3D 0, use rt3, rt1, rs3, rs1. + */ +#define PRECR_QH_PW(name, var) \ +target_ulong helper_precr_##name##_qh_pw(target_ulong rs, \ + target_ulong rt, \ + uint32_t sa) \ { \ uint16_t rs3, rs2, rs1, rs0; \ uint16_t rt3, rt2, rt1, rt0; \ @@ -1456,8 +1464,6 @@ target_ulong helper_precr_##name##_qh_pw(target_ulong= rs, target_ulong rt, \ MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ \ - /* When sa =3D 0, we use rt2, rt0, rs2, rs0; \ - * when sa !=3D 0, we use rt3, rt1, rs3, rs1. */ \ if (sa =3D=3D 0) { \ tempD =3D rt2 << var; \ tempC =3D rt0 << var; \ @@ -1965,7 +1971,8 @@ SHIFT_PH(shra_r, rnd16_rashift); #undef SHIFT_PH =20 /** DSP Multiply Sub-class insns **/ -/* Return value made up by two 16bits value. +/* + * Return value made up by two 16bits value. * FIXME give the macro a better name. */ #define MUL_RETURN32_16_PH(name, func, \ @@ -3274,11 +3281,15 @@ target_ulong helper_dextr_l(target_ulong ac, target= _ulong shift, CPUMIPSState *env) { uint64_t temp[3]; + target_ulong ret; =20 shift =3D shift & 0x3F; =20 mipsdsp_rndrashift_acc(temp, ac, shift, env); - return (temp[1] << 63) | (temp[0] >> 1); + + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } =20 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, @@ -3286,6 +3297,7 @@ target_ulong helper_dextr_r_l(target_ulong ac, target= _ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; =20 shift =3D shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3305,7 +3317,9 @@ target_ulong helper_dextr_r_l(target_ulong ac, target= _ulong shift, set_DSPControl_overflow_flag(1, 23, env); } =20 - return (temp[1] << 63) | (temp[0] >> 1); + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } =20 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, @@ -3313,6 +3327,7 @@ target_ulong helper_dextr_rs_l(target_ulong ac, targe= t_ulong shift, { uint64_t temp[3]; uint32_t temp128; + target_ulong ret; =20 shift =3D shift & 0x3F; mipsdsp_rndrashift_acc(temp, ac, shift, env); @@ -3338,7 +3353,10 @@ target_ulong helper_dextr_rs_l(target_ulong ac, targ= et_ulong shift, } set_DSPControl_overflow_flag(1, 23, env); } - return (temp[1] << 63) | (temp[0] >> 1); + + ret =3D (temp[1] << 63) | (temp[0] >> 1); + + return ret; } #endif =20 --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019557; cv=none; d=zoho.com; s=zohoarc; b=HDKtOIcJGHFpxsIB07W4tAXV28IW8YM3HzkB96Bcu6keNOZ13OLhnNkTNQJe2ICFm2OWPLiQbrNhFcTTa3rGM7uW2jvQMtHQzJAiBmVu8aouWFYKe5b0Chzl2R7fJZQT8qO1F3CAbnefqdHHYleQ7vh6L/wM55oh7dyW6Ymqow4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019557; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; 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Tue, 23 Apr 2019 07:30:59 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45020 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItda-0005WR-3z for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 91D891A1E4D; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 696B71A243C; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:40 +0200 Message-Id: <1556018982-3715-7-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 6/8] target/mips: Clean up lmi_helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/lmi_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/lmi_helper.c b/target/mips/lmi_helper.c index fb1245b..6c645cf 100644 --- a/target/mips/lmi_helper.c +++ b/target/mips/lmi_helper.c @@ -21,9 +21,11 @@ #include "cpu.h" #include "exec/helper-proto.h" =20 -/* If the byte ordering doesn't matter, i.e. all columns are treated - identically, then this union can be used directly. If byte ordering - does matter, we generally ignore dumping to memory. */ +/* + * If the byte ordering doesn't matter, i.e. all columns are treated + * identically, then this union can be used directly. If byte ordering + * does matter, we generally ignore dumping to memory. + */ typedef union { uint8_t ub[8]; int8_t sb[8]; --=20 2.7.4 From nobody Tue May 7 11:17:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1556019563; cv=none; d=zoho.com; s=zohoarc; b=iuzm5QXf4TLycRq+c176amFEikUup/BuggOTtCgcN5j3Ww1+iQnd/F2+EeY61fJ+vgsgYb4kz9DIJWABG98iQ50myYWqA6X5L5yQhY98X1YmIR203Bm+aG0M1ft/FgYh1wF1APKaMXgRmHNBVoJCJ6KXePLnKTMPI88ykJqhQhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556019563; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=xaGTitTwIAWz/usdhFVWjIysvh/vIublpnux4K5ByO8=; b=alT6Lazg3wONPTcnas+HkuI2NQ31fR/615f0mWevKy3ywi8fkki5+9J3EjbN/n86Nf2/ZsvxnJr7qa8RjxEeWR9JFbDLHjvf1jEZVjWIwu1qUYYOXXiyhVmCqQ1fuHhoAYEa8tBVWCdWtUDGbYyjgW+4mMz6xoZh/5mJWZR3xp0= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1556019563345919.3292686804537; Tue, 23 Apr 2019 04:39:23 -0700 (PDT) Received: from localhost ([127.0.0.1]:52160 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItli-0007Jt-Dn for importer@patchew.org; Tue, 23 Apr 2019 07:39:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:36501) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hItdc-0001eY-Kx for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:31:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hItda-0005Ya-II for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:31:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45025 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItda-0005WZ-5E for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9F0B71A243C; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 72C6B1A242D; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:41 +0200 Message-Id: <1556018982-3715-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 7/8] target/mips: Fix some space checkpatch errors in translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove several space-related checkpatch warnings. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 126 +++++++++++++++++++++++++-------------------= ---- 1 file changed, 65 insertions(+), 61 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 797f090..fb4ff0b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2616,7 +2616,7 @@ static const char * const mxuregnames[] =3D { } while (0) =20 /* General purpose registers moves. */ -static inline void gen_load_gpr (TCGv t, int reg) +static inline void gen_load_gpr(TCGv t, int reg) { if (reg =3D=3D 0) tcg_gen_movi_tl(t, 0); @@ -2624,14 +2624,14 @@ static inline void gen_load_gpr (TCGv t, int reg) tcg_gen_mov_tl(t, cpu_gpr[reg]); } =20 -static inline void gen_store_gpr (TCGv t, int reg) +static inline void gen_store_gpr(TCGv t, int reg) { if (reg !=3D 0) tcg_gen_mov_tl(cpu_gpr[reg], t); } =20 /* Moves to/from shadow registers. */ -static inline void gen_load_srsgpr (int from, int to) +static inline void gen_load_srsgpr(int from, int to) { TCGv t0 =3D tcg_temp_new(); =20 @@ -2838,7 +2838,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i= 64 t, int reg) } } =20 -static inline int get_fp_bit (int cc) +static inline int get_fp_bit(int cc) { if (cc) return 24 + cc; @@ -2847,7 +2847,8 @@ static inline int get_fp_bit (int cc) } =20 /* Addresses computation */ -static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0= , TCGv arg1) +static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, + TCGv arg1) { tcg_gen_add_tl(ret, arg0, arg1); =20 @@ -3327,8 +3328,8 @@ OP_LD_ATOMIC(lld,ld64); #endif #undef OP_LD_ATOMIC =20 -static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, - int base, int offset) +static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, + int base, int offset) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); @@ -3340,7 +3341,7 @@ static void gen_base_offset_addr (DisasContext *ctx, = TCGv addr, } } =20 -static target_ulong pc_relative_pc (DisasContext *ctx) +static target_ulong pc_relative_pc(DisasContext *ctx) { target_ulong pc =3D ctx->base.pc_next; =20 @@ -3577,8 +3578,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base= , int16_t offset, } =20 /* Store */ -static void gen_st (DisasContext *ctx, uint32_t opc, int rt, - int base, int offset) +static void gen_st(DisasContext *ctx, uint32_t opc, int rt, + int base, int offset) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -3716,8 +3717,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base= , int16_t offset, } =20 /* Load and store */ -static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, - TCGv t0) +static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, + TCGv t0) { /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -5131,8 +5132,8 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, tcg_temp_free(t1); } =20 -static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) +static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -5195,8 +5196,8 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32= _t opc, tcg_temp_free(t1); } =20 -static void gen_cl (DisasContext *ctx, uint32_t opc, - int rd, int rs) +static void gen_cl(DisasContext *ctx, uint32_t opc, + int rd, int rs) { TCGv t0; =20 @@ -6187,8 +6188,8 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, =20 =20 /* special3 bitfield operations */ -static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, - int rs, int lsb, int msb) +static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, + int rs, int lsb, int msb) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -6258,7 +6259,7 @@ fail: tcg_temp_free(t1); } =20 -static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) +static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) { TCGv t0; =20 @@ -6501,7 +6502,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_= ulong off, int shift) tcg_temp_free_i64(t0); } =20 -static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) +static inline void gen_mfc0_load32(TCGv arg, target_ulong off) { TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 @@ -6510,13 +6511,13 @@ static inline void gen_mfc0_load32 (TCGv arg, targe= t_ulong off) tcg_temp_free_i32(t0); } =20 -static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) +static inline void gen_mfc0_load64(TCGv arg, target_ulong off) { tcg_gen_ld_tl(arg, cpu_env, off); tcg_gen_ext32s_tl(arg, arg); } =20 -static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) +static inline void gen_mtc0_store32(TCGv arg, target_ulong off) { TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 @@ -10076,7 +10077,8 @@ die: generate_exception_end(ctx, EXCP_RI); } =20 -static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, i= nt rt, int rd) +static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rt, int rd) { const char *opn =3D "ldst"; =20 @@ -10632,7 +10634,8 @@ enum r6_f_cmp_op { R6_OPC_CMP_SUNE_D =3D FOP(26, FMT_L), R6_OPC_CMP_SNE_D =3D FOP(27, FMT_L), }; -static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) + +static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) { TCGv t0 =3D tcg_temp_new(); =20 @@ -10713,7 +10716,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t op= c, int rt, int fs) tcg_temp_free(t0); } =20 -static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) +static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) { TCGLabel *l1; TCGCond cond; @@ -10762,7 +10765,8 @@ static inline void gen_movcf_s(DisasContext *ctx, i= nt fs, int fd, int cc, tcg_temp_free_i32(t0); } =20 -static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc,= int tf) +static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, + int tf) { int cond; TCGv_i32 t0 =3D tcg_temp_new_i32(); @@ -10885,8 +10889,8 @@ static void gen_sel_d(DisasContext *ctx, enum fopco= de op1, int fd, int ft, tcg_temp_free_i64(t1); } =20 -static void gen_farith (DisasContext *ctx, enum fopcode op1, - int ft, int fs, int fd, int cc) +static void gen_farith(DisasContext *ctx, enum fopcode op1, + int ft, int fs, int fd, int cc) { uint32_t func =3D ctx->opcode & 0x3f; switch (op1) { @@ -12313,8 +12317,8 @@ static void gen_farith (DisasContext *ctx, enum fop= code op1, } =20 /* Coprocessor 3 (FPU) */ -static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, - int fd, int fs, int base, int index) +static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, + int fd, int fs, int base, int index) { TCGv t0 =3D tcg_temp_new(); =20 @@ -12393,8 +12397,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint3= 2_t opc, tcg_temp_free(t0); } =20 -static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, - int fd, int fr, int fs, int ft) +static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, + int fd, int fr, int fs, int ft) { switch (opc) { case OPC_ALNV_PS: @@ -13156,17 +13160,17 @@ enum { RR_RY_CNVT_SEW =3D 0x6, }; =20 -static int xlat (int r) +static int xlat(int r) { static int map[] =3D { 16, 17, 2, 3, 4, 5, 6, 7 }; =20 return map[r]; } =20 -static void gen_mips16_save (DisasContext *ctx, - int xsregs, int aregs, - int do_ra, int do_s0, int do_s1, - int framesize) +static void gen_mips16_save(DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -13321,10 +13325,10 @@ static void gen_mips16_save (DisasContext *ctx, tcg_temp_free(t2); } =20 -static void gen_mips16_restore (DisasContext *ctx, - int xsregs, int aregs, - int do_ra, int do_s0, int do_s1, - int framesize) +static void gen_mips16_restore(DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) { int astatic; TCGv t0 =3D tcg_temp_new(); @@ -13427,8 +13431,8 @@ static void gen_mips16_restore (DisasContext *ctx, tcg_temp_free(t2); } =20 -static void gen_addiupc (DisasContext *ctx, int rx, int imm, - int is_64_bit, int extended) +static void gen_addiupc(DisasContext *ctx, int rx, int imm, + int is_64_bit, int extended) { TCGv t0; =20 @@ -13458,9 +13462,9 @@ static void gen_cache_operation(DisasContext *ctx, = uint32_t op, int base, } =20 #if defined(TARGET_MIPS64) -static void decode_i64_mips16 (DisasContext *ctx, - int ry, int funct, int16_t offset, - int extended) +static void decode_i64_mips16(DisasContext *ctx, + int ry, int funct, int16_t offset, + int extended) { switch (funct) { case I64_LDSP: @@ -13519,7 +13523,7 @@ static void decode_i64_mips16 (DisasContext *ctx, } #endif =20 -static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ct= x) +static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { int extend =3D cpu_lduw_code(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; @@ -13725,7 +13729,7 @@ static inline bool is_uhi(int sdbbp_code) #endif } =20 -static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) +static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { int rx, ry; int sa; @@ -13948,7 +13952,7 @@ static int decode_mips16_opc (CPUMIPSState *env, Di= sasContext *ctx) case M16_OPC_LWPC: gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case M16_OPC_LWU: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14052,7 +14056,7 @@ static int decode_mips16_opc (CPUMIPSState *env, Di= sasContext *ctx) case RR_SRAV: gen_shift(ctx, OPC_SRAV, ry, rx, ry); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DSRL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14115,7 +14119,7 @@ static int decode_mips16_opc (CPUMIPSState *env, Di= sasContext *ctx) case RR_MFLO: gen_HILO(ctx, OPC_MFLO, 0, rx); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DSRA: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14149,7 +14153,7 @@ static int decode_mips16_opc (CPUMIPSState *env, Di= sasContext *ctx) case RR_DIVU: gen_muldiv(ctx, OPC_DIVU, 0, rx, ry); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DMULT: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14793,7 +14797,7 @@ enum { ADDIUR1SP =3D 0x1 }; =20 -static int mmreg (int r) +static int mmreg(int r) { static const int map[] =3D { 16, 17, 2, 3, 4, 5, 6, 7 }; =20 @@ -14801,7 +14805,7 @@ static int mmreg (int r) } =20 /* Used for 16-bit store instructions. */ -static int mmreg2 (int r) +static int mmreg2(int r) { static const int map[] =3D { 0, 17, 2, 3, 4, 5, 6, 7 }; =20 @@ -14876,8 +14880,8 @@ static void gen_andi16(DisasContext *ctx) gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); } =20 -static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglis= t, - int base, int16_t offset) +static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, + int base, int16_t offset) { TCGv t0, t1; TCGv_i32 t2; @@ -15150,7 +15154,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) } } =20 -static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) +static void gen_ldxs(DisasContext *ctx, int base, int index, int rd) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -15170,8 +15174,8 @@ static void gen_ldxs (DisasContext *ctx, int base, = int index, int rd) tcg_temp_free(t1); } =20 -static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, - int base, int16_t offset) +static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, + int base, int16_t offset) { TCGv t0, t1; =20 @@ -15261,7 +15265,7 @@ static void gen_sync(int stype) tcg_gen_mb(tcg_mo); } =20 -static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, i= nt rs) +static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, in= t rs) { int extension =3D (ctx->opcode >> 6) & 0x3f; int minor =3D (ctx->opcode >> 12) & 0xf; @@ -17225,7 +17229,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) +static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; 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Tue, 23 Apr 2019 07:31:00 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:45024 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hItda-0005WV-4c for qemu-devel@nongnu.org; Tue, 23 Apr 2019 07:30:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id ABFC61A242D; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7F2D61A2454; Tue, 23 Apr 2019 13:29:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 23 Apr 2019 13:29:42 +0200 Message-Id: <1556018982-3715-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1556018982-3715-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 8/8] target/mips: Fix if-else arms checkpatch errors in translate.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Remove if-else-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 112 ++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 70 insertions(+), 42 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index fb4ff0b..35007eb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2618,16 +2618,18 @@ static const char * const mxuregnames[] =3D { /* General purpose registers moves. */ static inline void gen_load_gpr(TCGv t, int reg) { - if (reg =3D=3D 0) + if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); - else + } else { tcg_gen_mov_tl(t, cpu_gpr[reg]); + } } =20 static inline void gen_store_gpr(TCGv t, int reg) { - if (reg !=3D 0) + if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); + } } =20 /* Moves to/from shadow registers. */ @@ -2635,9 +2637,9 @@ static inline void gen_load_srsgpr(int from, int to) { TCGv t0 =3D tcg_temp_new(); =20 - if (from =3D=3D 0) + if (from =3D=3D 0) { tcg_gen_movi_tl(t0, 0); - else { + } else { TCGv_i32 t2 =3D tcg_temp_new_i32(); TCGv_ptr addr =3D tcg_temp_new_ptr(); =20 @@ -2840,10 +2842,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv= _i64 t, int reg) =20 static inline int get_fp_bit(int cc) { - if (cc) + if (cc) { return 24 + cc; - else + } else { return 23; + } } =20 /* Addresses computation */ @@ -2907,14 +2910,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i= 64 arg) =20 static inline void check_cp0_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_err(ctx, EXCP_CpU, 0); + } } =20 static inline void check_cp1_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); + } } =20 /* Verify that the processor is running with COP1X instructions enabled. @@ -2923,8 +2928,9 @@ static inline void check_cp1_enabled(DisasContext *ct= x) =20 static inline void check_cop1x(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* Verify that the processor is running with 64-bit floating-point @@ -2932,8 +2938,9 @@ static inline void check_cop1x(DisasContext *ctx) =20 static inline void check_cp1_64bitmode(DisasContext *ctx) { - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* @@ -2949,8 +2956,9 @@ static inline void check_cp1_64bitmode(DisasContext *= ctx) */ static inline void check_cp1_registers(DisasContext *ctx, int regs) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { generate_exception_end(ctx, EXCP_RI); + } } =20 /* Verify that the processor is running with DSP instructions enabled. @@ -3039,8 +3047,9 @@ static inline void check_ps(DisasContext *ctx) instructions are not enabled. */ static inline void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { generate_exception_end(ctx, EXCP_RI); + } } #endif =20 @@ -3130,8 +3139,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && - !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) - { + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) { generate_exception_end(ctx, EXCP_RI); } } @@ -3881,22 +3889,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32= _t opc, uimm =3D (uint16_t)imm; switch (opc) { case OPC_ANDI: - if (likely(rs !=3D 0)) + if (likely(rs !=3D 0)) { tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], 0); + } break; case OPC_ORI: - if (rs !=3D 0) + if (rs !=3D 0) { tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_XORI: - if (likely(rs !=3D 0)) + if (likely(rs !=3D 0)) { tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_LUI: if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS32R6)) { @@ -6059,8 +6070,9 @@ static void gen_compute_branch (DisasContext *ctx, ui= nt32_t opc, } =20 out: - if (insn_bytes =3D=3D 2) + if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; + } tcg_temp_free(t0); tcg_temp_free(t1); } @@ -6707,8 +6719,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS32); + } =20 switch (reg) { case CP0_REGISTER_00: @@ -7463,8 +7476,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS32); + } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -8209,8 +8223,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS64); + } =20 switch (reg) { case CP0_REGISTER_00: @@ -8919,8 +8934,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) { const char *register_name =3D "invalid"; =20 - if (sel !=3D 0) + if (sel !=3D 0) { check_insn(ctx, ISA_MIPS64); + } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -10161,8 +10177,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_TLBWI: opn =3D "tlbwi"; - if (!env->tlb->helper_tlbwi) + if (!env->tlb->helper_tlbwi) { goto die; + } gen_helper_tlbwi(cpu_env); break; case OPC_TLBINV: @@ -10185,20 +10202,23 @@ static void gen_cp0(CPUMIPSState *env, DisasConte= xt *ctx, uint32_t opc, break; case OPC_TLBWR: opn =3D "tlbwr"; - if (!env->tlb->helper_tlbwr) + if (!env->tlb->helper_tlbwr) { goto die; + } gen_helper_tlbwr(cpu_env); break; case OPC_TLBP: opn =3D "tlbp"; - if (!env->tlb->helper_tlbp) + if (!env->tlb->helper_tlbp) { goto die; + } gen_helper_tlbp(cpu_env); break; case OPC_TLBR: opn =3D "tlbr"; - if (!env->tlb->helper_tlbr) + if (!env->tlb->helper_tlbr) { goto die; + } gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ @@ -10272,8 +10292,9 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, goto out; } =20 - if (cc !=3D 0) + if (cc !=3D 0) { check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + } =20 btarget =3D ctx->base.pc_next + 4 + offset; =20 @@ -10727,10 +10748,11 @@ static void gen_movci(DisasContext *ctx, int rd, = int rs, int cc, int tf) return; } =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 l1 =3D gen_new_label(); t0 =3D tcg_temp_new_i32(); @@ -10752,10 +10774,11 @@ static inline void gen_movcf_s(DisasContext *ctx,= int fs, int fd, int cc, TCGv_i32 t0 =3D tcg_temp_new_i32(); TCGLabel *l1 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10773,10 +10796,11 @@ static inline void gen_movcf_d(DisasContext *ctx,= int fs, int fd, int cc, TCGv_i64 fp0; TCGLabel *l1 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10796,10 +10820,11 @@ static inline void gen_movcf_ps(DisasContext *ctx= , int fs, int fd, TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); =20 - if (tf) + if (tf) { cond =3D TCG_COND_EQ; - else + } else { cond =3D TCG_COND_NE; + } =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -12095,8 +12120,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; =20 - if (ft !=3D 0) + if (ft !=3D 0) { tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); @@ -29837,11 +29863,13 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, f= printf_function cpu_fprintf, env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO= [0], env->hflags, env->btarget, env->bcond); for (i =3D 0; i < 32; i++) { - if ((i & 3) =3D=3D 0) + if ((i & 3) =3D=3D 0) { cpu_fprintf(f, "GPR%02d:", i); + } cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.g= pr[i]); - if ((i & 3) =3D=3D 3) + if ((i & 3) =3D=3D 3) { cpu_fprintf(f, "\n"); + } } =20 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FM= T_lx "\n", --=20 2.7.4