From nobody Fri Apr 19 09:50:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=hygon.cn ARC-Seal: i=1; a=rsa-sha256; t=1555124225; cv=none; d=zoho.com; s=zohoarc; b=S5+0Z7oNv28uf1wY6lqb8ZqNkJ+/aFgy8ror5/TFdeUsDJmBcTrf6WRy66hNihI/L/N7xNb7ecKhX2W+10xkQKHmvObALV75+KhI8qw0WfpuSAEReUtqMcecqPMoIIZRUX3zzVFbWOupl9diNERm3BpVt2usZU2V5poshAG6Ofo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1555124225; h=Content-Type:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To:ARC-Authentication-Results; bh=ja5PnvaPP1vy2SGO/Gl9cMvCWxFEo9kkQ2HYj7pAUDA=; b=Mgr2EJo40re7X8lLEqoo9YqhnSIhPNKxKbVRPzz3FuyQJ4pwwCdzJN9y0XpuXgJl8mGVnblHUJBV/DhAYDk2q/Wa2IPHkmjAUpifHBLIbfF7TRUak2KzUsodTFYkgzk0R5aEGZgkeI7nOsmUxws1spIK2tbDe4dWhxCSSxMVvuU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1555124225051113.78491685155245; Fri, 12 Apr 2019 19:57:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:45776 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hF8qd-0006AW-6y for importer@patchew.org; Fri, 12 Apr 2019 22:56:55 -0400 Received: from eggs.gnu.org ([209.51.188.92]:49621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hF8pj-0005md-0F for qemu-devel@nongnu.org; Fri, 12 Apr 2019 22:56:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hF8pg-0003VX-E6 for qemu-devel@nongnu.org; Fri, 12 Apr 2019 22:55:58 -0400 Received: from [110.188.70.11] (port=6142 helo=spam2.hygon.cn) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hF8pc-0003Qf-MN for qemu-devel@nongnu.org; Fri, 12 Apr 2019 22:55:54 -0400 Received: from MK-DB.hygon.cn ([172.23.18.60]) by spam2.hygon.cn with ESMTP id x3D2t58X079040; Sat, 13 Apr 2019 10:55:05 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from cncheex02.Hygon.cn ([172.23.18.12]) by MK-DB.hygon.cn with ESMTP id x3D2t2U5096218; Sat, 13 Apr 2019 10:55:02 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from pw-vbox.hygon.cn (172.23.18.44) by cncheex02.Hygon.cn (172.23.18.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Sat, 13 Apr 2019 10:55:03 +0800 From: Pu Wen To: Date: Sat, 13 Apr 2019 10:54:40 +0800 Message-ID: <1555124080-27089-1-git-send-email-puwen@hygon.cn> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex02.Hygon.cn (172.23.18.12) To cncheex02.Hygon.cn (172.23.18.12) X-MAIL: spam2.hygon.cn x3D2t58X079040 X-DNSRBL: X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 110.188.70.11 Subject: [Qemu-devel] [PATCH v2] i386: Add new Hygon 'Dhyana' CPU model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, Pu Wen , pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new base CPU model called 'Dhyana' to model processors from Hygon Dhyana(family 18h), which derived from AMD EPYC(family 17h). The following features bits have been removed compare to AMD EPYC: aes, pclmulqdq, sha_ni The Hygon Dhyana support to KVM in Linux is already accepted upstream[1]. So add Hygon Dhyana support to Qemu is necessary to create Hygon's own CPU model. Reference: [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87 Signed-off-by: Pu Wen --- v1->v2: - Remove CPU model 'Dhyana' and rename the CPU model 'Dhyana-IBPB' to 'Dhyana' because Dhyana CPUs already have the IBPB feature. hw/i386/pc.c | 3 +++ target/i386/cpu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 2 ++ 3 files changed, 55 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f2c15bf..551bec9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -128,6 +128,8 @@ GlobalProperty pc_compat_3_1[] =3D { { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, + { "Dhyana" "-" TYPE_X86_CPU, "npt", "off" }, + { "Dhyana" "-" TYPE_X86_CPU, "nrip-save", "off" }, { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, @@ -152,6 +154,7 @@ GlobalProperty pc_compat_2_12[] =3D { { TYPE_X86_CPU, "topoext", "off" }, { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, + { "Dhyana-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, }; const size_t pc_compat_2_12_len =3D G_N_ELEMENTS(pc_compat_2_12); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d6bb57d..d314c5f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2934,6 +2934,56 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .model_id =3D "AMD EPYC Processor (with IBPB)", .cache_info =3D &epyc_cache_info, }, + { + .name =3D "Dhyana", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_HYGON, + .family =3D 24, + .model =3D 0, + .stepping =3D 1, + .features[FEAT_1_EDX] =3D + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUS= H | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, + .features[FEAT_8000_0008_EBX] =3D + CPUID_8000_0008_EBX_IBPB, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AV= X2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED= | + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSH= OPT, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component. + */ + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .features[FEAT_SVM] =3D + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, + .xlevel =3D 0x8000001E, + .model_id =3D "Hygon Dhyana Processor", + .cache_info =3D &epyc_cache_info, + }, }; =20 typedef struct PropValue { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 83fb522..553dbe7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -726,6 +726,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; =20 #define CPUID_VENDOR_VIA "CentaurHauls" =20 +#define CPUID_VENDOR_HYGON "HygonGenuine" + #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ =20 --=20 2.7.4