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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 11 Apr 2019 17:32:25 +0100 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x3BGWOnc45678680 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 11 Apr 2019 16:32:24 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B9644203F; Thu, 11 Apr 2019 16:32:24 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 612A442041; Thu, 11 Apr 2019 16:32:24 +0000 (GMT) Received: from bahia.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.41]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 11 Apr 2019 16:32:24 +0000 (GMT) From: Greg Kurz To: qemu-devel@nongnu.org Date: Thu, 11 Apr 2019 18:32:24 +0200 User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19041116-0028-0000-0000-0000035FD206 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19041116-0029-0000-0000-0000241EF9A1 Message-Id: <155500034416.646888.1307366522340665522.stgit@bahia.lab.toulouse-stg.fr.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-11_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1904110110 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH for-4.0] spapr_pci: Fix broken naming of PCI bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Recent commit 5cf0d326a0fe fixed a regression which was preventing the guest to access the extended config space of a PCIe device. This was done by introducing a new PCI bus subtype for PAPR. The original fix was causing PCI busses to be named "spapr-pci-host-bridge-root-bus.N" instead of "pci.N", which was making upper layers unhappy of course. This got worked around by hardcoding the PCI bus name to "pci.0", but this only works for the default PHB. And we're now hitting: # qemu-system-ppc64 \ -device spapr-pci-host-bridge,index=3D1 \ -device e1000e,bus=3Dpci.0 \ -device e1000e,bus=3Dpci.1 qemu-system-ppc64: -device e1000e,bus=3Dpci.1: Bus 'pci.1' not found David already posted some patches [1] to control PCI extended config space accesses with a new flag in the base PCI bus class instead of subtyping. These patches are a bit more intrusive though, and are targetted for 4.1. When no name is passed to pci_register_bus(), the core device code generates a lowercase name based on the QOM typename. The typename for the base PCI bus class is "PCI", hence the "pci.0", "pci.1" bus names. Rename the type of the PAPR PCI bus to "pci", so that the QOM code can generate proper names. This is a hack but it is enough to fix the regression. And all this will be reworked properly in 4.1. [1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D100486 Fixes: 5cf0d326a0fe Signed-off-by: Greg Kurz --- hw/ppc/spapr_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index f0b6b23afc9b..f62e6833b8c9 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1652,7 +1652,7 @@ static void spapr_phb_root_bus_class_init(ObjectClass= *klass, void *data) pbc->allows_extended_config_space =3D spapr_phb_allows_extended_config= _space; } =20 -#define TYPE_SPAPR_PHB_ROOT_BUS "spapr-pci-host-bridge-root-bus" +#define TYPE_SPAPR_PHB_ROOT_BUS "pci" =20 static const TypeInfo spapr_phb_root_bus_info =3D { .name =3D TYPE_SPAPR_PHB_ROOT_BUS, @@ -1761,7 +1761,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, &sphb->iowindow); =20 - bus =3D pci_register_root_bus(dev, "pci.0", + bus =3D pci_register_root_bus(dev, NULL, pci_spapr_set_irq, pci_spapr_map_irq, sphb, &sphb->memspace, &sphb->iospace, PCI_DEVFN(0, 0), PCI_NUM_PINS,