From nobody Mon Feb 9 17:24:21 2026 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554213038128740.7214738056678; Tue, 2 Apr 2019 06:50:38 -0700 (PDT) Received: from localhost ([127.0.0.1]:35760 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJo0-0005kt-UB for importer@patchew.org; Tue, 02 Apr 2019 09:50:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46052) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJhS-0007Nl-NJ for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBJhR-00072Q-8L for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:38 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:35227 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBJhP-0006zn-OT for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:36 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4109C1A226F; Tue, 2 Apr 2019 15:43:31 +0200 (CEST) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id 0DA051A22B2; Tue, 2 Apr 2019 15:43:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:25 +0200 Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 5/5] target/mips: Refactor and fix INSERT. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the INSERT. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/helper.h | 5 +++- target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++++++--------= ---- target/mips/translate.c | 19 +++++++++++++- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 8b6703c..82f6a40 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -875,7 +875,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_2(msa_cfcmsa, tl, env, i32) @@ -942,6 +941,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index d5bf4dc..d5c3842 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1323,28 +1323,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 -void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, +void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd, uint32_t rs_num, uint32_t n) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + pwd->b[n] =3D (int8_t)rs; +} =20 - switch (df) { - case DF_BYTE: - pwd->b[n] =3D (int8_t)rs; - break; - case DF_HALF: - pwd->h[n] =3D (int16_t)rs; - break; - case DF_WORD: - pwd->w[n] =3D (int32_t)rs; - break; - case DF_DOUBLE: - pwd->d[n] =3D (int64_t)rs; - break; - default: - assert(0); +void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } +#endif + pwd->h[n] =3D (int16_t)rs; +} + +void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + pwd->w[n] =3D (int32_t)rs; +} + +void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 2; + pwd->d[n] =3D (int64_t)rs; } =20 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index 72ed0a8..64587c4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29446,7 +29446,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, } break; case OPC_INSERT_df: - gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } break; } break; --=20 2.7.4