From nobody Fri May 3 01:30:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554212748043675.573148133216; Tue, 2 Apr 2019 06:45:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:34542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJjL-00006C-V6 for importer@patchew.org; Tue, 02 Apr 2019 09:45:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJhR-0007Mj-8E for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBJhO-0006z7-Nt for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:33643 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBJhO-0006wd-6z for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1180C1A229D; Tue, 2 Apr 2019 15:43:31 +0200 (CEST) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id D6FF41A2262; Tue, 2 Apr 2019 15:43:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:21 +0200 Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 1/5] target/mips: Fix MSA instructions LD. on big endian host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Fix the case when the host is a big endian machine, and change the approach toward LD. instruction helpers. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 188 ++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 168 insertions(+), 20 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5..45be406 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4371,31 +4371,179 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->ac= tive_fpu.fp_status) #define MEMOP_IDX(DF) #endif =20 -#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \ -void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - wr_t wx; \ - int i; \ - MEMOP_IDX(DF) \ - for (i =3D 0; i < DF_ELEMENTS(DF); i++) { \ - wx.TYPE[i] =3D LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \ - } \ - memcpy(pwd, &wx, sizeof(wr_t)); \ +void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); +#else + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); +#else + pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); +#endif +#endif } =20 +void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) #if !defined(CONFIG_USER_ONLY) -MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC()) -MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC()) -MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC()) -MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC()) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); +#else + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); #else -MSA_LD_DF(DF_BYTE, b, cpu_ldub_data) -MSA_LD_DF(DF_HALF, h, cpu_lduw_data) -MSA_LD_DF(DF_WORD, w, cpu_ldl_data) -MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data) + pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); #endif +#endif +} + +void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); +#else + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); +#else + pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); +#endif +#endif +} + +void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); + pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); +#else + pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); + pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); +#endif +} =20 #define MSA_PAGESPAN(x) \ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >=3D TARGET_PAGE_SI= ZE) --=20 2.7.4 From nobody Fri May 3 01:30:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554212923895997.911037195446; Tue, 2 Apr 2019 06:48:43 -0700 (PDT) Received: from localhost ([127.0.0.1]:35265 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJmK-0003Nr-V8 for importer@patchew.org; Tue, 02 Apr 2019 09:48:40 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46020) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJhR-0007Ml-8h for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBJhO-0006zO-O3 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:33687 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBJhO-0006wg-50 for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 232941A22AF; Tue, 2 Apr 2019 15:43:31 +0200 (CEST) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id E3DD01A226F; Tue, 2 Apr 2019 15:43:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:22 +0200 Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 2/5] target/mips: Fix MSA instructions ST. on big endian host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Fix the case when the host is a big endian machine, and change the approach toward ST. instruction helpers. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/op_helper.c | 188 ++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 168 insertions(+), 20 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 45be406..d94909a 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4565,31 +4565,179 @@ static inline void ensure_writable_pages(CPUMIPSSt= ate *env, #endif } =20 -#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \ -void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); \ - int mmu_idx =3D cpu_mmu_index(env, false); \ - int i; \ - MEMOP_IDX(DF) \ - ensure_writable_pages(env, addr, mmu_idx, GETPC()); \ - for (i =3D 0; i < DF_ELEMENTS(DF); i++) { \ - ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ - } \ +void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#else + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); +#else + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); +#endif +#endif +} + +void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); +#else + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); +#else + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); +#endif +#endif } =20 +void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) #if !defined(CONFIG_USER_ONLY) -MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC()) -MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC()) -MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC()) -MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC()) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]); + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]); #else -MSA_ST_DF(DF_BYTE, b, cpu_stb_data) -MSA_ST_DF(DF_HALF, h, cpu_stw_data) -MSA_ST_DF(DF_WORD, w, cpu_stl_data) -MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data) + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]); + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]); #endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); +#else + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); +#endif +#endif +} + +void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); + helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); +#else + cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); + cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); +#endif +} =20 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { --=20 2.7.4 From nobody Fri May 3 01:30:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554212748098960.284762983277; Tue, 2 Apr 2019 06:45:48 -0700 (PDT) Received: from localhost ([127.0.0.1]:34536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJjM-00005b-90 for importer@patchew.org; Tue, 02 Apr 2019 09:45:36 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hBJhR-0007Mk-8g for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hBJhO-0006zE-NX for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:36 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:33711 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hBJhO-0006wh-2R for qemu-devel@nongnu.org; Tue, 02 Apr 2019 09:43:34 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 2DCB01A2262; Tue, 2 Apr 2019 15:43:31 +0200 (CEST) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id EE9321A22A4; Tue, 2 Apr 2019 15:43:30 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:23 +0200 Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 3/5] target/mips: Refactor and fix COPY_S. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the COPY_S. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/helper.h | 7 +++++- target/mips/msa_helper.c | 62 +++++++++++++++++++++++++++++++++-----------= ---- target/mips/translate.c | 19 ++++++++++++++- 3 files changed, 67 insertions(+), 21 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 2f23b0d..4e49618 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -874,7 +874,7 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) =20 DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32) + DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) @@ -936,6 +936,11 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index a500c59..5a06579 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1232,29 +1232,53 @@ void helper_msa_splati_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, msa_splat_df(df, pwd, pws, n); } =20 -void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %=3D DF_ELEMENTS(df); + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + env->active_tc.gpr[rd] =3D (int8_t)env->active_fpu.fpr[ws].wr.b[n]; +} =20 - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] =3D (int8_t)env->active_fpu.fpr[ws].wr.b[n]; - break; - case DF_HALF: - env->active_tc.gpr[rd] =3D (int16_t)env->active_fpu.fpr[ws].wr.h[n= ]; - break; - case DF_WORD: - env->active_tc.gpr[rd] =3D (int32_t)env->active_fpu.fpr[ws].wr.w[n= ]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n= ]; - break; +void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } #endif - default: - assert(0); + env->active_tc.gpr[rd] =3D (int16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + env->active_tc.gpr[rd] =3D (int32_t)env->active_fpu.fpr[ws].wr.w[n]; +} + +void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 2; + env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } =20 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, diff --git a/target/mips/translate.c b/target/mips/translate.c index 189bbc4..f2ea378 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29401,7 +29401,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: if (likely(wd !=3D 0)) { - gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_COPY_U_df: --=20 2.7.4 From nobody Fri May 3 01:30:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554212748092324.63870052412415; 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Tue, 2 Apr 2019 15:43:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:24 +0200 Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 4/5] target/mips: Refactor and fix COPY_U. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the COPY_U. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/helper.h | 4 +++- target/mips/msa_helper.c | 55 +++++++++++++++++++++++++++++++-------------= ---- target/mips/translate.c | 21 +++++++++++++++++- 3 files changed, 59 insertions(+), 21 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 4e49618..8b6703c 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -875,7 +875,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) @@ -940,6 +939,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 5a06579..d5bf4dc 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1281,29 +1281,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } =20 -void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %=3D DF_ELEMENTS(df); + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + env->active_tc.gpr[rd] =3D (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; +} =20 - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] =3D (uint8_t)env->active_fpu.fpr[ws].wr.b[n= ]; - break; - case DF_HALF: - env->active_tc.gpr[rd] =3D (uint16_t)env->active_fpu.fpr[ws].wr.h[= n]; - break; - case DF_WORD: - env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[= n]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] =3D (uint64_t)env->active_fpu.fpr[ws].wr.d[= n]; - break; +void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } #endif - default: - assert(0); + env->active_tc.gpr[rd] =3D (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index f2ea378..72ed0a8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29397,6 +29397,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, generate_exception_end(ctx, EXCP_RI); break; } + if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && + (df =3D=3D DF_WORD)) { + generate_exception_end(ctx, EXCP_RI); + break; + } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -29423,7 +29428,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, break; case OPC_COPY_U_df: if (likely(wd !=3D 0)) { - gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_INSERT_df: --=20 2.7.4 From nobody Fri May 3 01:30:11 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554213038128740.7214738056678; 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Tue, 2 Apr 2019 15:43:31 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 2 Apr 2019 15:43:25 +0200 Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1554212605-16457-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 5/5] target/mips: Refactor and fix INSERT. instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic The old version of the helper for the INSERT. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/helper.h | 5 +++- target/mips/msa_helper.c | 65 ++++++++++++++++++++++++++++++++++++--------= ---- target/mips/translate.c | 19 +++++++++++++- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index 8b6703c..82f6a40 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -875,7 +875,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i= 32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) =20 -DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) DEF_HELPER_2(msa_cfcmsa, tl, env, i32) @@ -942,6 +941,10 @@ DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) =20 DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index d5bf4dc..d5c3842 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1323,28 +1323,61 @@ void helper_msa_copy_u_w(CPUMIPSState *env, uint32_= t rd, env->active_tc.gpr[rd] =3D (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } =20 -void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, +void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd, uint32_t rs_num, uint32_t n) { wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n =3D 8 - n - 1; + } else { + n =3D 24 - n - 1; + } +#endif + pwd->b[n] =3D (int8_t)rs; +} =20 - switch (df) { - case DF_BYTE: - pwd->b[n] =3D (int8_t)rs; - break; - case DF_HALF: - pwd->h[n] =3D (int16_t)rs; - break; - case DF_WORD: - pwd->w[n] =3D (int32_t)rs; - break; - case DF_DOUBLE: - pwd->d[n] =3D (int64_t)rs; - break; - default: - assert(0); +void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n =3D 4 - n - 1; + } else { + n =3D 12 - n - 1; + } +#endif + pwd->h[n] =3D (int16_t)rs; +} + +void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n =3D 2 - n - 1; + } else { + n =3D 6 - n - 1; } +#endif + pwd->w[n] =3D (int32_t)rs; +} + +void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd, + uint32_t rs_num, uint32_t n) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + target_ulong rs =3D env->active_tc.gpr[rs_num]; + n %=3D 2; + pwd->d[n] =3D (int64_t)rs; } =20 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/target/mips/translate.c b/target/mips/translate.c index 72ed0a8..64587c4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29446,7 +29446,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disa= sContext *ctx, uint32_t df, } break; case OPC_INSERT_df: - gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } break; } break; --=20 2.7.4