From nobody Sat Feb 7 05:56:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553278101433739.3987222176395; Fri, 22 Mar 2019 11:08:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:32872 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OaX-0007UF-Cx for importer@patchew.org; Fri, 22 Mar 2019 14:08:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34559) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OWN-0003VB-DT for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:04:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h7OWI-0000EK-F1 for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:03:56 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47982) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h7OWH-00009Z-1K for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:03:54 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2MHxETl072045 for ; Fri, 22 Mar 2019 14:03:48 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rd16cjpg1-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 22 Mar 2019 14:03:46 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 22 Mar 2019 18:03:32 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2MI3fm752953132 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 22 Mar 2019 18:03:41 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0962FA4060; Fri, 22 Mar 2019 18:03:41 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9458A4065; Fri, 22 Mar 2019 18:03:40 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.131]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 22 Mar 2019 18:03:40 +0000 (GMT) From: Greg Kurz To: qemu-devel@nongnu.org Date: Fri, 22 Mar 2019 19:03:40 +0100 In-Reply-To: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> References: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19032218-0016-0000-0000-000002660B3E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032218-0017-0000-0000-000032C13202 Message-Id: <155327782047.1283071.10234727692461848972.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-22_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=810 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903220130 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH for-4.0 1/3] target/ppc: Fix TCG temporary leaks in gen_bcond() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Richard Henderson , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Greg Kurz Tested-by: Suraj Jitindar Singh --- target/ppc/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 98b37cebc2f5..aaafa3a715d8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3749,6 +3749,8 @@ static void gen_bcond(DisasContext *ctx, int type) TCGv temp =3D tcg_temp_new(); if (unlikely(type =3D=3D BCOND_CTR)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + tcg_temp_free(temp); + tcg_temp_free(target); return; } tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); From nobody Sat Feb 7 05:56:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553277993411172.6894369761353; Fri, 22 Mar 2019 11:06:33 -0700 (PDT) Received: from localhost ([127.0.0.1]:32837 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OYk-0005s6-8l for importer@patchew.org; Fri, 22 Mar 2019 14:06:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OWP-0003Xi-Dv for qemu-devel@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 22 Mar 2019 18:03:37 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2MI3k6c32702642 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 22 Mar 2019 18:03:46 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B8D352052; Fri, 22 Mar 2019 18:03:46 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.131]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 562295204E; Fri, 22 Mar 2019 18:03:46 +0000 (GMT) From: Greg Kurz To: qemu-devel@nongnu.org Date: Fri, 22 Mar 2019 19:03:46 +0100 In-Reply-To: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> References: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19032218-0020-0000-0000-000003267ADF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032218-0021-0000-0000-00002178A863 Message-Id: <155327782604.1283071.10640596307206921951.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-22_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=655 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903220130 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH for-4.0 2/3] target/ppc: Enable "decrement and test CTR" version of bcctr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Richard Henderson , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Even if all ISAs up to v3 indeed mention: If the "decrement and test CTR" option is specified (BO2=3D0), the instruction form is invalid. The UMs of all existing 64-bit server class processors say: If BO[2] =3D 0, the contents of CTR (before any update) are used as the target address and for the test of the contents of CTR to resolve the branch. The contents of the CTR are then decremented and written back to the CTR. The linux kernel has spectre v2 mitigation code that relies on a BO[2] =3D 0 variant of bcctr, which is now activated by default on spapr, even with TCG. This causes linux guests to panic with the default machine type under TCG. Since any CPU model can provide its own behaviour for invalid forms, we could possibly introduce a new instruction flag to handle this. In practice, since the behaviour is shared by all 64-bit server processors starting with 970 up to POWER9, let's reuse the PPC_SEGMENT_64B flag. Caveat: this may have to be fixed later if POWER10 introduces a different behaviour. The existing behaviour of throwing a program interrupt is kept for all other CPU models. Signed-off-by: Greg Kurz Tested-by: Suraj Jitindar Singh --- target/ppc/translate.c | 52 ++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index aaafa3a715d8..d3aaa6482c6a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3747,22 +3747,44 @@ static void gen_bcond(DisasContext *ctx, int type) if ((bo & 0x4) =3D=3D 0) { /* Decrement and test CTR */ TCGv temp =3D tcg_temp_new(); - if (unlikely(type =3D=3D BCOND_CTR)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - tcg_temp_free(temp); - tcg_temp_free(target); - return; - } - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + + if (type =3D=3D BCOND_CTR) { + /* + * All ISAs up to v3 describe this form of bcctr as invalid but + * some processors, ie. 64-bit server processors compliant with + * arch 2.x, do implement a "test and decrement" logic instead, + * as described in their respective UMs. + */ + if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + tcg_temp_free(temp); + tcg_temp_free(target); + return; + } + + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } } tcg_temp_free(temp); } From nobody Sat Feb 7 05:56:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553278231829702.2621628646509; Fri, 22 Mar 2019 11:10:31 -0700 (PDT) Received: from localhost ([127.0.0.1]:32894 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OcY-0000wh-JB for importer@patchew.org; Fri, 22 Mar 2019 14:10:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:34722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h7OWh-0003sO-2t for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:04:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h7OWY-0000Q2-PV for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:04:13 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:55088 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h7OWV-0000GI-1n for qemu-devel@nongnu.org; Fri, 22 Mar 2019 14:04:08 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2MHxCKu022262 for ; Fri, 22 Mar 2019 14:03:58 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2rd2vuwg79-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 22 Mar 2019 14:03:57 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 22 Mar 2019 18:03:44 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2MI3qT760686538 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 22 Mar 2019 18:03:52 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 26E884C046; Fri, 22 Mar 2019 18:03:52 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E38C84C040; Fri, 22 Mar 2019 18:03:51 +0000 (GMT) Received: from bahia.lan (unknown [9.145.42.131]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 22 Mar 2019 18:03:51 +0000 (GMT) From: Greg Kurz To: qemu-devel@nongnu.org Date: Fri, 22 Mar 2019 19:03:51 +0100 In-Reply-To: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> References: <155327781490.1283071.6082995362788639045.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19032218-4275-0000-0000-0000031E2A0E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032218-4276-0000-0000-0000382CB6E8 Message-Id: <155327783157.1283071.3747129891004927299.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-22_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=994 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903220130 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH for-4.0 3/3] target/ppc: Consolidate 64-bit server processor detection in a helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Richard Henderson , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" We use PPC_SEGMENT_64B in various places to guard code that is specific to 64-bit server processors compliant with arch 2.x. Consolidate the logic in a helper macro with an explicit name. Signed-off-by: Greg Kurz Tested-by: Suraj Jitindar Singh --- hw/ppc/ppc.c | 2 +- target/ppc/cpu.h | 6 ++++++ target/ppc/helper_regs.h | 2 +- target/ppc/translate.c | 10 ++++------ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 49d57469fb34..ad20584f268d 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint3= 2_t freq) tb_env =3D g_malloc0(sizeof(ppc_tb_t)); env->tb_env =3D tb_env; tb_env->flags =3D PPC_DECR_UNDERFLOW_TRIGGERED; - if (env->insns_flags & PPC_SEGMENT_64B) { + if (is_book3s_arch2x(env)) { /* All Book3S 64bit CPUs implement level based DEC logic */ tb_env->flags |=3D PPC_DECR_UNDERFLOW_LEVEL; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fc12b4688e8c..070717758452 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2409,6 +2409,12 @@ enum { target_ulong cpu_read_xer(CPUPPCState *env); void cpu_write_xer(CPUPPCState *env, target_ulong xer); =20 +/* + * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer, + * have PPC_SEGMENT_64B. + */ +#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) + static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *f= lags) { diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index a2205e1044c9..c863abc0bfc3 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, * - 64-bit embedded implementations do not need any operation to be * performed when PR is set. */ - if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) { + if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { value |=3D (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); } #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d3aaa6482c6a..576210d901ad 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int type) * arch 2.x, do implement a "test and decrement" logic instead, * as described in their respective UMs. */ - if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) { + if (unlikely(!is_book3s_arch2x(ctx))) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); tcg_temp_free(temp); tcg_temp_free(target); @@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx) /* This instruction doesn't exist anymore on 64-bit server * processors compliant with arch 2.x */ - if (ctx->insns_flags & PPC_SEGMENT_64B) { + if (is_book3s_arch2x(ctx)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } @@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx) GEN_PRIV; #else CHK_HV; - /* 64-bit server processors compliant with arch 2.x */ - if (ctx->insns_flags & PPC_SEGMENT_64B) { + if (is_book3s_arch2x(ctx)) { gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); } else { gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); @@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx) GEN_PRIV; #else CHK_HV; - /* 64-bit server processors compliant with arch 2.x */ - if (ctx->insns_flags & PPC_SEGMENT_64B) { + if (is_book3s_arch2x(ctx)) { gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); } else { gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);