From nobody Fri Apr 26 15:23:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552644604061768.8260006767321; Fri, 15 Mar 2019 03:10:04 -0700 (PDT) Received: from localhost ([127.0.0.1]:52913 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4jmp-0002c4-U0 for importer@patchew.org; Fri, 15 Mar 2019 06:10:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:37982) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4jkz-0001Rw-V2 for qemu-devel@nongnu.org; Fri, 15 Mar 2019 06:08:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4jkx-0000nh-AN for qemu-devel@nongnu.org; Fri, 15 Mar 2019 06:08:05 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:43643) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h4jkw-0000mp-MI for qemu-devel@nongnu.org; Fri, 15 Mar 2019 06:08:03 -0400 Received: by mail-pg1-x536.google.com with SMTP id l11so6110546pgq.10 for ; Fri, 15 Mar 2019 03:08:02 -0700 (PDT) Received: from localhost.localdomain ([104.237.86.214]) by smtp.gmail.com with ESMTPSA id b7sm4882128pfi.36.2019.03.15.03.07.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Mar 2019 03:08:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dlFv4qIVZhs5Ia6Gi4pgZMscUXtZDFECZFAvEbrV6jU=; b=stcyfdQWjsPL71cxZDdfHabH3vTeciZSEAiCj3ZqV74YVCvAb9ZIw+ZS5GJMte+UHh aKFc8x/udYXOK4SrppkzD0jXm6fmGoTrxdL9WnRGS42aQxwkTIP/XQ1qKR6jSkGt3fFx 5bB66iDFQVZL9kwZpi8upYqt6GNxWGPkFaOgM1yOPTMOqADS1biJrx6Hynm28ZsFBgof PnjHhSNywYXfMbSzf/XLuI4nncWSKfsKCrdE9rghxrvmRn4zxJhi1joy7EbhCWgyywPW 5cCiU0vPwUyxlypq2OTjEtVrwyUabCMQ8xEl6L5v8JRHXxTxkyz01ApoGT0o/Ze6j7nR sKHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dlFv4qIVZhs5Ia6Gi4pgZMscUXtZDFECZFAvEbrV6jU=; b=Xt367HvZKVlem0BIKxxid6IzWgWZezclGQhi8m5BNwzD3P5T85PshKQOhKQBfCvNzv wWSYdNsy2eGJ/7rQPco0CDvNfbj8nOs/T11eju07/GVtT9bGyYqq/kS3foMTNPCTjul1 FtKmcVUJDXDik5kUWCh7TPm35AU5BMSZ1FjxyQu7ZI35lZcFlbbI+FOJpTUs8UwJQheD ry80n8msdPTtbztokwqpRIqYwE51fSmKKISStgzNU1utv7jxNbnnc55sRgX7UD6hUANV wNUa/kyZdj6RpNeQ9YPagiowKEOxA8kgrY6avI3eGC9vjrM8YpfIp4kUMeYARnK/gwIv 4bdg== X-Gm-Message-State: APjAAAWlMCc1/7q/a+FhvHJ3Tqta4+7h8F8j4UYA1Y/xufb3JYdfWx3S w3vpg9qRGq3WhvO1L6WinF2ytA== X-Google-Smtp-Source: APXvYqylRJFNN2qGehpjDsFm6d0zgjk75RdRSvopN4GU5dRdOFVKYvwV8WLt8hJanTqElb+b2SlGcQ== X-Received: by 2002:a62:e40d:: with SMTP id r13mr3114098pfh.11.1552644481095; Fri, 15 Mar 2019 03:08:01 -0700 (PDT) From: Hongbo Zhang To: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 15 Mar 2019 18:07:45 +0800 Message-Id: <1552644466-24625-2-git-send-email-hongbo.zhang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552644466-24625-1-git-send-email-hongbo.zhang@linaro.org> References: <1552644466-24625-1-git-send-email-hongbo.zhang@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::536 Subject: [Qemu-devel] [PATCH v6 1/2] hw/arm: Add arm SBSA reference machine, skeleton part X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hongbo Zhang , radoslaw.biernacki@linaro.org, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the Aarch64, there is one machine 'virt', it is primarily meant to run on KVM and execute virtualization workloads, but we need an environment as faithful as possible to physical hardware, for supporting firmware and OS development for pysical Aarch64 machines. This patch introduces new machine type 'sbsa-ref' with main features: - Based on 'virt' machine type. - A new memory map. - CPU type cortex-a57. - EL2 and EL3 are enabled. - GIC version 3. - System bus AHCI controller. - System bus EHCI controller. - CDROM and hard disc on AHCI bus. - E1000E ethernet card on PCIE bus. - VGA display adaptor on PCIE bus. - No virtio deivces. - No fw_cfg device. - No ACPI table supplied. - Only minimal device tree nodes. Arm Trusted Firmware and UEFI porting to this are done accordingly, and it should supply ACPI tables to load OS, the minimal device tree nodes supplied from this platform are only to pass the dynamic info reflecting command line input to firmware, not for loading OS. To make the review easier, this task is split into two patches, the fundamental sceleton part and the peripheral devices part, this patch is the first part. Signed-off-by: Hongbo Zhang --- default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 3 + hw/arm/Makefile.objs | 1 + hw/arm/sbsa-ref.c | 303 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 308 insertions(+) create mode 100644 hw/arm/sbsa-ref.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 2a7efc1..4fbb6ac 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -144,6 +144,7 @@ CONFIG_IOH3420=3Dy CONFIG_I82801B11=3Dy CONFIG_ACPI=3Dy CONFIG_ARM_VIRT=3Dy +CONFIG_SBSA_REF=3Dy CONFIG_SMBIOS=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_SMBUS_EEPROM=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d298fbd..6654914 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -38,6 +38,9 @@ config PXA2XX config REALVIEW bool =20 +config SBSA_REF + bool + config STELLARIS bool =20 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fa57c7c..fa812ec 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -12,6 +12,7 @@ obj-$(CONFIG_NSERIES) +=3D nseries.o obj-$(CONFIG_OMAP) +=3D omap_sx1.o palm.o obj-$(CONFIG_PXA2XX) +=3D gumstix.o spitz.o tosa.o z2.o obj-$(CONFIG_REALVIEW) +=3D realview.o +obj-$(CONFIG_SBSA_REF) +=3D sbsa-ref.o obj-$(CONFIG_STELLARIS) +=3D stellaris.o obj-$(CONFIG_STRONGARM) +=3D collie.o obj-$(CONFIG_VERSATILE) +=3D vexpress.o versatilepb.o diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c new file mode 100644 index 0000000..b6d31f2 --- /dev/null +++ b/hw/arm/sbsa-ref.c @@ -0,0 +1,303 @@ +/* + * ARM SBSA Reference Platform emulation + * + * Copyright (c) 2018 Linaro Limited + * Written by Hongbo Zhang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/units.h" +#include "sysemu/numa.h" +#include "sysemu/sysemu.h" +#include "exec/address-spaces.h" +#include "exec/hwaddr.h" +#include "kvm_arm.h" +#include "hw/arm/arm.h" +#include "hw/boards.h" +#include "hw/intc/arm_gicv3_common.h" + +#define RAMLIMIT_GB 8192 +#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) + +enum { + SBSA_FLASH, + SBSA_MEM, + SBSA_CPUPERIPHS, + SBSA_GIC_DIST, + SBSA_GIC_REDIST, + SBSA_SMMU, + SBSA_UART, + SBSA_RTC, + SBSA_PCIE, + SBSA_PCIE_MMIO, + SBSA_PCIE_MMIO_HIGH, + SBSA_PCIE_PIO, + SBSA_PCIE_ECAM, + SBSA_GPIO, + SBSA_SECURE_UART, + SBSA_SECURE_MEM, + SBSA_AHCI, + SBSA_EHCI, +}; + +typedef struct MemMapEntry { + hwaddr base; + hwaddr size; +} MemMapEntry; + +typedef struct { + MachineState parent; + struct arm_boot_info bootinfo; + const MemMapEntry *memmap; + const int *irqmap; + int smp_cpus; + void *fdt; + int fdt_size; + int psci_conduit; +} SBSAMachineState; + +#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") +#define SBSA_MACHINE(obj) \ + OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE) + +static const MemMapEntry sbsa_ref_memmap[] =3D { + /* 512M boot ROM */ + [SBSA_FLASH] =3D { 0, 0x20000000 }, + /* 512M secure memory */ + [SBSA_SECURE_MEM] =3D { 0x20000000, 0x20000000 }, + /* Space reserved for CPU peripheral devices */ + [SBSA_CPUPERIPHS] =3D { 0x40000000, 0x00040000 }, + [SBSA_GIC_DIST] =3D { 0x40060000, 0x00010000 }, + [SBSA_GIC_REDIST] =3D { 0x40080000, 0x04000000 }, + [SBSA_UART] =3D { 0x60000000, 0x00001000 }, + [SBSA_RTC] =3D { 0x60010000, 0x00001000 }, + [SBSA_GPIO] =3D { 0x60020000, 0x00001000 }, + [SBSA_SECURE_UART] =3D { 0x60030000, 0x00001000 }, + [SBSA_SMMU] =3D { 0x60040000, 0x00020000 }, + /* Space here reserved for more SMMUs */ + [SBSA_AHCI] =3D { 0x60100000, 0x00010000 }, + [SBSA_EHCI] =3D { 0x60110000, 0x00010000 }, + /* Space here reserved for other devices */ + [SBSA_PCIE_PIO] =3D { 0x7fff0000, 0x00010000 }, + /* 256M PCIE ECAM space */ + [SBSA_PCIE_ECAM] =3D { 0x80000000, 0x10000000 }, + /* 32-bit address PCIE MMIO space */ + [SBSA_PCIE_MMIO] =3D { 0x90000000, 0x70000000 }, + /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ + [SBSA_PCIE_MMIO_HIGH] =3D { 0x100000000ULL, 0xFF00000000ULL }, + [SBSA_MEM] =3D { 0x10000000000ULL, RAMLIMIT_BYTES }, +}; + +static const int sbsa_ref_irqmap[] =3D { + [SBSA_UART] =3D 1, + [SBSA_RTC] =3D 2, + [SBSA_PCIE] =3D 3, /* ... to 6 */ + [SBSA_GPIO] =3D 7, + [SBSA_SECURE_UART] =3D 8, + [SBSA_AHCI] =3D 9, + [SBSA_EHCI] =3D 10, +}; + +static void sbsa_ref_init(MachineState *machine) +{ + SBSAMachineState *vms =3D SBSA_MACHINE(machine); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *secure_sysmem =3D NULL; + MemoryRegion *ram =3D g_new(MemoryRegion, 1); + bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); + const CPUArchIdList *possible_cpus; + int n, sbsa_max_cpus; + + if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { + error_report("sbsa-ref: CPU type other than the built-in " + "cortex-a57 not supported"); + exit(1); + } + + if (kvm_enabled()) { + error_report("sbsa-ref: KVM is not supported at this machine"); + exit(1); + } + + if (machine->kernel_filename && firmware_loaded) { + error_report("sbsa-ref: No fw_cfg device on this machine, " + "so -kernel option is not supported when firmware loa= ded, " + "please load OS from hard disk instead"); + exit(1); + } + + /* + * This machine has EL3 enabled, external firmware should supply PSCI + * implementation, so the QEMU's internal PSCI is disabled. + */ + vms->psci_conduit =3D QEMU_PSCI_CONDUIT_DISABLED; + + sbsa_max_cpus =3D vms->memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZ= E; + + if (max_cpus > sbsa_max_cpus) { + error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " + "supported by machine 'sbsa-ref' (%d)", + max_cpus, sbsa_max_cpus); + exit(1); + } + + vms->smp_cpus =3D smp_cpus; + + if (machine->ram_size > vms->memmap[SBSA_MEM].size) { + error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT= _GB); + exit(1); + } + + secure_sysmem =3D g_new(MemoryRegion, 1); + memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", + UINT64_MAX); + memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); + + possible_cpus =3D mc->possible_cpu_arch_ids(machine); + for (n =3D 0; n < possible_cpus->len; n++) { + Object *cpuobj; + CPUState *cs; + + if (n >=3D smp_cpus) { + break; + } + + cpuobj =3D object_new(possible_cpus->cpus[n].type); + object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, + "mp-affinity", NULL); + + cs =3D CPU(cpuobj); + cs->cpu_index =3D n; + + numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuo= bj), + &error_fatal); + + if (object_property_find(cpuobj, "reset-cbar", NULL)) { + object_property_set_int(cpuobj, vms->memmap[SBSA_CPUPERIPHS].b= ase, + "reset-cbar", &error_abort); + } + + object_property_set_link(cpuobj, OBJECT(sysmem), "memory", + &error_abort); + + object_property_set_link(cpuobj, OBJECT(secure_sysmem), + "secure-memory", &error_abort); + + object_property_set_bool(cpuobj, true, "realized", &error_fatal); + object_unref(cpuobj); + } + + memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", + machine->ram_size); + memory_region_add_subregion(sysmem, vms->memmap[SBSA_MEM].base, ram); + + vms->bootinfo.ram_size =3D machine->ram_size; + vms->bootinfo.kernel_filename =3D machine->kernel_filename; + vms->bootinfo.nb_cpus =3D smp_cpus; + vms->bootinfo.board_id =3D -1; + vms->bootinfo.loader_start =3D vms->memmap[SBSA_MEM].base; + vms->bootinfo.firmware_loaded =3D firmware_loaded; + arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); +} + +static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *vms, int idx) +{ + uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; + return arm_cpu_mp_affinity(idx, clustersz); +} + +static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *m= s) +{ + SBSAMachineState *vms =3D SBSA_MACHINE(ms); + int n; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len =3D=3D max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len =3D max_cpus; + for (n =3D 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id =3D + sbsa_ref_cpu_mp_affinity(vms, n); + ms->possible_cpus->cpus[n].props.has_thread_id =3D true; + ms->possible_cpus->cpus[n].props.thread_id =3D n; + } + return ms->possible_cpus; +} + +static CpuInstanceProperties +sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + +static int64_t +sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) +{ + return idx % nb_numa_nodes; +} + +static void sbsa_ref_instance_init(Object *obj) +{ + SBSAMachineState *vms =3D SBSA_MACHINE(obj); + + vms->memmap =3D sbsa_ref_memmap; + vms->irqmap =3D sbsa_ref_irqmap; +} + +static void sbsa_ref_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D sbsa_ref_init; + mc->desc =3D "QEMU 'SBSA Reference' ARM Virtual Machine"; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a57"); + mc->max_cpus =3D 512; + mc->pci_allow_0_address =3D true; + mc->minimum_page_bits =3D 12; + mc->block_default_type =3D IF_IDE; + mc->no_cdrom =3D 1; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D 4; + mc->possible_cpu_arch_ids =3D sbsa_ref_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D sbsa_ref_cpu_index_to_props; + mc->get_default_cpu_node_id =3D sbsa_ref_get_default_cpu_node_id; +} + +static const TypeInfo sbsa_ref_info =3D { + .name =3D TYPE_SBSA_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(SBSAMachineState), + .instance_init =3D sbsa_ref_instance_init, + .class_init =3D sbsa_ref_class_init, +}; + +static void sbsa_ref_machine_init(void) +{ + type_register_static(&sbsa_ref_info); +} + +type_init(sbsa_ref_machine_init); --=20 2.7.4 From nobody Fri Apr 26 15:23:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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bh=lyI8FSWT0nxnAfub97OSeN2LGNcG+tlKwzZTdk59txI=; b=JXJ/ouTPLVZ0geLkHHOD+/CGrh/+aZw/ojC5+ZGEfgW4IvLefsSmMNayYIW8izAb7+ FOut5ZDtqjKGjUIJVW0uZ6cDQgogJ95Om6+fi0EscV2b8FrydPCkT4+G0BQG7Gwvq/cg RwcEnsn/NX/gPwFRuV+LBPnzPqgj2Z0wzswNYFFbG7dYd3Xxght6ZaYjUkDSB8f0LRwO OYAZMFqiuMHoRPmhDJNAgdwMBIPKjgjvIqdvtMS91GvIVdRv9UhGvafBbE9xwjiQ2boy BqOnOsBrG2t5flwm1DsvZe4xWJJFHZ7iWWSDvX87U5BplhTgfYRo1aCrdbcF+UzJARbt 3tfg== X-Gm-Message-State: APjAAAVZgqyVKFlRIipw+PA6bD6MO2MSTUhUAuwcngO92OFivyCozT4O iEzcXxSvFngXouOmEBANzq4fIA== X-Google-Smtp-Source: APXvYqyB7CSBEGx8ma9zjRCcjnv7qG3OQ5yn/L1laVEm919zPj+deOr8bnfuMuJPbMl/p6fhJckikw== X-Received: by 2002:a63:f80c:: with SMTP id n12mr2590314pgh.297.1552644486240; Fri, 15 Mar 2019 03:08:06 -0700 (PDT) From: Hongbo Zhang To: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Fri, 15 Mar 2019 18:07:46 +0800 Message-Id: <1552644466-24625-3-git-send-email-hongbo.zhang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552644466-24625-1-git-send-email-hongbo.zhang@linaro.org> References: <1552644466-24625-1-git-send-email-hongbo.zhang@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v6 2/2] hw/arm: Add arm SBSA reference machine, devices part X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hongbo Zhang , radoslaw.biernacki@linaro.org, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Following the previous patch, this patch adds peripheral devices to the newly introduced SBSA-ref machine. Signed-off-by: Hongbo Zhang --- hw/arm/sbsa-ref.c | 451 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 451 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index b6d31f2..6b26111 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/units.h" +#include "sysemu/device_tree.h" #include "sysemu/numa.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" @@ -28,11 +29,28 @@ #include "kvm_arm.h" #include "hw/arm/arm.h" #include "hw/boards.h" +#include "hw/ide/internal.h" +#include "hw/ide/ahci_internal.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/loader.h" +#include "hw/pci-host/gpex.h" +#include "hw/usb.h" +#include "net/net.h" =20 #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) =20 +#define NUM_IRQS 256 +#define NUM_SMMU_IRQS 4 +#define NUM_SATA_PORTS 6 + +#define VIRTUAL_PMU_IRQ 7 +#define ARCH_GIC_MAINT_IRQ 9 +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 + enum { SBSA_FLASH, SBSA_MEM, @@ -112,6 +130,415 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_EHCI] =3D 10, }; =20 +/* + * Firmware on this machine only uses ACPI table to load OS, these limited + * device tree nodes are just to let firmware know the info which varies f= rom + * command line parameters, so it is not necessary to be fully compatible + * with the kernel CPU and NUMA binding rules. + */ +static void create_fdt(SBSAMachineState *vms) +{ + void *fdt =3D create_device_tree(&vms->fdt_size); + const MachineState *ms =3D MACHINE(vms); + int cpu; + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + vms->fdt =3D fdt; + + qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + + if (have_numa_distance) { + int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); + uint32_t *matrix =3D g_malloc0(size); + int idx, i, j; + + for (i =3D 0; i < nb_numa_nodes; i++) { + for (j =3D 0; j < nb_numa_nodes; j++) { + idx =3D (i * nb_numa_nodes + j) * 3; + matrix[idx + 0] =3D cpu_to_be32(i); + matrix[idx + 1] =3D cpu_to_be32(j); + matrix[idx + 2] =3D cpu_to_be32(numa_info[i].distance[j]); + } + } + + qemu_fdt_add_subnode(fdt, "/distance-map"); + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + matrix, size); + g_free(matrix); + } + + qemu_fdt_add_subnode(vms->fdt, "/cpus"); + + for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + CPUState *cs =3D CPU(armcpu); + + qemu_fdt_add_subnode(vms->fdt, nodename); + + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } + + g_free(nodename); + } +} + +static void create_one_flash(const char *name, hwaddr flashbase, + hwaddr flashsize, const char *file, + MemoryRegion *sysmem) +{ + /* + * Create and map a single flash device. We use the same + * parameters as the flash devices on the Versatile Express board. + */ + DriveInfo *dinfo =3D drive_get_next(IF_PFLASH); + DeviceState *dev =3D qdev_create(NULL, "cfi.pflash01"); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + const uint64_t sectorlength =3D 256 * 1024; + + if (dinfo) { + qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), + &error_abort); + } + + qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); + qdev_prop_set_uint64(dev, "sector-length", sectorlength); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, flashbase, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev)= , 0)); + + if (file) { + char *fn; + int image_size; + + if (drive_get(IF_PFLASH, 0, 0)) { + error_report("The contents of the first flash device may be " + "specified with -bios or with -drive if=3Dpflash.= .. " + "but you cannot use both options at once"); + exit(1); + } + fn =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, file); + if (!fn) { + error_report("Could not find ROM image '%s'", file); + exit(1); + } + image_size =3D load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); + g_free(fn); + if (image_size < 0) { + error_report("Could not load ROM image '%s'", file); + exit(1); + } + } +} + +static void create_flash(const SBSAMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *secure_sysmem) +{ + /* + * Create one secure and nonsecure flash devices to fill SBSA_FLASH + * space in the memmap, file passed via -bios goes in the first one. + */ + hwaddr flashsize =3D vms->memmap[SBSA_FLASH].size / 2; + hwaddr flashbase =3D vms->memmap[SBSA_FLASH].base; + + create_one_flash("sbsa-ref.flash0", flashbase, flashsize, + bios_name, secure_sysmem); + create_one_flash("sbsa-ref.flash1", flashbase + flashsize, flashsize, + NULL, sysmem); +} + +static void create_secure_ram(SBSAMachineState *vms, + MemoryRegion *secure_sysmem) +{ + MemoryRegion *secram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[SBSA_SECURE_MEM].base; + hwaddr size =3D vms->memmap[SBSA_SECURE_MEM].size; + + memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, + &error_fatal); + memory_region_add_subregion(secure_sysmem, base, secram); +} + +static void create_gic(SBSAMachineState *vms, qemu_irq *pic) +{ + DeviceState *gicdev; + SysBusDevice *gicbusdev; + const char *gictype; + uint32_t redist0_capacity, redist0_count; + int i; + + gictype =3D gicv3_class_name(); + + gicdev =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(gicdev, "revision", 3); + qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); + /* + * Note that the num-irq property counts both internal and external + * interrupts; there are always 32 of the former (mandated by GIC spec= ). + */ + qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); + qdev_prop_set_bit(gicdev, "has-security-extensions", true); + + redist0_capacity =3D + vms->memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; + redist0_count =3D MIN(smp_cpus, redist0_capacity); + + qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); + qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); + + qdev_init_nofail(gicdev); + gicbusdev =3D SYS_BUS_DEVICE(gicdev); + sysbus_mmio_map(gicbusdev, 0, vms->memmap[SBSA_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 1, vms->memmap[SBSA_GIC_REDIST].base); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. + */ + for (i =3D 0; i < smp_cpus; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs used for this board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(gicdev, + ppibase + timer_irq[irq= ])); + } + + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, + qdev_get_gpio_in(gicdev, ppibase + + ARCH_GIC_MAINT_IRQ)= ); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(gicdev, ppibase + + VIRTUAL_PMU_IRQ)); + + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); + sysbus_connect_irq(gicbusdev, i + smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } + + for (i =3D 0; i < NUM_IRQS; i++) { + pic[i] =3D qdev_get_gpio_in(gicdev, i); + } +} + +static void create_uart(const SBSAMachineState *vms, qemu_irq *pic, int ua= rt, + MemoryRegion *mem, Chardev *chr) +{ + hwaddr base =3D vms->memmap[uart].base; + int irq =3D vms->irqmap[uart]; + DeviceState *dev =3D qdev_create(NULL, "pl011"); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + qdev_init_nofail(dev); + memory_region_add_subregion(mem, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, pic[irq]); +} + +static void create_rtc(const SBSAMachineState *vms, qemu_irq *pic) +{ + hwaddr base =3D vms->memmap[SBSA_RTC].base; + int irq =3D vms->irqmap[SBSA_RTC]; + + sysbus_create_simple("pl031", base, pic[irq]); +} + +static DeviceState *gpio_key_dev; +static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) +{ + /* use gpio Pin 3 for power button event */ + qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); +} + +static Notifier sbsa_ref_powerdown_notifier =3D { + .notify =3D sbsa_ref_powerdown_req +}; + +static void create_gpio(const SBSAMachineState *vms, qemu_irq *pic) +{ + DeviceState *pl061_dev; + hwaddr base =3D vms->memmap[SBSA_GPIO].base; + int irq =3D vms->irqmap[SBSA_GPIO]; + + pl061_dev =3D sysbus_create_simple("pl061", base, pic[irq]); + + gpio_key_dev =3D sysbus_create_simple("gpio-key", -1, + qdev_get_gpio_in(pl061_dev, 3)); + + /* connect powerdown request */ + qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); +} + +static void create_ahci(const SBSAMachineState *vms, qemu_irq *pic) +{ + hwaddr base =3D vms->memmap[SBSA_AHCI].base; + int irq =3D vms->irqmap[SBSA_AHCI]; + DeviceState *dev; + DriveInfo *hd[NUM_SATA_PORTS]; + SysbusAHCIState *sysahci; + AHCIState *ahci; + int i; + + dev =3D qdev_create(NULL, "sysbus-ahci"); + qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); + + sysahci =3D SYSBUS_AHCI(dev); + ahci =3D &sysahci->ahci; + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i =3D 0; i < ahci->ports; i++) { + if (hd[i] =3D=3D NULL) { + continue; + } + ide_create_drive(&ahci->dev[i].port, 0, hd[i]); + } +} + +static void create_ehci(const SBSAMachineState *vms, qemu_irq *pic) +{ + hwaddr base =3D vms->memmap[SBSA_EHCI].base; + int irq =3D vms->irqmap[SBSA_EHCI]; + USBBus *usb_bus; + + sysbus_create_simple("platform-ehci-usb", base, pic[irq]); + + usb_bus =3D usb_bus_find(-1); + usb_create_simple(usb_bus, "usb-kbd"); + usb_create_simple(usb_bus, "usb-mouse"); +} + +static void create_smmu(const SBSAMachineState *vms, qemu_irq *pic, + PCIBus *bus) +{ + hwaddr base =3D vms->memmap[SBSA_SMMU].base; + int irq =3D vms->irqmap[SBSA_SMMU]; + DeviceState *dev; + int i; + + dev =3D qdev_create(NULL, "arm-smmuv3"); + + object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", + &error_abort); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + for (i =3D 0; i < NUM_SMMU_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + } +} + +static void create_pcie(SBSAMachineState *vms, qemu_irq *pic) +{ + hwaddr base_ecam =3D vms->memmap[SBSA_PCIE_ECAM].base; + hwaddr size_ecam =3D vms->memmap[SBSA_PCIE_ECAM].size; + hwaddr base_mmio =3D vms->memmap[SBSA_PCIE_MMIO].base; + hwaddr size_mmio =3D vms->memmap[SBSA_PCIE_MMIO].size; + hwaddr base_mmio_high =3D vms->memmap[SBSA_PCIE_MMIO_HIGH].base; + hwaddr size_mmio_high =3D vms->memmap[SBSA_PCIE_MMIO_HIGH].size; + hwaddr base_pio =3D vms->memmap[SBSA_PCIE_PIO].base; + int irq =3D vms->irqmap[SBSA_PCIE]; + MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; + MemoryRegion *ecam_alias, *ecam_reg; + DeviceState *dev; + PCIHostState *pci; + int i; + + dev =3D qdev_create(NULL, TYPE_GPEX_HOST); + qdev_init_nofail(dev); + + /* Map ECAM space */ + ecam_alias =3D g_new0(MemoryRegion, 1); + ecam_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, size_ecam); + memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias= ); + + /* Map the MMIO space */ + mmio_alias =3D g_new0(MemoryRegion, 1); + mmio_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, base_mmio, size_mmio); + memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias= ); + + /* Map the MMIO_HIGH space */ + mmio_alias_high =3D g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high= ", + mmio_reg, base_mmio_high, size_mmio_high); + memory_region_add_subregion(get_system_memory(), base_mmio_high, + mmio_alias_high); + + /* Map IO port space */ + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); + + for (i =3D 0; i < GPEX_NUM_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); + } + + pci =3D PCI_HOST_BRIDGE(dev); + if (pci->bus) { + for (i =3D 0; i < nb_nics; i++) { + NICInfo *nd =3D &nd_table[i]; + + if (!nd->model) { + nd->model =3D g_strdup("e1000e"); + } + + pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); + } + } + + pci_create_simple(pci->bus, -1, "VGA"); + + create_smmu(vms, pic, pci->bus); +} + +static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) +{ + const SBSAMachineState *board =3D container_of(binfo, SBSAMachineState, + bootinfo); + + *fdt_size =3D board->fdt_size; + return board->fdt; +} + static void sbsa_ref_init(MachineState *machine) { SBSAMachineState *vms =3D SBSA_MACHINE(machine); @@ -122,6 +549,7 @@ static void sbsa_ref_init(MachineState *machine) bool firmware_loaded =3D bios_name || drive_get(IF_PFLASH, 0, 0); const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; + qemu_irq pic[NUM_IRQS]; =20 if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { error_report("sbsa-ref: CPU type other than the built-in " @@ -206,11 +634,34 @@ static void sbsa_ref_init(MachineState *machine) machine->ram_size); memory_region_add_subregion(sysmem, vms->memmap[SBSA_MEM].base, ram); =20 + create_fdt(vms); + + create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); + + create_secure_ram(vms, secure_sysmem); + + create_gic(vms, pic); + + create_uart(vms, pic, SBSA_UART, sysmem, serial_hd(0)); + + create_uart(vms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); + + create_rtc(vms, pic); + + create_gpio(vms, pic); + + create_ahci(vms, pic); + + create_ehci(vms, pic); + + create_pcie(vms, pic); + vms->bootinfo.ram_size =3D machine->ram_size; vms->bootinfo.kernel_filename =3D machine->kernel_filename; vms->bootinfo.nb_cpus =3D smp_cpus; vms->bootinfo.board_id =3D -1; vms->bootinfo.loader_start =3D vms->memmap[SBSA_MEM].base; + vms->bootinfo.get_dtb =3D sbsa_ref_dtb; vms->bootinfo.firmware_loaded =3D firmware_loaded; arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); } --=20 2.7.4