From nobody Sat Apr 20 11:45:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552582009842499.3606263416468; Thu, 14 Mar 2019 09:46:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:41435 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4TVF-0004YE-RH for importer@patchew.org; Thu, 14 Mar 2019 12:46:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h4TPZ-0000EQ-B0 for qemu-devel@nongnu.org; Thu, 14 Mar 2019 12:40:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h4TJC-0007LW-FS for qemu-devel@nongnu.org; Thu, 14 Mar 2019 12:34:19 -0400 Received: from sainfoin-smtp-out.extra.cea.fr ([132.167.192.228]:58871) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h4TJC-0007Gk-2L; Thu, 14 Mar 2019 12:34:18 -0400 Received: from pisaure.intra.cea.fr (pisaure.intra.cea.fr [132.166.88.21]) by sainfoin-sys.extra.cea.fr (8.14.7/8.14.7/CEAnet-Internet-out-4.0) with ESMTP id x2EGYAAL017597; Thu, 14 Mar 2019 17:34:10 +0100 Received: from localhost.localdomain (localhost [127.0.0.1]) by localhost (Postfix) with ESMTP id F1EC92058B2; Thu, 14 Mar 2019 17:34:09 +0100 (CET) Received: from pisaure by pisaure with queue id 6968901-2; Thu, 14 Mar 2019 16:34:09 GMT Received: from muguet2-smtp-out.intra.cea.fr (muguet2-smtp-out.intra.cea.fr [132.166.192.13]) by pisaure.intra.cea.fr (Postfix) with ESMTP id C8A872039A2; Thu, 14 Mar 2019 17:34:09 +0100 (CET) Received: from amir-VirtualBox.intra.cea.fr (is233176-dock.intra.cea.fr [10.8.35.126]) by muguet2-sys.intra.cea.fr (8.14.7/8.14.7/CEAnet-Internet-out-4.0) with ESMTP id x2EGY9WN003367; Thu, 14 Mar 2019 17:34:09 +0100 From: Amir Charif To: qemu-devel@nongnu.org Date: Thu, 14 Mar 2019 17:00:48 +0100 Message-Id: <1552579248-31025-1-git-send-email-amir.charif@cea.fr> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 132.167.192.228 Subject: [Qemu-devel] [PATCH] Check access permission to ADDVL/ADDPL/RDVL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Amir Charif , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Signed-off-by: Amir Charif Reviewed-by: Richard Henderson --- target/arm/translate-sve.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 3a2eb51..245cd82 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX= _rr *a) =20 static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); - TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + } return true; } =20 static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); - TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd =3D cpu_reg_sp(s, a->rd); + TCGv_i64 rn =3D cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + } return true; } =20 static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - TCGv_i64 reg =3D cpu_reg(s, a->rd); - tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 reg =3D cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + } return true; } =20 --=20 2.7.4