From nobody Tue May 7 15:21:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155239532248096.66865160920986; Tue, 12 Mar 2019 05:55:22 -0700 (PDT) Received: from localhost ([127.0.0.1]:51828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3gwB-0008Qb-Bd for importer@patchew.org; Tue, 12 Mar 2019 08:55:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3guL-000773-SB for qemu-devel@nongnu.org; Tue, 12 Mar 2019 08:53:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3guK-00032i-Dw for qemu-devel@nongnu.org; Tue, 12 Mar 2019 08:53:25 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2191 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h3guF-0002nL-FC; Tue, 12 Mar 2019 08:53:20 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D425ACF5711A91F593F1; Tue, 12 Mar 2019 20:53:06 +0800 (CST) Received: from localhost.localdomain (10.143.28.91) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.408.0; Tue, 12 Mar 2019 20:52:57 +0800 From: Dongjiu Geng To: , , , Date: Tue, 12 Mar 2019 20:52:57 +0800 Message-ID: <1552395177-12608-1-git-send-email-gengdongjiu@huawei.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.143.28.91] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 45.249.212.190 Subject: [Qemu-devel] [PATCH V3] target/arm: change arch timer registers access permission X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wangnan0@huawei.com, chenguoping@huawei.com, wuyuming3@huawei.com, larkin.zhanglixin@huawei.com, linqiangmin@huawei.com, liuyutao2@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some generic arch timer registers are Config-RW in the EL0, which means the EL0 exception level can have write permission if it is appropriately configured. When VM access registers, QEMU firstly checks whether they have RW permission, then check whether it is appropriately configured. If they are defined to read only in EL0, even though they have been appropriately configured, they still do not have write permission. So need to add the write permission according to ARMV8 spec when define it. Signed-off-by: Dongjiu Geng Reviewed-by: Richard Henderson --- Change since V2: 1. Change 'Ready only' to 'read only' in the comments Change since V1: 1. Change 'PL1_RW | RL0_RW' to PL0_RW because PL0_RW implied that the highe= r PLx all have RW permission When VM kernel or Hypervisor configures the timer registers to RW in EL0 user space, it will still have below panic when EL0 user space access the timer registers. [INFO ]@(el0_sync:60): UNIMPLEMENTED, esr=3D2000000 [INFO ]@(unimpl_exception:88): KERNEL UNIMPLEMENTED EXCEPTION [INFO ]@(unimpl_exception:98): FAR=3D0000000000000000, ESR=3D02000000 (EC= =3D0x0, IL=3D0x1, ISS=3D0x0) [INFO ]@(dump_registers:64): KERNEL REGISTERS [INFO ]@(dump_registers:68): X0=3D00000000f52b7d50 X1=3D00000000040d5040 [INFO ]@(dump_registers:68): X2=3D0000004000033e10 X3=3D0000000000000000 [INFO ]@(dump_registers:68): X4=3D000000007fffffff X5=3D0000000000000020 [INFO ]@(dump_registers:68): X6=3D0000000000000020 X7=3D000000000c00b030 --- target/arm/helper.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2607d39..c8d3c21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2665,7 +2665,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { /* per-timer control */ { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), @@ -2674,7 +2674,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTP_CTL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), @@ -2682,14 +2682,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { }, { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), @@ -2697,7 +2697,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, @@ -2706,31 +2706,31 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, { .name =3D "CNTP_TVAL_S", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, }, { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write, }, { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, }, { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW | PL0_R, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write, }, @@ -2758,7 +2758,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { /* Comparison value, indicating when the timer goes off */ { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_NS, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .accessfn =3D gt_ptimer_access, @@ -2766,7 +2766,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, .secure =3D ARM_CP_SECSTATE_S, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), .accessfn =3D gt_ptimer_access, @@ -2774,14 +2774,14 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[= ] =3D { }, { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write, }, { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .accessfn =3D gt_vtimer_access, @@ -2789,7 +2789,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { }, { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW | PL0_R, + .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, --=20 2.7.4