From nobody Fri May 3 09:19:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1552320065983395.62292127819273; Mon, 11 Mar 2019 09:01:05 -0700 (PDT) Received: from localhost ([127.0.0.1]:35766 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3NMN-00031H-0U for importer@patchew.org; Mon, 11 Mar 2019 12:01:03 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h3MXR-0005P6-U6 for qemu-devel@nongnu.org; Mon, 11 Mar 2019 11:08:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h3MXR-0007WS-2k for qemu-devel@nongnu.org; Mon, 11 Mar 2019 11:08:25 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55615 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h3MXQ-0006lh-NN for qemu-devel@nongnu.org; Mon, 11 Mar 2019 11:08:25 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 9827C1A1D57; Mon, 11 Mar 2019 16:07:21 +0100 (CET) Received: from rtrkw870-lin.domain.local (rtrkw870-lin.domain.local [10.10.13.132]) by mail.rt-rk.com (Postfix) with ESMTPSA id 757E91A1FC3; Mon, 11 Mar 2019 16:07:21 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Brankovic To: qemu-devel@nongnu.org Date: Mon, 11 Mar 2019 16:07:10 +0100 Message-Id: <1552316831-14098-2-git-send-email-stefan.brankovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552316831-14098-1-git-send-email-stefan.brankovic@rt-rk.com> References: <1552316831-14098-1-git-send-email-stefan.brankovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Mon, 11 Mar 2019 11:55:25 -0400 Subject: [Qemu-devel] [PATCH 1/2] target/tilegx: Implement emulation of TILEGX instructions V1CMPLEU and V1CMPLTU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, richard.henderson@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement emulation of TILEGX instruction V1CMPLEU and V1CMPLTU using TCG front end operations. Signed-off-by: Stefan Brankovic --- target/tilegx/translate.c | 62 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index f201150..396c33e 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -491,6 +491,56 @@ static TileExcp gen_specill(DisasContext *dc, unsigned= dest, unsigned srca, return gen_signal(dc, signo, sigcode, mnemonic); } =20 +static void gen_v1cmpleu(TCGv tdest, TCGv tsrca, TCGv tsrcb) +{ + TCGv_64 t_sa =3D tcg_temp_new(); + TCGv_64 t_sb =3D tcg_temp_new(); + TCGv_64 t_d =3D tcg_temp_new(); + int64_t mask =3D 0xffULL; + int64_t mask1 =3D 0x1ULL; + int i; + + tcg_gen_movi_i64(tdest, 0x0ULL); + for (i =3D 0; i < 8; i++) { + tcg_gen_andi_i64(t_sa, tsrca, mask); + tcg_gen_andi_i64(t_sb, tsrcb, mask); + tcg_gen_setcond_i64(TCG_COND_LEU, t_d, t_sa, t_sb); + tcg_gen_andi_i64(t_d, t_d, mask1); + tcg_gen_or_i64(tdest, tdest, t_d); + mask =3D mask << 8; + mask1 =3D mask1 << 8; + } + + tcg_temp_free(t_sa); + tcg_temp_free(t_sb); + tcg_temp_free(t_d); +} + +static void gen_v1cmpltu(TCGv tdest, TCGv tsrca, TCGv tsrcb) +{ + TCGv_64 t_sa =3D tcg_temp_new(); + TCGv_64 t_sb =3D tcg_temp_new(); + TCGv_64 t_d =3D tcg_temp_new(); + int64_t mask =3D 0xffULL; + int64_t mask1 =3D 0x1ULL; + int i; + + tcg_gen_movi_i64(tdest, 0x0ULL); + for (i =3D 0; i < 8; i++) { + tcg_gen_andi_i64(t_sa, tsrca, mask); + tcg_gen_andi_i64(t_sb, tsrcb, mask); + tcg_gen_setcond_i64(TCG_COND_LTU, t_d, t_sa, t_sb); + tcg_gen_andi_i64(t_d, t_d, mask1); + tcg_gen_or_i64(tdest, tdest, t_d); + mask =3D mask << 8; + mask1 =3D mask1 << 8; + } + + tcg_temp_free(t_sa); + tcg_temp_free(t_sb); + tcg_temp_free(t_d); +} + static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, unsigned dest, unsigned srca, uint64_t bundl= e) { @@ -1247,12 +1297,8 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, uns= igned opext, break; case OE_RRR(V1CMPLES, 0, X0): case OE_RRR(V1CMPLES, 0, X1): - case OE_RRR(V1CMPLEU, 0, X0): - case OE_RRR(V1CMPLEU, 0, X1): case OE_RRR(V1CMPLTS, 0, X0): case OE_RRR(V1CMPLTS, 0, X1): - case OE_RRR(V1CMPLTU, 0, X0): - case OE_RRR(V1CMPLTU, 0, X1): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V1CMPNE, 0, X0): case OE_RRR(V1CMPNE, 0, X1): @@ -1260,6 +1306,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, uns= igned opext, gen_v1cmpne0(tdest); mnemonic =3D "v1cmpne"; break; + case OE_RRR(V1CMPLEU, 0, X0): + case OE_RRR(V1CMPLEU, 0, X1): + gen_v1cmpleu(tdest, tsrca, tsrcb); + break; + case OE_RRR(V1CMPLTU, 0, X0): + case OE_RRR(V1CMPLTU, 0, X1): + gen_v1cmpltu(tdest, tsrca, tsrcb); + break; case OE_RRR(V1DDOTPUA, 0, X0): case OE_RRR(V1DDOTPUSA, 0, X0): case OE_RRR(V1DDOTPUS, 0, X0): --=20 2.7.4 From nobody Fri May 3 09:19:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155231988498613.023690976363469; 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Mon, 11 Mar 2019 16:07:21 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Stefan Brankovic To: qemu-devel@nongnu.org Date: Mon, 11 Mar 2019 16:07:11 +0100 Message-Id: <1552316831-14098-3-git-send-email-stefan.brankovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552316831-14098-1-git-send-email-stefan.brankovic@rt-rk.com> References: <1552316831-14098-1-git-send-email-stefan.brankovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 X-Mailman-Approved-At: Mon, 11 Mar 2019 11:55:25 -0400 Subject: [Qemu-devel] [PATCH 2/2] target/tilegx: Implement emulation of TILEGX instructions V2CMPLEU and V2CMPLTU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, richard.henderson@linaro.org, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement emulation of TILEGX instruction V2CMPLEU and V2CMPLTU using TCG front end operations. Signed-off-by: Stefan Brankovic --- target/tilegx/translate.c | 62 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index 396c33e..6e0dc44 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -541,6 +541,56 @@ static void gen_v1cmpltu(TCGv tdest, TCGv tsrca, TCGv = tsrcb) tcg_temp_free(t_d); } =20 +static void gen_v2cmpleu(TCGv tdest, TCGv tsrca, TCGv tsrcb) +{ + TCGv_64 t_sa =3D tcg_temp_new(); + TCGv_64 t_sb =3D tcg_temp_new(); + TCGv_64 t_d =3D tcg_temp_new(); + int64_t mask =3D 0xffffULL; + int64_t mask1 =3D 0x1ULL; + int i; + + tcg_gen_movi_i64(tdest, 0x0ULL); + for (i =3D 0; i < 4; i++) { + tcg_gen_andi_i64(t_sa, tsrca, mask); + tcg_gen_andi_i64(t_sb, tsrcb, mask); + tcg_gen_setcond_i64(TCG_COND_LEU, t_d, t_sa, t_sb); + tcg_gen_andi_i64(t_d, t_d, mask1); + tcg_gen_or_i64(tdest, tdest, t_d); + mask =3D mask << 16; + mask1 =3D mask1 << 16; + } + + tcg_temp_free(t_sa); + tcg_temp_free(t_sb); + tcg_temp_free(t_d); +} + +static void gen_v2cmpltu(TCGv tdest, TCGv tsrca, TCGv tsrcb) +{ + TCGv_64 t_sa =3D tcg_temp_new(); + TCGv_64 t_sb =3D tcg_temp_new(); + TCGv_64 t_d =3D tcg_temp_new(); + int64_t mask =3D 0xffffULL; + int64_t mask1 =3D 0x1ULL; + int i; + + tcg_gen_movi_i64(tdest, 0x0ULL); + for (i =3D 0; i < 4; i++) { + tcg_gen_andi_i64(t_sa, tsrca, mask); + tcg_gen_andi_i64(t_sb, tsrcb, mask); + tcg_gen_setcond_i64(TCG_COND_LTU, t_d, t_sa, t_sb); + tcg_gen_andi_i64(t_d, t_d, mask1); + tcg_gen_or_i64(tdest, tdest, t_d); + mask =3D mask << 16; + mask1 =3D mask1 << 16; + } + + tcg_temp_free(t_sa); + tcg_temp_free(t_sb); + tcg_temp_free(t_d); +} + static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, unsigned dest, unsigned srca, uint64_t bundl= e) { @@ -1390,17 +1440,21 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, un= signed opext, case OE_RRR(V2CMPEQ, 0, X1): case OE_RRR(V2CMPLES, 0, X0): case OE_RRR(V2CMPLES, 0, X1): - case OE_RRR(V2CMPLEU, 0, X0): - case OE_RRR(V2CMPLEU, 0, X1): case OE_RRR(V2CMPLTS, 0, X0): case OE_RRR(V2CMPLTS, 0, X1): - case OE_RRR(V2CMPLTU, 0, X0): - case OE_RRR(V2CMPLTU, 0, X1): case OE_RRR(V2CMPNE, 0, X0): case OE_RRR(V2CMPNE, 0, X1): case OE_RRR(V2DOTPA, 0, X0): case OE_RRR(V2DOTP, 0, X0): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + case OE_RRR(V2CMPLEU, 0, X0): + case OE_RRR(V2CMPLEU, 0, X1): + gen_v2cmpleu(tdest, tsrca, tsrcb); + break; + case OE_RRR(V2CMPLTU, 0, X0): + case OE_RRR(V2CMPLTU, 0, X1): + gen_v2cmpltu(tdest, tsrca, tsrcb); + break; case OE_RRR(V2INT_H, 0, X0): case OE_RRR(V2INT_H, 0, X1): gen_helper_v2int_h(tdest, tsrca, tsrcb); --=20 2.7.4