From nobody Sun Nov 9 16:00:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551713438974945.689521610063; Mon, 4 Mar 2019 07:30:38 -0800 (PST) Received: from localhost ([127.0.0.1]:55819 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0pY0-0000I7-W8 for importer@patchew.org; Mon, 04 Mar 2019 10:30:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h0pIe-00040u-Gf for qemu-devel@nongnu.org; Mon, 04 Mar 2019 10:14:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h0pIc-0007qc-Jk for qemu-devel@nongnu.org; Mon, 04 Mar 2019 10:14:40 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:39726 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h0pIc-0007o7-3z for qemu-devel@nongnu.org; Mon, 04 Mar 2019 10:14:38 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4CA3D1A2138; Mon, 4 Mar 2019 16:13:33 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id E70D81A2073; Mon, 4 Mar 2019 16:13:32 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2019 16:13:16 +0100 Message-Id: <1551712405-2530-5-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551712405-2530-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551712405-2530-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add emulation of MMI instruction PEXCH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Markovic --- target/mips/translate.c | 97 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4763e06..9472477 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx) } } =20 +/* + * PEXCH rd, rt + * + * Parallel Exchange Center Halfword + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 | + * +-----------+---------+---------+---------+---------+-----------+ + */ +static void gen_mmi_pexch(DisasContext *ctx) +{ + uint32_t pd, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + pd =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (unlikely(pd !=3D 0)) { + generate_exception_end(ctx, EXCP_RI); + } else if (rd =3D=3D 0) { + /* nop */ + } else if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else if (rd =3D=3D rt) { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 16) - 1; + uint64_t mask1 =3D mask0 << 16; + uint64_t mask2 =3D mask1 << 16; + uint64_t mask3 =3D (mask2 << 16) | mask0; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + + tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3); + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0); + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + + tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3); + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0); + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } else { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 16) - 1; + uint64_t mask1 =3D mask0 << 16; + uint64_t mask2 =3D mask1 << 16; + uint64_t mask3 =3D mask2 << 16; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1); + tcg_gen_shli_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0); + tcg_gen_or_i64(t0, t0, t1); + + tcg_gen_mov_i64(cpu_gpr[rd], t0); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1); + tcg_gen_shli_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0); + tcg_gen_or_i64(t0, t0, t1); + + tcg_gen_mov_i64(cpu_mmr[rd], t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } +} + #endif =20 =20 @@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ - case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ break; @@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PCPYUD: gen_mmi_pcpyud(ctx); break; + case MMI_OPC_3_PEXCH: + gen_mmi_pexch(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI3"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4