From nobody Sun Nov 9 17:55:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15511863192837.061762342708448; Tue, 26 Feb 2019 05:05:19 -0800 (PST) Received: from localhost ([127.0.0.1]:54741 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gycQ1-0001O1-7c for importer@patchew.org; Tue, 26 Feb 2019 08:05:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35706) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gycIJ-0004DH-GW for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:57:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gycID-0000DN-Bz for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:57:09 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:40128 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gycIC-0000CS-VN for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:57:05 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 08B0F1A2260; Tue, 26 Feb 2019 13:55:59 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id D58511A222E; Tue, 26 Feb 2019 13:55:58 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:55:35 +0100 Message-Id: <1551185735-17154-10-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551185735-17154-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1551185735-17154-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v4 9/9] target/mips: Add support for DSPRAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch= pad RAM used for temporary storage of data. The DSPRAM provides a connection to on-= chip memory or memory-mapped registers, which are accessed in parallel with the = L1 data cache to minimize access latency Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- default-configs/mips-softmmu-common.mak | 1 + hw/mips/cps.c | 3 ++- hw/mips/mips_malta.c | 31 +++++++++++++++++++++++++++++= ++ hw/misc/Makefile.objs | 1 + include/hw/mips/cps.h | 2 ++ target/mips/cpu.h | 5 +++++ target/mips/internal.h | 1 + target/mips/op_helper.c | 10 ++++++++++ target/mips/translate.c | 8 ++++++++ target/mips/translate_init.inc.c | 2 ++ 10 files changed, 63 insertions(+), 1 deletion(-) diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips= -softmmu-common.mak index ded7498..d3f85b0 100644 --- a/default-configs/mips-softmmu-common.mak +++ b/default-configs/mips-softmmu-common.mak @@ -35,6 +35,7 @@ CONFIG_ISA_TESTDEV=3Dy CONFIG_EMPTY_SLOT=3Dy CONFIG_MIPS_CPS=3Dy CONFIG_MIPS_ITU=3Dy +CONFIG_MIPS_DSPRAM=3Dy CONFIG_I2C=3Dy CONFIG_R4K=3Dy CONFIG_MALTA=3Dy diff --git a/hw/mips/cps.c b/hw/mips/cps.c index fc97f59..97e2232 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -102,7 +102,8 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", &err); if (saar_present) { - qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_S= AAR); + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", + (void *) &env->CP0_SAAR[0]); } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 7a403ef..306d701 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1170,6 +1170,36 @@ static void create_cps(MaltaState *s, const char *cp= u_type, *cbus_irq =3D NULL; } =20 +static void create_dspram(void) +{ + MIPSCPU *cpu =3D MIPS_CPU(first_cpu); + CPUMIPSState *env =3D &cpu->env; + bool dspram_present =3D (bool) env->dspramp; + Error *err =3D NULL; + + env->dspram =3D g_new0(MIPSDSPRAMState, 1); + + /* DSPRAM */ + if (dspram_present) { + if (!(bool) env->saarp) { + error_report("%s: DSPRAM requires SAAR registers", __func__); + exit(1); + } + object_initialize(env->dspram, sizeof(MIPSDSPRAMState), + TYPE_MIPS_DSPRAM); + qdev_set_parent_bus(DEVICE(env->dspram), sysbus_get_default()); + qdev_prop_set_ptr(DEVICE(env->dspram), "saar", + (void *) &env->CP0_SAAR[1]); + object_property_set_bool(OBJECT(env->dspram), true, "realized", &e= rr); + if (err !=3D NULL) { + error_report("%s: DSPRAM initialisation failed", __func__); + exit(1); + } + memory_region_add_subregion(get_system_memory(), 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(env->dspram), 0)= ); + } +} + static void mips_create_cpu(MaltaState *s, const char *cpu_type, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { @@ -1178,6 +1208,7 @@ static void mips_create_cpu(MaltaState *s, const char= *cpu_type, } else { create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq); } + create_dspram(); } =20 static diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 74c91d2..37c4108 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) +=3D stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) +=3D mips_cpc.o obj-$(CONFIG_MIPS_ITU) +=3D mips_itu.o +obj-$(CONFIG_MIPS_DSPRAM) +=3D mips_dspram.o obj-$(CONFIG_MPS2_FPGAIO) +=3D mps2-fpgaio.o obj-$(CONFIG_MPS2_SCC) +=3D mps2-scc.o =20 diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index aab1af9..a637036 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -25,6 +25,7 @@ #include "hw/intc/mips_gic.h" #include "hw/misc/mips_cpc.h" #include "hw/misc/mips_itu.h" +#include "hw/misc/mips_dspram.h" =20 #define TYPE_MIPS_CPS "mips-cps" #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS) @@ -41,6 +42,7 @@ typedef struct MIPSCPSState { MIPSGICState gic; MIPSCPCState cpc; MIPSITUState itu; + MIPSDSPRAMState dspram; } MIPSCPSState; =20 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a10eeb0..da21d2b 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1022,6 +1022,7 @@ struct CPUMIPSState { uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ int saarp; + int dspramp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -1039,6 +1040,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ + struct MIPSDSPRAMState *dspram; target_ulong exception_base; /* ExceptionBase input to the core */ }; =20 @@ -1181,6 +1183,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, in= t level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); =20 +/* mips_dspram.c */ +void dspram_reconfigure(struct MIPSDSPRAMState *dspram); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index 8f6fc91..766350c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -62,6 +62,7 @@ struct mips_def_t { uint64_t insn_flags; enum mips_mmu_types mmu_type; int32_t SAARP; + int32_t DSPRAMP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5..e49fe05 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1614,6 +1614,11 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } @@ -1631,6 +1636,11 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) itc_reconfigure(env->itu); } break; + case 1: + if (env->dspram) { + dspram_reconfigure(env->dspram); + } + break; } } } diff --git a/target/mips/translate.c b/target/mips/translate.c index 3b17020..dd50c52 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29925,6 +29925,8 @@ void cpu_state_reset(CPUMIPSState *env) env->active_fpu.fcr31 =3D env->cpu_model->CP1_fcr31; env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; + env->saarp =3D env->cpu_model->SAARP; + env->dspramp =3D env->cpu_model->DSPRAMP; =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); @@ -30079,6 +30081,12 @@ void cpu_state_reset(CPUMIPSState *env) msa_reset(env); } =20 + /* DSPRAM */ + if (env->dspramp) { + /* Fixed DSPRAM size with Default Value */ + env->CP0_SAAR[1] =3D 0x10 << 1; + } + compute_hflags(env); restore_fp_status(env); restore_pamask(env); diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index bf559af..4c49a0e 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -760,6 +760,8 @@ const mips_def_t mips_defs[] =3D .PABITS =3D 48, .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, .mmu_type =3D MMU_TYPE_R4000, + .SAARP =3D 1, + .DSPRAMP =3D 1, }, { .name =3D "Loongson-2E", --=20 2.7.4