From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551183954234357.54849594317557; Tue, 26 Feb 2019 04:25:54 -0800 (PST) Received: from localhost ([127.0.0.1]:54102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybns-0008Oo-2z for importer@patchew.org; Tue, 26 Feb 2019 07:25:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyblu-0007Bs-FC for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyblr-00071o-EM for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:42 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:43264 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gybln-0006we-M2 for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:37 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 749561A2231; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 46EAD1A2076; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:12 +0100 Message-Id: <1551183797-13570-2-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 1/6] target/mips: Preparing for adding MMI instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Set up MMI code to be compiled only for TARGET_MIPS64. This is needed so that GPRs are 64 bit, and combined with MMI registers, they will form full 128 bit registers. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Rikalo --- target/mips/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 3b17020..332ff79 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4362,6 +4362,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } =20 +#if defined(TARGET_MIPS64) /* Copy GPR to and from TX79 HI1/LO1 register. */ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { @@ -4397,6 +4398,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_= t opc, int reg) break; } } +#endif =20 /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) @@ -4746,6 +4748,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_temp_free(t1); } =20 +#if defined(TARGET_MIPS64) static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt) { TCGv t0, t1; @@ -4802,6 +4805,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) tcg_temp_free(t0); tcg_temp_free(t1); } +#endif =20 static void gen_muldiv(DisasContext *ctx, uint32_t opc, int acc, int rs, int rt) @@ -24324,6 +24328,29 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) } =20 =20 +#if defined(TARGET_MIPS64) + +/* + * + * MMI (MultiMedia Interface) ASE instructions + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + */ + +/* + * MMI instructions category: data communication + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH + * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W + * PCPYUD PEXCEH PEXTLW PPACW + * PEXCEW PEXTUB + * PEXTUB + * PEXTUB + */ + +#endif + + #if !defined(TARGET_MIPS64) =20 /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ @@ -27247,6 +27274,9 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } } =20 + +#if defined(TARGET_MIPS64) + static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx) { uint32_t opc =3D MASK_MMI0(ctx->opcode); @@ -27491,6 +27521,8 @@ static void decode_mmi_sq(CPUMIPSState *env, DisasC= ontext *ctx) gen_mmi_sq(ctx, base, rt, offset); } =20 +#endif + static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -28796,10 +28828,11 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) decode_opc_special(env, ctx); break; case OPC_SPECIAL2: +#if defined(TARGET_MIPS64) if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI))= { decode_mmi(env, ctx); -#if !defined(TARGET_MIPS64) - } else if (ctx->insn_flags & ASE_MXU) { +#else + if (ctx->insn_flags & ASE_MXU) { decode_opc_mxu(env, ctx); #endif } else { @@ -28807,11 +28840,15 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) } break; case OPC_SPECIAL3: +#if defined(TARGET_MIPS64) if (ctx->insn_flags & INSN_R5900) { decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ } else { decode_opc_special3(env, ctx); } +#else + decode_opc_special3(env, ctx); +#endif break; case OPC_REGIMM: op1 =3D MASK_REGIMM(ctx->opcode); @@ -29483,7 +29520,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_MSA: /* OPC_MDMX */ if (ctx->insn_flags & INSN_R5900) { +#if defined(TARGET_MIPS64) gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */ +#endif } else { /* MDMX: Not implemented. */ gen_msa(env, ctx); --=20 2.7.4 From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551184090877521.5702420285955; Tue, 26 Feb 2019 04:28:10 -0800 (PST) Received: from localhost ([127.0.0.1]:54138 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybqB-0001zF-PJ for importer@patchew.org; Tue, 26 Feb 2019 07:28:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57120) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyblv-0007Cm-PZ for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyblu-00073P-Qq for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:43 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:43347 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyblu-0006wj-FD for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7F9ED1A2132; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 514F61A207A; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:13 +0100 Message-Id: <1551183797-13570-3-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add emulation of MMI instruction PCPYH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Rikalo --- target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 332ff79..0d648b6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24348,6 +24348,68 @@ static void decode_opc_special(CPUMIPSState *env, = DisasContext *ctx) * PEXTUB */ =20 +/* + * PCPYH rd, rt + * + * Parallel Copy Halfword + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 | + * +-----------+---------+---------+---------+---------+-----------+ + */ +static void gen_mmi_pcpyh(DisasContext *ctx) +{ + uint32_t pd, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + pd =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (unlikely(pd !=3D 0)) { + generate_exception_end(ctx, EXCP_RI); + } else if (rd =3D=3D 0) { + /* nop */ + } else if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask =3D (1ULL << 16) - 1; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask); + tcg_gen_movi_i64(t1, 0); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + + tcg_gen_mov_i64(cpu_gpr[rd], t1); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask); + tcg_gen_movi_i64(t1, 0); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_or_i64(t1, t0, t1); + + tcg_gen_mov_i64(cpu_mmr[rd], t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } +} + #endif =20 =20 @@ -27400,10 +27462,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ - case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ break; + case MMI_OPC_3_PCPYH: + gen_mmi_pcpyh(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI3"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155118395170892.28576755182519; Tue, 26 Feb 2019 04:25:51 -0800 (PST) Received: from localhost ([127.0.0.1]:54110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybns-0008T4-Id for importer@patchew.org; Tue, 26 Feb 2019 07:25:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyblv-0007CH-40 for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyblu-00072p-Ag for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:43 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:43393 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyblp-0006wm-7R for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:38 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8AA9D1A1FCC; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 5AAD71A21E8; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:14 +0100 Message-Id: <1551183797-13570-4-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 3/6] target/mips: Add emulation of MMI instruction PCPYLD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add emulation of MMI instruction PCPYLD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Rikalo --- target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0d648b6..7c26a43 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24410,6 +24410,45 @@ static void gen_mmi_pcpyh(DisasContext *ctx) } } =20 +/* + * PCPYLD rd, rs, rt + * + * Parallel Copy Lower Doubleword + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI | rs | rt | rd | PCPYLD | MMI2 | + * +-----------+---------+---------+---------+---------+-----------+ + */ +static void gen_mmi_pcpyld(DisasContext *ctx) +{ + uint32_t rs, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + rs =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (rd =3D=3D 0) { + /* nop */ + } else { + if (rs =3D=3D 0) { + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else { + tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]); + } + if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + } else { + if (rd !=3D rt) { + tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]); + } + } + } +} + #endif =20 =20 @@ -27424,7 +27463,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */ case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */ case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */ - case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */ case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */ case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */ case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */ @@ -27439,6 +27477,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 = */ break; + case MMI_OPC_2_PCPYLD: + gen_mmi_pcpyld(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI2"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551184089513149.57154114142475; Tue, 26 Feb 2019 04:28:09 -0800 (PST) Received: from localhost ([127.0.0.1]:54134 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybqA-0001xW-EU for importer@patchew.org; Tue, 26 Feb 2019 07:28:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57076) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyblu-0007Bv-FT for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyblr-00071s-EM for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:42 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:43454 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gybln-0006wt-ML for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:37 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 943091A2076; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 649F61A2229; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:15 +0100 Message-Id: <1551183797-13570-5-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 4/6] target/mips: Add emulation of MMI instruction PCPYUD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add emulation of MMI instruction PCPYUD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic Reviewed-by: Aleksandar Rikalo --- target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7c26a43..dd90178 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24449,6 +24449,45 @@ static void gen_mmi_pcpyld(DisasContext *ctx) } } =20 +/* + * PCPYUD rd, rs, rt + * + * Parallel Copy Upper Doubleword + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI | rs | rt | rd | PCPYUD | MMI3 | + * +-----------+---------+---------+---------+---------+-----------+ + */ +static void gen_mmi_pcpyud(DisasContext *ctx) +{ + uint32_t rs, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + rs =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (rd =3D=3D 0) { + /* nop */ + } else { + if (rs =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]); + } + if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else { + if (rd !=3D rt) { + tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]); + } + } + } +} + #endif =20 =20 @@ -27499,7 +27538,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */ case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */ case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ - case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */ case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ @@ -27509,6 +27547,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PCPYH: gen_mmi_pcpyh(ctx); break; + case MMI_OPC_3_PCPYUD: + gen_mmi_pcpyud(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI3"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1551184090888201.95164229583872; Tue, 26 Feb 2019 04:28:10 -0800 (PST) Received: from localhost ([127.0.0.1]:54136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gybqA-0001yB-QJ for importer@patchew.org; Tue, 26 Feb 2019 07:28:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyblw-0007D0-39 for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyblv-00073z-0A for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:44 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:47712 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyblu-00071z-JE for qemu-devel@nongnu.org; Tue, 26 Feb 2019 07:23:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B175D1A21E8; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6E0561A224F; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:16 +0100 Message-Id: <1551183797-13570-6-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add emulation of MMI instruction PEXCH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic --- target/mips/translate.c | 97 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index dd90178..66cea86 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx) } } =20 +/* + * PEXCH rd, rt + * + * Parallel Exchange Center Halfword + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 | + * +-----------+---------+---------+---------+---------+-----------+ + */ +static void gen_mmi_pexch(DisasContext *ctx) +{ + uint32_t pd, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + pd =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (unlikely(pd !=3D 0)) { + generate_exception_end(ctx, EXCP_RI); + } else if (rd =3D=3D 0) { + /* nop */ + } else if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else if (rd =3D=3D rt) { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 16) - 1; + uint64_t mask1 =3D mask0 << 16; + uint64_t mask2 =3D mask1 << 16; + uint64_t mask3 =3D (mask2 << 16) | mask0; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + + tcg_gen_andi_i64(cpu_gpr[rt], cpu_gpr[rt], mask3); + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0); + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1); + tcg_gen_shli_i64(t0, t0, 16); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + + tcg_gen_andi_i64(cpu_mmr[rt], cpu_mmr[rt], mask3); + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0); + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } else { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 16) - 1; + uint64_t mask1 =3D mask0 << 16; + uint64_t mask2 =3D mask1 << 16; + uint64_t mask3 =3D mask2 << 16; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1); + tcg_gen_shli_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0); + tcg_gen_or_i64(t0, t0, t1); + + tcg_gen_mov_i64(cpu_gpr[rd], t0); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2); + tcg_gen_shri_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1); + tcg_gen_shli_i64(t1, t1, 16); + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0); + tcg_gen_or_i64(t0, t0, t1); + + tcg_gen_mov_i64(cpu_mmr[rd], t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } +} + #endif =20 =20 @@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ - case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ break; @@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PCPYUD: gen_mmi_pcpyud(ctx); break; + case MMI_OPC_3_PEXCH: + gen_mmi_pexch(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI3"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4 From nobody Sun Nov 9 13:00:08 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Tue, 26 Feb 2019 07:23:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B00381A207A; Tue, 26 Feb 2019 13:23:25 +0100 (CET) Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.57]) by mail.rt-rk.com (Postfix) with ESMTPSA id 789C31A225A; Tue, 26 Feb 2019 13:23:25 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2019 13:23:17 +0100 Message-Id: <1551183797-13570-7-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551183797-13570-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Mateja Marjanovic Add emulation of MMI instruction PEXCW. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic --- target/mips/translate.c | 73 +++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 66cea86..7a13841 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx) } } =20 +/* + * PEXCW rd, rt + * + * Parallel Exchange Center Word + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---------+---------+-----------+ + * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 | + * +-----------+---------+---------+---------+---------+-----------+ + */ + +static void gen_mmi_pexcw(DisasContext *ctx) +{ + uint32_t pd, rt, rd; + uint32_t opcode; + + opcode =3D ctx->opcode; + + pd =3D extract32(opcode, 21, 5); + rt =3D extract32(opcode, 16, 5); + rd =3D extract32(opcode, 11, 5); + + if (unlikely(pd !=3D 0)) { + generate_exception_end(ctx, EXCP_RI); + } else if (rd =3D=3D 0) { + /* nop */ + } else if (rt =3D=3D 0) { + tcg_gen_movi_i64(cpu_gpr[rd], 0); + tcg_gen_movi_i64(cpu_mmr[rd], 0); + } else if (rt =3D=3D rd) { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 32) - 1; + uint64_t mask1 =3D mask0 << 32; + + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1); + tcg_gen_shri_i64(t0, t0, 32); + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0); + tcg_gen_shli_i64(t1, t1, 32); + + tcg_gen_and_i64(cpu_mmr[rd], cpu_mmr[rd], mask1); + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0); + + tcg_gen_and_i64(cpu_gpr[rd], cpu_gpr[rd], mask0); + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } else { + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + uint64_t mask0 =3D (1ULL << 32) - 1; + uint64_t mask1 =3D mask0 << 32; + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1); + tcg_gen_shri_i64(t1, t1, 32); + tcg_gen_or_i64(cpu_mmr[rd], t0, t1); + + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0); + tcg_gen_shli_i64(t0, t0, 32); + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0); + tcg_gen_or_i64(cpu_gpr[rd], t0, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } +} + #endif =20 =20 @@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ - case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ break; case MMI_OPC_3_PCPYH: @@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PEXCH: gen_mmi_pexch(ctx); break; + case MMI_OPC_3_PEXCW: + gen_mmi_pexcw(ctx); + break; default: MIPS_INVAL("TX79 MMI class MMI3"); generate_exception_end(ctx, EXCP_RI); --=20 2.7.4