From nobody Thu Oct 2 09:16:52 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1550664519168461.3994597102418; Wed, 20 Feb 2019 04:08:39 -0800 (PST) Received: from localhost ([127.0.0.1]:38951 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwQfy-0007Fw-14 for importer@patchew.org; Wed, 20 Feb 2019 07:08:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gwQeE-0006IO-A8 for qemu-devel@nongnu.org; Wed, 20 Feb 2019 07:06:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gwQeB-0001lL-Gh for qemu-devel@nongnu.org; Wed, 20 Feb 2019 07:06:46 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41652) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gwQeB-0001T8-7b for qemu-devel@nongnu.org; Wed, 20 Feb 2019 07:06:43 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1A8D6C0669A7; Wed, 20 Feb 2019 12:06:40 +0000 (UTC) Received: from thuth.com (ovpn-116-135.ams2.redhat.com [10.36.116.135]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2FDE817989; Wed, 20 Feb 2019 12:06:37 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 20 Feb 2019 13:06:29 +0100 Message-Id: <1550664389-2865-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 20 Feb 2019 12:06:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH] hw/sd/sdhci: Move PCI-related code into a separate file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some machines have an SDHCI device, but no PCI. To be able to compile hw/sd/sdhci.c without CONFIG_PCI, we must not call functions like pci_get_address_space() and pci_allocate_irq() there. Thus move the PCI-related code into a separate file. This is required for the upcoming Kconfig-like build system, e.g. it is needed if a user wants to compile a QEMU binary with just one machine that has SDHCI, but no PCI, like the ARM "raspi" machines for example. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- Note: Once we've got Kconfig in place, the "land" in the Makefile should be replaced with a proper new CONFIG_SDHCI_PCI switch instead hw/sd/Makefile.objs | 1 + hw/sd/sdhci-internal.h | 34 ++++++++++++++++++ hw/sd/sdhci-pci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++ hw/sd/sdhci.c | 98 +++-------------------------------------------= ---- 4 files changed, 127 insertions(+), 93 deletions(-) create mode 100644 hw/sd/sdhci-pci.c diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index a99d9fb..58be7b3 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -2,6 +2,7 @@ common-obj-$(CONFIG_PL181) +=3D pl181.o common-obj-$(CONFIG_SSI_SD) +=3D ssi-sd.o common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-internal.o common-obj-$(CONFIG_SDHCI) +=3D sdhci.o +common-obj-$(call land,$(CONFIG_SDHCI),$(CONFIG_PCI)) +=3D sdhci-pci.o =20 obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o obj-$(CONFIG_OMAP) +=3D omap_mmc.o diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 19665fd..3414140 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -304,4 +304,38 @@ extern const VMStateDescription sdhci_vmstate; =20 #define ESDHC_PRNSTS_SDSTB (1 << 3) =20 +/* + * Default SD/MMC host controller features information, which will be + * presented in CAPABILITIES register of generic SD host controller at res= et. + * + * support: + * - 3.3v and 1.8v voltages + * - SDMA/ADMA1/ADMA2 + * - high-speed + * max host controller R/W buffers size: 512B + * max clock frequency for SDclock: 52 MHz + * timeout clock frequency: 52 MHz + * + * does not support: + * - 3.0v voltage + * - 64-bit system bus + * - suspend/resume + */ +#define SDHC_CAPAB_REG_DEFAULT 0x057834b4 + +#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ + DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ + DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ + \ + /* Capabilities registers provide information on supported + * features of this specific host controller implementation */ \ + DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT)= , \ + DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) + +void sdhci_initfn(SDHCIState *s); +void sdhci_uninitfn(SDHCIState *s); +void sdhci_common_realize(SDHCIState *s, Error **errp); +void sdhci_common_unrealize(SDHCIState *s, Error **errp); +void sdhci_common_class_init(ObjectClass *klass, void *data); + #endif diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c new file mode 100644 index 0000000..f884661 --- /dev/null +++ b/hw/sd/sdhci-pci.c @@ -0,0 +1,87 @@ +/* + * SDHCI device on PCI + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/sd/sdhci.h" +#include "sdhci-internal.h" + +static Property sdhci_pci_properties[] =3D { + DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sdhci_pci_realize(PCIDevice *dev, Error **errp) +{ + SDHCIState *s =3D PCI_SDHCI(dev); + Error *local_err =3D NULL; + + sdhci_initfn(s); + sdhci_common_realize(s, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + dev->config[PCI_CLASS_PROG] =3D 0x01; /* Standard Host supported DMA */ + dev->config[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin A */ + s->irq =3D pci_allocate_irq(dev); + s->dma_as =3D pci_get_address_space(dev); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); +} + +static void sdhci_pci_exit(PCIDevice *dev) +{ + SDHCIState *s =3D PCI_SDHCI(dev); + + sdhci_common_unrealize(s, &error_abort); + sdhci_uninitfn(s); +} + +static void sdhci_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D sdhci_pci_realize; + k->exit =3D sdhci_pci_exit; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_SDHCI; + k->class_id =3D PCI_CLASS_SYSTEM_SDHCI; + dc->props =3D sdhci_pci_properties; + + sdhci_common_class_init(klass, data); +} + +static const TypeInfo sdhci_pci_info =3D { + .name =3D TYPE_PCI_SDHCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(SDHCIState), + .class_init =3D sdhci_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void sdhci_pci_register_type(void) +{ + type_register_static(&sdhci_pci_info); +} + +type_init(sdhci_pci_register_type) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 83f1574..17ad546 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -40,24 +40,6 @@ =20 #define MASKED_WRITE(reg, mask, val) (reg =3D (reg & (mask)) | (val)) =20 -/* Default SD/MMC host controller features information, which will be - * presented in CAPABILITIES register of generic SD host controller at res= et. - * - * support: - * - 3.3v and 1.8v voltages - * - SDMA/ADMA1/ADMA2 - * - high-speed - * max host controller R/W buffers size: 512B - * max clock frequency for SDclock: 52 MHz - * timeout clock frequency: 52 MHz - * - * does not support: - * - 3.0v voltage - * - 64-bit system bus - * - suspend/resume - */ -#define SDHC_CAPAB_REG_DEFAULT 0x057834b4 - static inline unsigned int sdhci_get_fifolen(SDHCIState *s) { return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); @@ -1328,16 +1310,7 @@ static void sdhci_init_readonly_registers(SDHCIState= *s, Error **errp) =20 /* --- qdev common --- */ =20 -#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ - DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ - DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ - \ - /* Capabilities registers provide information on supported - * features of this specific host controller implementation */ \ - DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT)= , \ - DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) - -static void sdhci_initfn(SDHCIState *s) +void sdhci_initfn(SDHCIState *s) { qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); @@ -1348,7 +1321,7 @@ static void sdhci_initfn(SDHCIState *s) s->io_ops =3D &sdhci_mmio_ops; } =20 -static void sdhci_uninitfn(SDHCIState *s) +void sdhci_uninitfn(SDHCIState *s) { timer_del(s->insert_timer); timer_free(s->insert_timer); @@ -1359,7 +1332,7 @@ static void sdhci_uninitfn(SDHCIState *s) s->fifo_buffer =3D NULL; } =20 -static void sdhci_common_realize(SDHCIState *s, Error **errp) +void sdhci_common_realize(SDHCIState *s, Error **errp) { Error *local_err =3D NULL; =20 @@ -1375,7 +1348,7 @@ static void sdhci_common_realize(SDHCIState *s, Error= **errp) SDHC_REGISTERS_MAP_SIZE); } =20 -static void sdhci_common_unrealize(SDHCIState *s, Error **errp) +void sdhci_common_unrealize(SDHCIState *s, Error **errp) { /* This function is expected to be called only once for each class: * - SysBus: via DeviceClass->unrealize(), @@ -1445,7 +1418,7 @@ const VMStateDescription sdhci_vmstate =3D { }, }; =20 -static void sdhci_common_class_init(ObjectClass *klass, void *data) +void sdhci_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 @@ -1454,66 +1427,6 @@ static void sdhci_common_class_init(ObjectClass *kla= ss, void *data) dc->reset =3D sdhci_poweron_reset; } =20 -/* --- qdev PCI --- */ - -static Property sdhci_pci_properties[] =3D { - DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), - DEFINE_PROP_END_OF_LIST(), -}; - -static void sdhci_pci_realize(PCIDevice *dev, Error **errp) -{ - SDHCIState *s =3D PCI_SDHCI(dev); - Error *local_err =3D NULL; - - sdhci_initfn(s); - sdhci_common_realize(s, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - dev->config[PCI_CLASS_PROG] =3D 0x01; /* Standard Host supported DMA */ - dev->config[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin A */ - s->irq =3D pci_allocate_irq(dev); - s->dma_as =3D pci_get_address_space(dev); - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); -} - -static void sdhci_pci_exit(PCIDevice *dev) -{ - SDHCIState *s =3D PCI_SDHCI(dev); - - sdhci_common_unrealize(s, &error_abort); - sdhci_uninitfn(s); -} - -static void sdhci_pci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); - - k->realize =3D sdhci_pci_realize; - k->exit =3D sdhci_pci_exit; - k->vendor_id =3D PCI_VENDOR_ID_REDHAT; - k->device_id =3D PCI_DEVICE_ID_REDHAT_SDHCI; - k->class_id =3D PCI_CLASS_SYSTEM_SDHCI; - dc->props =3D sdhci_pci_properties; - - sdhci_common_class_init(klass, data); -} - -static const TypeInfo sdhci_pci_info =3D { - .name =3D TYPE_PCI_SDHCI, - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(SDHCIState), - .class_init =3D sdhci_pci_class_init, - .interfaces =3D (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, -}; - /* --- qdev SysBus --- */ =20 static Property sdhci_sysbus_properties[] =3D { @@ -1846,7 +1759,6 @@ static const TypeInfo imx_usdhc_info =3D { =20 static void sdhci_register_types(void) { - type_register_static(&sdhci_pci_info); type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); type_register_static(&imx_usdhc_info); --=20 1.8.3.1