From nobody Sat Nov 8 07:42:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549997499673844.9243278942135; Tue, 12 Feb 2019 10:51:39 -0800 (PST) Received: from localhost ([127.0.0.1]:44433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd9e-0004sp-LD for importer@patchew.org; Tue, 12 Feb 2019 13:51:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcl0-0002Qj-LN for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcky-0005Kd-UH for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:10 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:49388) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtckw-0004p2-OI for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:08 -0500 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIKZZJ127937 for ; Tue, 12 Feb 2019 13:25:37 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0ns058t-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:36 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:28 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIPRQ98782120 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:27 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 41074A405C; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 22F8CA405B; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id E4D84220182; Tue, 12 Feb 2019 19:25:25 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:25 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3D2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC754 Message-Id: <154999592549.690774.13071669609040970763.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 14/15] spapr: add hotplug hooks for PHB hotplug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Hotplugging PHBs is a machine-level operation, but PHBs reside on the main system bus, so we register spapr machine as the handler for the main system bus. Provide the usual pre-plug, plug and unplug-request handlers. Move the checking of the PHB index to the pre-plug handler. It is okay to do that and assert in the realize function because the pre-plug handler is always called, even for the oldest machine types we support. Unlike with other device types, there are some cases where we cannot provide the FDT fragment of the PHB from the plug handler, eg, before KVMPPC_H_UPDATE_DT was called. Do this from a DRC callback that is called just before the first FDT fragment is exposed to the guest. Signed-off-by: Michael Roth (Fixed interrupt controller phandle in "interrupt-map" and TCE table size in "ibm,dma-window" FDT fragment, Greg Kurz) Signed-off-by: Greg Kurz --- v4: - populate FDT fragment in a DRC callback v3: - reworked phandle handling some more v2: - reworked phandle handling - sync LSIs to KVM --- --- hw/ppc/spapr.c | 121 ++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/ppc/spapr_drc.c | 2 + hw/ppc/spapr_pci.c | 16 ------ include/hw/ppc/spapr.h | 5 ++ 4 files changed, 127 insertions(+), 17 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 021758825b7e..06ce0babcb54 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2930,6 +2930,11 @@ static void spapr_machine_init(MachineState *machine) register_savevm_live(NULL, "spapr/htab", -1, 1, &savevm_htab_handlers, spapr); =20 + if (smc->dr_phb_enabled) { + qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), + &error_fatal); + } + qemu_register_boot_set(spapr_boot_set, spapr); =20 if (kvm_enabled()) { @@ -3733,6 +3738,108 @@ out: error_propagate(errp, local_err); } =20 +int spapr_dt_phb(DeviceState *dev, sPAPRMachineState *spapr, void *fdt, + int *fdt_start_offset, Error **errp) +{ + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + uint32_t intc_phandle; + + if (spapr_irq_get_phandle(spapr, spapr->fdt_blob, &intc_phandle, errp)= ) { + return -1; + } + + if (spapr_populate_pci_dt(sphb, intc_phandle, fdt, spapr->irq->nr_msis, + fdt_start_offset)) { + error_setg(errp, "unable to create FDT node for PHB %d", sphb->ind= ex); + return -1; + } + + /* generally SLOF creates these, for hotplug it's up to QEMU */ + _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); + + return 0; +} + +static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *d= ev, + Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); + + if (sphb->index =3D=3D (uint32_t)-1) { + error_setg(errp, "\"index\" for PAPR PHB is mandatory"); + return; + } + + /* + * This will check that sphb->index doesn't exceed the maximum number = of + * PHBs for the current machine type. + */ + smc->phb_placement(spapr, sphb->index, + &sphb->buid, &sphb->io_win_addr, + &sphb->mem_win_addr, &sphb->mem64_win_addr, + windows_supported, sphb->dma_liobn, errp); +} + +static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, + Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRDRConnector *drc; + bool hotplugged =3D spapr_drc_hotplugged(dev); + Error *local_err =3D NULL; + + if (!smc->dr_phb_enabled) { + return; + } + + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); + /* hotplug hooks should check it's enabled before getting this far */ + assert(drc); + + /* + * The FDT fragment will be added during the first invocation of RTAS + * ibm,client-architecture-support for this device, when we're sure + * that the IOMMU is configured and that QEMU knows the phandle of the + * interrupt controller. + */ + spapr_drc_attach(drc, DEVICE(dev), NULL, 0, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (hotplugged) { + spapr_hotplug_req_add_by_index(drc); + } else { + spapr_drc_reset(drc); + } +} + +void spapr_phb_release(DeviceState *dev) +{ + object_unparent(OBJECT(dev)); +} + +static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRDRConnector *drc; + + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); + assert(drc); + + if (!spapr_drc_unplug_requested(drc)) { + spapr_drc_detach(drc); + spapr_hotplug_req_remove_by_index(drc); + } +} + static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { @@ -3740,6 +3847,8 @@ static void spapr_machine_device_plug(HotplugHandler = *hotplug_dev, spapr_memory_plug(hotplug_dev, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { spapr_core_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + spapr_phb_plug(hotplug_dev, dev, errp); } } =20 @@ -3758,6 +3867,7 @@ static void spapr_machine_device_unplug_request(Hotpl= ugHandler *hotplug_dev, { sPAPRMachineState *sms =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); MachineClass *mc =3D MACHINE_GET_CLASS(sms); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); =20 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { @@ -3777,6 +3887,12 @@ static void spapr_machine_device_unplug_request(Hotp= lugHandler *hotplug_dev, return; } spapr_core_unplug_request(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + if (!smc->dr_phb_enabled) { + error_setg(errp, "PHB hot unplug not supported on this machine= "); + return; + } + spapr_phb_unplug_request(hotplug_dev, dev, errp); } } =20 @@ -3787,6 +3903,8 @@ static void spapr_machine_device_pre_plug(HotplugHand= ler *hotplug_dev, spapr_memory_pre_plug(hotplug_dev, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { spapr_core_pre_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + spapr_phb_pre_plug(hotplug_dev, dev, errp); } } =20 @@ -3794,7 +3912,8 @@ static HotplugHandler *spapr_get_hotplug_handler(Mach= ineState *machine, DeviceState *dev) { if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || - object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { + object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || + object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { return HOTPLUG_HANDLER(machine); } return NULL; diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index c5a281915665..22563a381a37 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -709,6 +709,8 @@ static void spapr_drc_phb_class_init(ObjectClass *k, vo= id *data) drck->typeshift =3D SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB; drck->typename =3D "PHB"; drck->drc_name_prefix =3D "PHB "; + drck->release =3D spapr_phb_release; + drck->populate_dt =3D spapr_dt_phb; } =20 static const TypeInfo spapr_dr_connector_info =3D { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7df7f6502f93..d0caca627455 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1647,21 +1647,7 @@ static void spapr_phb_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (sphb->index !=3D (uint32_t)-1) { - Error *local_err =3D NULL; - - smc->phb_placement(spapr, sphb->index, - &sphb->buid, &sphb->io_win_addr, - &sphb->mem_win_addr, &sphb->mem64_win_addr, - windows_supported, sphb->dma_liobn, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } else { - error_setg(errp, "\"index\" for PAPR PHB is mandatory"); - return; - } + assert(sphb->index !=3D (uint32_t)-1); /* checked in spapr_phb_pre_plu= g() */ =20 if (sphb->mem64_win_size !=3D 0) { if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a3074e7fea37..69d9c2196ca2 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -764,9 +764,12 @@ void spapr_reallocate_hpt(sPAPRMachineState *spapr, in= t shift, void spapr_clear_pending_events(sPAPRMachineState *spapr); int spapr_max_server_number(sPAPRMachineState *spapr); =20 -/* CPU and LMB DRC release callbacks. */ +/* DRC callbacks. */ void spapr_core_release(DeviceState *dev); void spapr_lmb_release(DeviceState *dev); +void spapr_phb_release(DeviceState *dev); +int spapr_dt_phb(DeviceState *dev, sPAPRMachineState *spapr, void *fdt, + int *fdt_start_offset, Error **errp); =20 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);