From nobody Sat Nov 8 07:38:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996249808360.6559479715605; Tue, 12 Feb 2019 10:30:49 -0800 (PST) Received: from localhost ([127.0.0.1]:44030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcpR-00061i-Ko for importer@patchew.org; Tue, 12 Feb 2019 13:30:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcjA-0000c5-UZ for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcj8-00033o-QH for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:16 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:33328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcj6-00031H-SS for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:14 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJw52064181 for ; Tue, 12 Feb 2019 13:24:11 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm2xks6u0-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:11 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:02 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIO1vw59113602 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 12 Feb 2019 18:24:01 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AD2DB52052; Tue, 12 Feb 2019 18:24:01 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 908AE5204F; Tue, 12 Feb 2019 18:24:01 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 68DF1220182; Tue, 12 Feb 2019 19:24:00 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:00 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3B6 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC737 Message-Id: <154999583999.690774.9854440646408554397.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 01/15] spapr_irq: Add an @xics_offset field to sPAPRIrq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Only pseries machines, either recent ones started with ic-mode=3Dxics or older ones using the legacy irq allocation scheme, need to set the @offset of the ICS to XICS_IRQ_BASE. Recent pseries started with ic-mode=3Ddual set it to 0 and powernv machines set it to some other value at runtime. It thus doesn't really help to set the default value of the ICS offset to XICS_IRQ_BASE in ics_base_instance_init(). Drop that code from XICS and let the pseries code set the offset explicitely for clarity. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 8 -------- hw/ppc/spapr_irq.c | 33 ++++++++++++++++++++------------- include/hw/ppc/spapr_irq.h | 1 + 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 16e8ffa2aaf7..7cac138067e2 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -638,13 +638,6 @@ static void ics_base_realize(DeviceState *dev, Error *= *errp) ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); } =20 -static void ics_base_instance_init(Object *obj) -{ - ICSState *ics =3D ICS_BASE(obj); - - ics->offset =3D XICS_IRQ_BASE; -} - static int ics_base_dispatch_pre_save(void *opaque) { ICSState *ics =3D opaque; @@ -720,7 +713,6 @@ static const TypeInfo ics_base_info =3D { .parent =3D TYPE_DEVICE, .abstract =3D true, .instance_size =3D sizeof(ICSState), - .instance_init =3D ics_base_instance_init, .class_init =3D ics_base_class_init, .class_size =3D sizeof(ICSStateClass), }; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 80b0083b8e38..8217e0215411 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -68,10 +68,11 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr) =20 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, const char *type_ics, - int nr_irqs, Error **errp) + int nr_irqs, int offset, Error **errp) { Error *local_err =3D NULL; Object *obj; + ICSState *ics; =20 obj =3D object_new(type_ics); object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); @@ -86,7 +87,10 @@ static ICSState *spapr_ics_create(sPAPRMachineState *spa= pr, goto error; } =20 - return ICS_BASE(obj); + ics =3D ICS_BASE(obj); + ics->offset =3D offset; + + return ics; =20 error: error_propagate(errp, local_err); @@ -104,6 +108,7 @@ static void spapr_irq_init_xics(sPAPRMachineState *spap= r, Error **errp) !xics_kvm_init(spapr, &local_err)) { spapr->icp_type =3D TYPE_KVM_ICP; spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, + spapr->irq->xics_offset, &local_err); } if (machine_kernel_irqchip_required(machine) && !spapr->ics) { @@ -119,6 +124,7 @@ static void spapr_irq_init_xics(sPAPRMachineState *spap= r, Error **errp) xics_spapr_init(spapr); spapr->icp_type =3D TYPE_ICP; spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, + spapr->irq->xics_offset, &local_err); } =20 @@ -246,6 +252,7 @@ sPAPRIrq spapr_irq_xics =3D { .nr_irqs =3D SPAPR_IRQ_XICS_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_NR_MSIS, .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics_offset =3D XICS_IRQ_BASE, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, @@ -451,17 +458,6 @@ static void spapr_irq_init_dual(sPAPRMachineState *spa= pr, Error **errp) return; } =20 - /* - * Align the XICS and the XIVE IRQ number space under QEMU. - * - * However, the XICS KVM device still considers that the IRQ - * numbers should start at XICS_IRQ_BASE (0x1000). Either we - * should introduce a KVM device ioctl to set the offset or ignore - * the lower 4K numbers when using the get/set ioctl of the XICS - * KVM device. The second option seems the least intrusive. - */ - spapr->ics->offset =3D 0; - spapr_irq_xive.init(spapr, &local_err); if (local_err) { error_propagate(errp, local_err); @@ -582,6 +578,16 @@ sPAPRIrq spapr_irq_dual =3D { .nr_irqs =3D SPAPR_IRQ_DUAL_NR_IRQS, .nr_msis =3D SPAPR_IRQ_DUAL_NR_MSIS, .ov5 =3D SPAPR_OV5_XIVE_BOTH, + /* + * Align the XICS and the XIVE IRQ number space under QEMU. + * + * However, the XICS KVM device still considers that the IRQ + * numbers should start at XICS_IRQ_BASE (0x1000). Either we + * should introduce a KVM device ioctl to set the offset or ignore + * the lower 4K numbers when using the get/set ioctl of the XICS + * KVM device. The second option seems the least intrusive. + */ + .xics_offset =3D 0, =20 .init =3D spapr_irq_init_dual, .claim =3D spapr_irq_claim_dual, @@ -712,6 +718,7 @@ sPAPRIrq spapr_irq_xics_legacy =3D { .nr_irqs =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics_offset =3D XICS_IRQ_BASE, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 14b02c3aca33..5e30858dc22a 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -34,6 +34,7 @@ typedef struct sPAPRIrq { uint32_t nr_irqs; uint32_t nr_msis; uint8_t ov5; + uint32_t xics_offset; =20 void (*init)(sPAPRMachineState *spapr, Error **errp); int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp= );