From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996249808360.6559479715605; Tue, 12 Feb 2019 10:30:49 -0800 (PST) Received: from localhost ([127.0.0.1]:44030 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcpR-00061i-Ko for importer@patchew.org; Tue, 12 Feb 2019 13:30:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcjA-0000c5-UZ for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcj8-00033o-QH for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:16 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:33328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcj6-00031H-SS for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:14 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJw52064181 for ; Tue, 12 Feb 2019 13:24:11 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm2xks6u0-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:11 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:02 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIO1vw59113602 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 12 Feb 2019 18:24:01 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AD2DB52052; Tue, 12 Feb 2019 18:24:01 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 908AE5204F; Tue, 12 Feb 2019 18:24:01 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 68DF1220182; Tue, 12 Feb 2019 19:24:00 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:00 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3B6 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC737 Message-Id: <154999583999.690774.9854440646408554397.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 01/15] spapr_irq: Add an @xics_offset field to sPAPRIrq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Only pseries machines, either recent ones started with ic-mode=3Dxics or older ones using the legacy irq allocation scheme, need to set the @offset of the ICS to XICS_IRQ_BASE. Recent pseries started with ic-mode=3Ddual set it to 0 and powernv machines set it to some other value at runtime. It thus doesn't really help to set the default value of the ICS offset to XICS_IRQ_BASE in ics_base_instance_init(). Drop that code from XICS and let the pseries code set the offset explicitely for clarity. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/xics.c | 8 -------- hw/ppc/spapr_irq.c | 33 ++++++++++++++++++++------------- include/hw/ppc/spapr_irq.h | 1 + 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 16e8ffa2aaf7..7cac138067e2 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -638,13 +638,6 @@ static void ics_base_realize(DeviceState *dev, Error *= *errp) ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); } =20 -static void ics_base_instance_init(Object *obj) -{ - ICSState *ics =3D ICS_BASE(obj); - - ics->offset =3D XICS_IRQ_BASE; -} - static int ics_base_dispatch_pre_save(void *opaque) { ICSState *ics =3D opaque; @@ -720,7 +713,6 @@ static const TypeInfo ics_base_info =3D { .parent =3D TYPE_DEVICE, .abstract =3D true, .instance_size =3D sizeof(ICSState), - .instance_init =3D ics_base_instance_init, .class_init =3D ics_base_class_init, .class_size =3D sizeof(ICSStateClass), }; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 80b0083b8e38..8217e0215411 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -68,10 +68,11 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr) =20 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, const char *type_ics, - int nr_irqs, Error **errp) + int nr_irqs, int offset, Error **errp) { Error *local_err =3D NULL; Object *obj; + ICSState *ics; =20 obj =3D object_new(type_ics); object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); @@ -86,7 +87,10 @@ static ICSState *spapr_ics_create(sPAPRMachineState *spa= pr, goto error; } =20 - return ICS_BASE(obj); + ics =3D ICS_BASE(obj); + ics->offset =3D offset; + + return ics; =20 error: error_propagate(errp, local_err); @@ -104,6 +108,7 @@ static void spapr_irq_init_xics(sPAPRMachineState *spap= r, Error **errp) !xics_kvm_init(spapr, &local_err)) { spapr->icp_type =3D TYPE_KVM_ICP; spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, + spapr->irq->xics_offset, &local_err); } if (machine_kernel_irqchip_required(machine) && !spapr->ics) { @@ -119,6 +124,7 @@ static void spapr_irq_init_xics(sPAPRMachineState *spap= r, Error **errp) xics_spapr_init(spapr); spapr->icp_type =3D TYPE_ICP; spapr->ics =3D spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, + spapr->irq->xics_offset, &local_err); } =20 @@ -246,6 +252,7 @@ sPAPRIrq spapr_irq_xics =3D { .nr_irqs =3D SPAPR_IRQ_XICS_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_NR_MSIS, .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics_offset =3D XICS_IRQ_BASE, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, @@ -451,17 +458,6 @@ static void spapr_irq_init_dual(sPAPRMachineState *spa= pr, Error **errp) return; } =20 - /* - * Align the XICS and the XIVE IRQ number space under QEMU. - * - * However, the XICS KVM device still considers that the IRQ - * numbers should start at XICS_IRQ_BASE (0x1000). Either we - * should introduce a KVM device ioctl to set the offset or ignore - * the lower 4K numbers when using the get/set ioctl of the XICS - * KVM device. The second option seems the least intrusive. - */ - spapr->ics->offset =3D 0; - spapr_irq_xive.init(spapr, &local_err); if (local_err) { error_propagate(errp, local_err); @@ -582,6 +578,16 @@ sPAPRIrq spapr_irq_dual =3D { .nr_irqs =3D SPAPR_IRQ_DUAL_NR_IRQS, .nr_msis =3D SPAPR_IRQ_DUAL_NR_MSIS, .ov5 =3D SPAPR_OV5_XIVE_BOTH, + /* + * Align the XICS and the XIVE IRQ number space under QEMU. + * + * However, the XICS KVM device still considers that the IRQ + * numbers should start at XICS_IRQ_BASE (0x1000). Either we + * should introduce a KVM device ioctl to set the offset or ignore + * the lower 4K numbers when using the get/set ioctl of the XICS + * KVM device. The second option seems the least intrusive. + */ + .xics_offset =3D 0, =20 .init =3D spapr_irq_init_dual, .claim =3D spapr_irq_claim_dual, @@ -712,6 +718,7 @@ sPAPRIrq spapr_irq_xics_legacy =3D { .nr_irqs =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .nr_msis =3D SPAPR_IRQ_XICS_LEGACY_NR_IRQS, .ov5 =3D SPAPR_OV5_XIVE_LEGACY, + .xics_offset =3D XICS_IRQ_BASE, =20 .init =3D spapr_irq_init_xics, .claim =3D spapr_irq_claim_xics, diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 14b02c3aca33..5e30858dc22a 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -34,6 +34,7 @@ typedef struct sPAPRIrq { uint32_t nr_irqs; uint32_t nr_msis; uint8_t ov5; + uint32_t xics_offset; =20 void (*init)(sPAPRMachineState *spapr, Error **errp); int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp= ); From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996452393609.8402245796932; Tue, 12 Feb 2019 10:34:12 -0800 (PST) Received: from localhost ([127.0.0.1]:44074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcsb-0008Uy-4M for importer@patchew.org; Tue, 12 Feb 2019 13:34:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcjR-0000qA-JD for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcjM-0003Fg-SN for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:31 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:51500 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcjC-000362-RQ for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:21 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJcCU095165 for ; Tue, 12 Feb 2019 13:24:16 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0rsyw6g-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:16 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:09 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIO8Bu66126030 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:08 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4D2EB11C054; Tue, 12 Feb 2019 18:24:08 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3559111C050; Tue, 12 Feb 2019 18:24:08 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:08 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 021F0220182; Tue, 12 Feb 2019 19:24:06 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:06 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-TM-AS-GCONF: 00 x-cbid: 19021218-0008-0000-0000-000002BFA6AA X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0009-0000-0000-0000222BC12F Message-Id: <154999584656.690774.18352404495120358613.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=946 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x1CIJcCU095165 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 02/15] xive: Only set source type for LSIs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" MSI is the default and LSI specific code is guarded by the xive_source_irq_is_lsi() helper. The xive_source_irq_set() helper is a nop for MSIs. Simplify the code by turning xive_source_irq_set() into xive_source_irq_set_lsi() and only call it for LSIs. The call to xive_source_irq_set(false) in spapr_xive_irq_free() is also a nop. Just drop it. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 7 +++---- include/hw/ppc/xive.h | 7 ++----- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index a0f5ff929447..290a290e43a5 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -489,20 +489,19 @@ bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t l= isn, bool lsi) } =20 xive->eat[lisn].w |=3D cpu_to_be64(EAS_VALID); - xive_source_irq_set(xsrc, lisn, lsi); + if (lsi) { + xive_source_irq_set_lsi(xsrc, lisn); + } return true; } =20 bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) { - XiveSource *xsrc =3D &xive->source; - if (lisn >=3D xive->nr_irqs) { return false; } =20 xive->eat[lisn].w &=3D cpu_to_be64(~EAS_VALID); - xive_source_irq_set(xsrc, lisn, false); return true; } =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index ec3bb2aae45a..13a487527b11 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -283,13 +283,10 @@ static inline bool xive_source_irq_is_lsi(XiveSource = *xsrc, uint32_t srcno) return test_bit(srcno, xsrc->lsi_map); } =20 -static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno, - bool lsi) +static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcn= o) { assert(srcno < xsrc->nr_irqs); - if (lsi) { - bitmap_set(xsrc->lsi_map, srcno, 1); - } + bitmap_set(xsrc->lsi_map, srcno, 1); } =20 void xive_source_set_irq(void *opaque, int srcno, int val); From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996021374218.22489546473696; Tue, 12 Feb 2019 10:27:01 -0800 (PST) Received: from localhost ([127.0.0.1]:43962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcll-0002bj-PZ for importer@patchew.org; Tue, 12 Feb 2019 13:26:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcjg-00014p-IL for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcja-0003VL-Rb for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:46 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:49642 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcja-0003BA-7S for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:42 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJlqP019040 for ; Tue, 12 Feb 2019 13:24:23 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2qm1rhcsyn-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:23 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:16 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOFig55115866 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:15 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0418511C058; Tue, 12 Feb 2019 18:24:15 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CDF6411C04A; Tue, 12 Feb 2019 18:24:14 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:14 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 8FC02220182; Tue, 12 Feb 2019 19:24:13 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:13 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3BC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC73B Message-Id: <154999585315.690774.7586633403635165044.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=787 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 03/15] spapr_irq: Set LSIs at interrupt controller init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The pseries machine only uses LSIs to support legacy PCI devices. Every PHB claims 4 LSIs at realize time. When using in-kernel XICS (or upcoming in-kernel XIVE), QEMU synchronizes the state of all irqs, including these LSIs, later on at machine reset. In order to support PHB hotplug, we need a way to tell KVM about the LSIs that doesn't require a machine reset. Since recent machine types allocate all these LSIs in a fixed range for the machine lifetime, identify them when initializing the interrupt controller, long before they get passed to KVM. In order to do that, first disintricate interrupt typing and allocation. Since the vast majority of interrupts are MSIs, make that the default and have only the LSI users to explicitely set the type. It is rather straight forward for XIVE. XICS needs some extra care though: allocation state and type are mixed up in the same bits of the flags field within the interrupt state. Setting the LSI bit there at init time would mean the interrupt is de facto allocated, even if no device asked for it. Introduce a bitmap to track LSIs at the ICS level. In order to keep the patch minimal, the bitmap is only used when writing the source state to KVM and when the interrupt is claimed, so that the code that checks the interrupt type through the flags stays untouched. With older pseries machine using the XICS legacy IRQ allocation scheme, all interrupt numbers come from a common pool and there's no such thing as a fixed range for LSIs. Introduce an helper so that these older machine types can continue to set the type when allocating the LSI. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 7 +------ hw/intc/xics.c | 10 ++++++++-- hw/intc/xics_kvm.c | 2 +- hw/ppc/pnv_psi.c | 3 ++- hw/ppc/spapr_events.c | 4 ++-- hw/ppc/spapr_irq.c | 42 ++++++++++++++++++++++++++++++++-------= --- hw/ppc/spapr_pci.c | 6 ++++-- hw/ppc/spapr_vio.c | 2 +- include/hw/ppc/spapr_irq.h | 5 +++-- include/hw/ppc/spapr_xive.h | 2 +- include/hw/ppc/xics.h | 4 +++- 11 files changed, 58 insertions(+), 29 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 290a290e43a5..815263ca72ab 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -480,18 +480,13 @@ static void spapr_xive_register_types(void) =20 type_init(spapr_xive_register_types) =20 -bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi) +bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn) { - XiveSource *xsrc =3D &xive->source; - if (lisn >=3D xive->nr_irqs) { return false; } =20 xive->eat[lisn].w |=3D cpu_to_be64(EAS_VALID); - if (lsi) { - xive_source_irq_set_lsi(xsrc, lisn); - } return true; } =20 diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 7cac138067e2..26e8940d7329 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -636,6 +636,7 @@ static void ics_base_realize(DeviceState *dev, Error **= errp) return; } ics->irqs =3D g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); + ics->lsi_map =3D bitmap_new(ics->nr_irqs); } =20 static int ics_base_dispatch_pre_save(void *opaque) @@ -733,12 +734,17 @@ ICPState *xics_icp_get(XICSFabric *xi, int server) return xic->icp_get(xi, server); } =20 -void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) +void ics_set_lsi(ICSState *ics, int srcno) +{ + set_bit(srcno, ics->lsi_map); +} + +void ics_claim_irq(ICSState *ics, int srcno) { assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); =20 ics->irqs[srcno].flags |=3D - lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; + test_bit(srcno, ics->lsi_map) ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IR= Q_MSI; } =20 static void xics_register_types(void) diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index dff13300504c..e63979abc7fc 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -271,7 +271,7 @@ static int ics_set_kvm_state(ICSState *ics, int version= _id) state |=3D KVM_XICS_MASKED; } =20 - if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) { + if (test_bit(i, ics->lsi_map)) { state |=3D KVM_XICS_LEVEL_SENSITIVE; if (irq->status & XICS_STATUS_ASSERTED) { state |=3D KVM_XICS_PENDING; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 8ced09506321..e6089e1035c0 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -487,7 +487,8 @@ static void pnv_psi_realize(DeviceState *dev, Error **e= rrp) } =20 for (i =3D 0; i < ics->nr_irqs; i++) { - ics_set_irq_type(ics, i, true); + ics_set_lsi(ics, i); + ics_claim_irq(ics, i); } =20 psi->qirqs =3D qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irq= s); diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index b9c7ecb9e987..559026d0981c 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -713,7 +713,7 @@ void spapr_events_init(sPAPRMachineState *spapr) epow_irq =3D spapr_irq_findone(spapr, &error_fatal); } =20 - spapr_irq_claim(spapr, epow_irq, false, &error_fatal); + spapr_irq_claim(spapr, epow_irq, &error_fatal); =20 QTAILQ_INIT(&spapr->pending_events); =20 @@ -737,7 +737,7 @@ void spapr_events_init(sPAPRMachineState *spapr) hp_irq =3D spapr_irq_findone(spapr, &error_fatal); } =20 - spapr_irq_claim(spapr, hp_irq, false, &error_fatal); + spapr_irq_claim(spapr, hp_irq, &error_fatal); =20 spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT= _PLUG, hp_irq); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 8217e0215411..3fc34d7c8a43 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -16,10 +16,13 @@ #include "hw/ppc/spapr_xive.h" #include "hw/ppc/xics.h" #include "hw/ppc/xics_spapr.h" +#include "hw/pci-host/spapr.h" #include "sysemu/kvm.h" =20 #include "trace.h" =20 +#define SPAPR_IRQ_PCI_LSI_NR (SPAPR_MAX_PHBS * PCI_NUM_PINS) + void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis) { spapr->irq_map_nr =3D nr_msis; @@ -102,6 +105,7 @@ static void spapr_irq_init_xics(sPAPRMachineState *spap= r, Error **errp) MachineState *machine =3D MACHINE(spapr); int nr_irqs =3D spapr->irq->nr_irqs; Error *local_err =3D NULL; + int i; =20 if (kvm_enabled()) { if (machine_kernel_irqchip_allowed(machine) && @@ -128,6 +132,14 @@ static void spapr_irq_init_xics(sPAPRMachineState *spa= pr, Error **errp) &local_err); } =20 + /* Identify the PCI LSIs */ + if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { + for (i =3D 0; i < SPAPR_IRQ_PCI_LSI_NR; ++i) { + ics_set_lsi(spapr->ics, + i + SPAPR_IRQ_PCI_LSI - spapr->irq->xics_offset); + } + } + error: error_propagate(errp, local_err); } @@ -135,7 +147,7 @@ error: #define ICS_IRQ_FREE(ics, srcno) \ (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) =20 -static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool ls= i, +static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, Error **errp) { ICSState *ics =3D spapr->ics; @@ -152,7 +164,7 @@ static int spapr_irq_claim_xics(sPAPRMachineState *spap= r, int irq, bool lsi, return -1; } =20 - ics_set_irq_type(ics, irq - ics->offset, lsi); + ics_claim_irq(ics, irq - ics->offset); return 0; } =20 @@ -296,16 +308,21 @@ static void spapr_irq_init_xive(sPAPRMachineState *sp= apr, Error **errp) =20 /* Enable the CPU IPIs */ for (i =3D 0; i < nr_servers; ++i) { - spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false); + spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i); + } + + /* Identify the PCI LSIs */ + for (i =3D 0; i < SPAPR_IRQ_PCI_LSI_NR; ++i) { + xive_source_irq_set_lsi(&spapr->xive->source, SPAPR_IRQ_PCI_LSI + = i); } =20 spapr_xive_hcall_init(spapr); } =20 -static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool ls= i, +static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, Error **errp) { - if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) { + if (!spapr_xive_irq_claim(spapr->xive, irq)) { error_setg(errp, "IRQ %d is invalid", irq); return -1; } @@ -465,19 +482,19 @@ static void spapr_irq_init_dual(sPAPRMachineState *sp= apr, Error **errp) } } =20 -static int spapr_irq_claim_dual(sPAPRMachineState *spapr, int irq, bool ls= i, +static int spapr_irq_claim_dual(sPAPRMachineState *spapr, int irq, Error **errp) { Error *local_err =3D NULL; int ret; =20 - ret =3D spapr_irq_xics.claim(spapr, irq, lsi, &local_err); + ret =3D spapr_irq_xics.claim(spapr, irq, &local_err); if (local_err) { error_propagate(errp, local_err); return ret; } =20 - ret =3D spapr_irq_xive.claim(spapr, irq, lsi, &local_err); + ret =3D spapr_irq_xive.claim(spapr, irq, &local_err); if (local_err) { error_propagate(errp, local_err); return ret; @@ -630,9 +647,9 @@ void spapr_irq_init(sPAPRMachineState *spapr, Error **e= rrp) spapr->irq->nr_irqs); } =20 -int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp) +int spapr_irq_claim(sPAPRMachineState *spapr, int irq, Error **errp) { - return spapr->irq->claim(spapr, irq, lsi, errp); + return spapr->irq->claim(spapr, irq, errp); } =20 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) @@ -712,6 +729,11 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, = bool align, Error **errp) return first + ics->offset; } =20 +void spapr_irq_set_lsi_legacy(sPAPRMachineState *spapr, int irq) +{ + ics_set_lsi(spapr->ics, irq - spapr->irq->xics_offset); +} + #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS 0x400 =20 sPAPRIrq spapr_irq_xics_legacy =3D { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index c3fb0ac884b0..d68595531d5a 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -391,7 +391,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRM= achineState *spapr, } =20 for (i =3D 0; i < req_num; i++) { - spapr_irq_claim(spapr, irq + i, false, &err); + spapr_irq_claim(spapr, irq + i, &err); if (err) { if (i) { spapr_irq_free(spapr, irq, i); @@ -1742,9 +1742,11 @@ static void spapr_phb_realize(DeviceState *dev, Erro= r **errp) "can't allocate LSIs: "); return; } + + spapr_irq_set_lsi_legacy(spapr, irq); } =20 - spapr_irq_claim(spapr, irq, true, &local_err); + spapr_irq_claim(spapr, irq, &local_err); if (local_err) { error_propagate_prepend(errp, local_err, "can't allocate LSIs:= "); return; diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index 2b7e7ecac57f..b1beefc24be5 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -512,7 +512,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev,= Error **errp) } } =20 - spapr_irq_claim(spapr, dev->irq, false, &local_err); + spapr_irq_claim(spapr, dev->irq, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 5e30858dc22a..0e6c65d55430 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -37,7 +37,7 @@ typedef struct sPAPRIrq { uint32_t xics_offset; =20 void (*init)(sPAPRMachineState *spapr, Error **errp); - int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp= ); + int (*claim)(sPAPRMachineState *spapr, int irq, Error **errp); void (*free)(sPAPRMachineState *spapr, int irq, int num); qemu_irq (*qirq)(sPAPRMachineState *spapr, int irq); void (*print_info)(sPAPRMachineState *spapr, Monitor *mon); @@ -56,7 +56,7 @@ extern sPAPRIrq spapr_irq_xive; extern sPAPRIrq spapr_irq_dual; =20 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp); -int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **e= rrp); +int spapr_irq_claim(sPAPRMachineState *spapr, int irq, Error **errp); void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id); @@ -67,5 +67,6 @@ void spapr_irq_reset(sPAPRMachineState *spapr, Error **er= rp); */ int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **= errp); #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, err= p) +void spapr_irq_set_lsi_legacy(sPAPRMachineState *spapr, int irq); =20 #endif diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 9bec9192e4a0..885ca169cb29 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -37,7 +37,7 @@ typedef struct sPAPRXive { MemoryRegion tm_mmio; } sPAPRXive; =20 -bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi); +bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn); bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn); void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon); =20 diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index fad786e8b22d..18b083fe2aec 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -133,6 +133,7 @@ struct ICSState { uint32_t offset; ICSIRQState *irqs; XICSFabric *xics; + unsigned long *lsi_map; }; =20 #define ICS_PROP_XICS "xics" @@ -193,7 +194,8 @@ void ics_simple_write_xive(ICSState *ics, int nr, int s= erver, void ics_simple_set_irq(void *opaque, int srcno, int val); void ics_kvm_set_irq(void *opaque, int srcno, int val); =20 -void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); +void ics_set_lsi(ICSState *ics, int srcno); +void ics_claim_irq(ICSState *ics, int srcno); void icp_pic_print_info(ICPState *icp, Monitor *mon); void ics_pic_print_info(ICSState *ics, Monitor *mon); =20 From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:22 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOL6165929450 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:21 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 868534C04E; Tue, 12 Feb 2019 18:24:21 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6773D4C040; Tue, 12 Feb 2019 18:24:21 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:21 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 33A47220182; Tue, 12 Feb 2019 19:24:20 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:19 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-TM-AS-GCONF: 00 x-cbid: 19021218-0028-0000-0000-00000347C2F3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0029-0000-0000-00002405E3FC Message-Id: <154999585977.690774.12822496774363025882.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x1CIJRG5090049 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 04/15] spapr: Expose the name of the interrupt controller node X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This will be needed by PHB hotplug in order to access the "phandle" property of the interrupt controller node. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Greg Kurz Reviewed-by: David Gibson --- v4: - folded some changes from patches 15, 16 and 17 of v3 - dropped useless helpers --- hw/intc/spapr_xive.c | 9 ++++----- hw/intc/xics_spapr.c | 2 +- hw/ppc/spapr_irq.c | 21 ++++++++++++++++++++- include/hw/ppc/spapr_irq.h | 1 + include/hw/ppc/spapr_xive.h | 3 +++ include/hw/ppc/xics_spapr.h | 2 ++ 6 files changed, 31 insertions(+), 7 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 815263ca72ab..f14e436ad4b9 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -317,6 +317,9 @@ static void spapr_xive_realize(DeviceState *dev, Error = **errp) /* Map all regions */ spapr_xive_map_mmio(xive); =20 + xive->nodename =3D g_strdup_printf("interrupt-controller@%" PRIx64, + xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SH= IFT)); + qemu_register_reset(spapr_xive_reset, dev); } =20 @@ -1443,7 +1446,6 @@ void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t= nr_servers, void *fdt, cpu_to_be32(7), /* start */ cpu_to_be32(0xf8), /* count */ }; - gchar *nodename; =20 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */ timas[0] =3D cpu_to_be64(xive->tm_base + @@ -1453,10 +1455,7 @@ void spapr_dt_xive(sPAPRMachineState *spapr, uint32_= t nr_servers, void *fdt, XIVE_TM_OS_PAGE * (1ull << TM_SHIFT)); timas[3] =3D cpu_to_be64(1ull << TM_SHIFT); =20 - nodename =3D g_strdup_printf("interrupt-controller@%" PRIx64, - xive->tm_base + XIVE_TM_USER_PAGE * (1 << TM_SH= IFT)); - _FDT(node =3D fdt_add_subnode(fdt, 0, nodename)); - g_free(nodename); + _FDT(node =3D fdt_add_subnode(fdt, 0, xive->nodename)); =20 _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe")); _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas))); diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index e2d8b3818336..53bda6661b2a 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -254,7 +254,7 @@ void spapr_dt_xics(sPAPRMachineState *spapr, uint32_t n= r_servers, void *fdt, }; int node; =20 - _FDT(node =3D fdt_add_subnode(fdt, 0, "interrupt-controller")); + _FDT(node =3D fdt_add_subnode(fdt, 0, XICS_NODENAME)); =20 _FDT(fdt_setprop_string(fdt, node, "device_type", "PowerPC-External-Interrupt-Presentation")); diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 3fc34d7c8a43..b8d725e251ba 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -256,6 +256,11 @@ static void spapr_irq_reset_xics(sPAPRMachineState *sp= apr, Error **errp) /* TODO: create the KVM XICS device */ } =20 +static const char *spapr_irq_get_nodename_xics(sPAPRMachineState *spapr) +{ + return XICS_NODENAME; +} + #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 #define SPAPR_IRQ_XICS_NR_MSIS \ (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI) @@ -276,6 +281,7 @@ sPAPRIrq spapr_irq_xics =3D { .post_load =3D spapr_irq_post_load_xics, .reset =3D spapr_irq_reset_xics, .set_irq =3D spapr_irq_set_irq_xics, + .get_nodename =3D spapr_irq_get_nodename_xics, }; =20 /* @@ -415,6 +421,11 @@ static void spapr_irq_set_irq_xive(void *opaque, int s= rcno, int val) xive_source_set_irq(&spapr->xive->source, srcno, val); } =20 +static const char *spapr_irq_get_nodename_xive(sPAPRMachineState *spapr) +{ + return spapr->xive->nodename; +} + /* * XIVE uses the full IRQ number space. Set it to 8K to be compatible * with XICS. @@ -438,6 +449,7 @@ sPAPRIrq spapr_irq_xive =3D { .post_load =3D spapr_irq_post_load_xive, .reset =3D spapr_irq_reset_xive, .set_irq =3D spapr_irq_set_irq_xive, + .get_nodename =3D spapr_irq_get_nodename_xive, }; =20 /* @@ -585,6 +597,11 @@ static void spapr_irq_set_irq_dual(void *opaque, int s= rcno, int val) spapr_irq_current(spapr)->set_irq(spapr, srcno, val); } =20 +static const char *spapr_irq_get_nodename_dual(sPAPRMachineState *spapr) +{ + return spapr_irq_current(spapr)->get_nodename(spapr); +} + /* * Define values in sync with the XIVE and XICS backend */ @@ -615,7 +632,8 @@ sPAPRIrq spapr_irq_dual =3D { .cpu_intc_create =3D spapr_irq_cpu_intc_create_dual, .post_load =3D spapr_irq_post_load_dual, .reset =3D spapr_irq_reset_dual, - .set_irq =3D spapr_irq_set_irq_dual + .set_irq =3D spapr_irq_set_irq_dual, + .get_nodename =3D spapr_irq_get_nodename_dual, }; =20 /* @@ -751,4 +769,5 @@ sPAPRIrq spapr_irq_xics_legacy =3D { .cpu_intc_create =3D spapr_irq_cpu_intc_create_xics, .post_load =3D spapr_irq_post_load_xics, .set_irq =3D spapr_irq_set_irq_xics, + .get_nodename =3D spapr_irq_get_nodename_xics, }; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 0e6c65d55430..ad7127355441 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -48,6 +48,7 @@ typedef struct sPAPRIrq { int (*post_load)(sPAPRMachineState *spapr, int version_id); void (*reset)(sPAPRMachineState *spapr, Error **errp); void (*set_irq)(void *opaque, int srcno, int val); + const char *(*get_nodename)(sPAPRMachineState *spapr); } sPAPRIrq; =20 extern sPAPRIrq spapr_irq_xics; diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 885ca169cb29..2c57a59a3f5b 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -26,6 +26,9 @@ typedef struct sPAPRXive { XiveENDSource end_source; hwaddr end_base; =20 + /* DT */ + gchar *nodename; + /* Routing table */ XiveEAS *eat; uint32_t nr_irqs; diff --git a/include/hw/ppc/xics_spapr.h b/include/hw/ppc/xics_spapr.h index b1ab27d022cf..b8d924baf437 100644 --- a/include/hw/ppc/xics_spapr.h +++ b/include/hw/ppc/xics_spapr.h @@ -29,6 +29,8 @@ =20 #include "hw/ppc/spapr.h" =20 +#define XICS_NODENAME "interrupt-controller" + void spapr_dt_xics(sPAPRMachineState *spapr, uint32_t nr_servers, void *fd= t, uint32_t phandle); int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996928327624.3934948765565; Tue, 12 Feb 2019 10:42:08 -0800 (PST) Received: from localhost ([127.0.0.1]:44229 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd0P-0005yv-9e for importer@patchew.org; Tue, 12 Feb 2019 13:42:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcji-00016G-Hl for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcjg-0003an-Jm for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:50 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:36096) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcjc-0003R2-Rg for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:46 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJwe8064153 for ; Tue, 12 Feb 2019 13:24:38 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm2xks7b4-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:38 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:29 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOSrl8913344 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:28 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 15A5442041; Tue, 12 Feb 2019 18:24:28 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2CC24203F; Tue, 12 Feb 2019 18:24:27 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:27 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C1F1F220182; Tue, 12 Feb 2019 19:24:26 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:26 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-TM-AS-GCONF: 00 x-cbid: 19021218-0012-0000-0000-000002F4E970 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0013-0000-0000-0000212C5FA8 Message-Id: <154999586635.690774.6503848986369114097.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=732 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x1CIJwe8064153 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 05/15] spapr_irq: Expose the phandle of the interrupt controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This will be used by PHB hotplug in order to create the "interrupt-map" property of the PHB node. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Greg Kurz --- v4: - return phandle via a pointer --- hw/ppc/spapr_irq.c | 26 ++++++++++++++++++++++++++ include/hw/ppc/spapr_irq.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index b8d725e251ba..31495033c37c 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -692,6 +692,32 @@ void spapr_irq_reset(sPAPRMachineState *spapr, Error *= *errp) } } =20 +int spapr_irq_get_phandle(sPAPRMachineState *spapr, void *fdt, + uint32_t *phandle, Error **errp) +{ + const char *nodename =3D spapr->irq->get_nodename(spapr); + int offset, ph; + + offset =3D fdt_subnode_offset(fdt, 0, nodename); + if (offset < 0) { + error_setg(errp, "Can't find node \"%s\": %s", nodename, + fdt_strerror(offset)); + return -1; + } + + ph =3D fdt_get_phandle(fdt, offset); + if (!ph) { + error_setg(errp, "Can't get phandle of node \"%s\"", nodename); + return -1; + } + + if (phandle) { + *phandle =3D ph; + } + + return 0; +} + /* * XICS legacy routines - to deprecate one day */ diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index ad7127355441..4b3303ef4f6a 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -62,6 +62,8 @@ void spapr_irq_free(sPAPRMachineState *spapr, int irq, in= t num); qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id); void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp); +int spapr_irq_get_phandle(sPAPRMachineState *spapr, void *fdt, + uint32_t *phandle, Error **errp); =20 /* * XICS legacy routines From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996513097151.02075690383242; Tue, 12 Feb 2019 10:35:13 -0800 (PST) Received: from localhost ([127.0.0.1]:44088 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtctc-0000l5-CU for importer@patchew.org; Tue, 12 Feb 2019 13:35:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcjq-0001GM-QG for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcjl-0003iK-4w for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:58 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:51546 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcjk-0003WH-OX for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:24:52 -0500 Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CILG6Q054597 for ; Tue, 12 Feb 2019 13:24:43 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2qm3bf83dg-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:43 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:35 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOYrg59113648 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:34 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7559AE045; Tue, 12 Feb 2019 18:24:34 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A119AE055; Tue, 12 Feb 2019 18:24:34 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:34 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 5B151220182; Tue, 12 Feb 2019 19:24:33 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:33 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0012-0000-0000-000002F4E972 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0013-0000-0000-0000212C5FAA Message-Id: <154999587292.690774.16487295114126456879.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 06/15] spapr_pci: add PHB unrealize X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" To support PHB hotplug we need to clean up lingering references, memory, child properties, etc. prior to the PHB object being finalized. Generally this will be called as a result of calling object_unparent() on the PHB object, which in turn would normally be called as the result of an unplug() operation. When the PHB is finalized, child objects will be unparented in turn, and finalized if the PHB was the only reference holder. so we don't bother to explicitly unparent child objects of the PHB (spapr_iommu, spapr_drc, etc). The formula that gives the number of DMA windows is moved to an inline function in the hw/pci-host/spapr.h header because it will have other users. The unrealize function is able to cope with partially realized PHBs. It is hence used to implement proper rollback on the realize error path. Signed-off-by: Michael Roth Signed-off-by: Greg Kurz Reviewed-by: David Gibson --- v4: - reverted to v2 v3: - don't free LSIs at unrealize v2: - implement rollback with unrealize function --- hw/ppc/spapr_pci.c | 75 +++++++++++++++++++++++++++++++++++++++= ++-- include/hw/pci-host/spapr.h | 5 +++ 2 files changed, 76 insertions(+), 4 deletions(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index d68595531d5a..e3781dd110b2 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1565,6 +1565,64 @@ static void spapr_pci_unplug_request(HotplugHandler = *plug_handler, } } =20 +static void spapr_phb_finalizefn(Object *obj) +{ + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(obj); + + g_free(sphb->dtbusname); + sphb->dtbusname =3D NULL; +} + +static void spapr_phb_unrealize(DeviceState *dev, Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + PCIHostState *phb =3D PCI_HOST_BRIDGE(s); + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(phb); + sPAPRTCETable *tcet; + int i; + const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); + + if (sphb->msi) { + g_hash_table_unref(sphb->msi); + sphb->msi =3D NULL; + } + + /* + * Remove IO/MMIO subregions and aliases, rest should get cleaned + * via PHB's unrealize->object_finalize + */ + for (i =3D windows_supported - 1; i >=3D 0; i--) { + tcet =3D spapr_tce_find_by_liobn(sphb->dma_liobn[i]); + if (tcet) { + memory_region_del_subregion(&sphb->iommu_root, + spapr_tce_get_iommu(tcet)); + } + } + + for (i =3D PCI_NUM_PINS - 1; i >=3D 0; i--) { + if (sphb->lsi_table[i].irq) { + spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); + sphb->lsi_table[i].irq =3D 0; + } + } + + QLIST_REMOVE(sphb, list); + + memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); + + address_space_destroy(&sphb->iommu_as); + + qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); + pci_unregister_root_bus(phb->bus); + + memory_region_del_subregion(get_system_memory(), &sphb->iowindow); + if (sphb->mem64_win_pciaddr !=3D (hwaddr)-1) { + memory_region_del_subregion(get_system_memory(), &sphb->mem64windo= w); + } + memory_region_del_subregion(get_system_memory(), &sphb->mem32window); +} + static void spapr_phb_realize(DeviceState *dev, Error **errp) { /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user @@ -1582,8 +1640,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) PCIBus *bus; uint64_t msi_window_size =3D 4096; sPAPRTCETable *tcet; - const unsigned windows_supported =3D - sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; + const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); =20 if (!spapr) { error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries mach= ine"); @@ -1740,6 +1797,10 @@ static void spapr_phb_realize(DeviceState *dev, Erro= r **errp) if (local_err) { error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); + /* + * Older machines will never support PHB hotplug, ie, this= is an + * init only path and QEMU will terminate. No need to roll= back. + */ return; } =20 @@ -1749,7 +1810,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) spapr_irq_claim(spapr, irq, &local_err); if (local_err) { error_propagate_prepend(errp, local_err, "can't allocate LSIs:= "); - return; + goto unrealize; } =20 sphb->lsi_table[i].irq =3D irq; @@ -1769,13 +1830,17 @@ static void spapr_phb_realize(DeviceState *dev, Err= or **errp) if (!tcet) { error_setg(errp, "Creating window#%d failed for %s", i, sphb->dtbusname); - return; + goto unrealize; } memory_region_add_subregion(&sphb->iommu_root, 0, spapr_tce_get_iommu(tcet)); } =20 sphb->msi =3D g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g= _free); + return; + +unrealize: + spapr_phb_unrealize(dev, NULL); } =20 static int spapr_phb_children_reset(Object *child, void *opaque) @@ -1974,6 +2039,7 @@ static void spapr_phb_class_init(ObjectClass *klass, = void *data) =20 hc->root_bus_path =3D spapr_phb_root_bus_path; dc->realize =3D spapr_phb_realize; + dc->unrealize =3D spapr_phb_unrealize; dc->props =3D spapr_phb_properties; dc->reset =3D spapr_phb_reset; dc->vmsd =3D &vmstate_spapr_pci; @@ -1989,6 +2055,7 @@ static const TypeInfo spapr_phb_info =3D { .name =3D TYPE_SPAPR_PCI_HOST_BRIDGE, .parent =3D TYPE_PCI_HOST_BRIDGE, .instance_size =3D sizeof(sPAPRPHBState), + .instance_finalize =3D spapr_phb_finalizefn, .class_init =3D spapr_phb_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 51d81c4b7ce8..7cfce54a9449 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -163,4 +163,9 @@ static inline void spapr_phb_vfio_reset(DeviceState *qd= ev) =20 void spapr_phb_dma_reset(sPAPRPHBState *sphb); =20 +static inline unsigned spapr_phb_windows_supported(sPAPRPHBState *sphb) +{ + return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1; +} + #endif /* PCI_HOST_SPAPR_H */ From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996671388946.5206998521221; Tue, 12 Feb 2019 10:37:51 -0800 (PST) Received: from localhost ([127.0.0.1]:44149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcwB-0002ju-9R for importer@patchew.org; Tue, 12 Feb 2019 13:37:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtck0-0001P7-7g for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcjy-0004Gg-As for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:07 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:48092) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcjw-0003cG-BX for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:06 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJp8F136922 for ; Tue, 12 Feb 2019 13:24:49 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0m78bka-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:24:49 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:42 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOfUp57868292 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:41 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3D5F2AE051; Tue, 12 Feb 2019 18:24:41 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 21B08AE04D; Tue, 12 Feb 2019 18:24:41 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:41 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id E4E41220182; Tue, 12 Feb 2019 19:24:39 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:39 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-4275-0000-0000-0000030EAC61 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-4276-0000-0000-0000381CC2C7 Message-Id: <154999587949.690774.5181981860272429438.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 07/15] spapr: create DR connectors for PHBs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: Greg Kurz --- hw/ppc/spapr.c | 13 +++++++++++++ hw/ppc/spapr_drc.c | 17 +++++++++++++++++ include/hw/ppc/spapr.h | 1 + include/hw/ppc/spapr_drc.h | 8 ++++++++ 4 files changed, 39 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 850cfe28c414..590c67805e52 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2796,6 +2796,19 @@ static void spapr_machine_init(MachineState *machine) /* We always have at least the nvram device on VIO */ spapr_create_nvram(spapr); =20 + /* + * Setup hotplug / dynamic-reconfiguration connectors. top-level + * connectors (described in root DT node's "ibm,drc-types" property) + * are pre-initialized here. additional child connectors (such as + * connectors for a PHBs PCI slots) are added as needed during their + * parent's realization. + */ + if (smc->dr_phb_enabled) { + for (i =3D 0; i < SPAPR_MAX_PHBS; i++) { + spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); + } + } + /* Set up PCI */ spapr_pci_rtas_init(); =20 diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 2edb7d1e9c8c..189ee681062a 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -696,6 +696,15 @@ static void spapr_drc_lmb_class_init(ObjectClass *k, v= oid *data) drck->release =3D spapr_lmb_release; } =20 +static void spapr_drc_phb_class_init(ObjectClass *k, void *data) +{ + sPAPRDRConnectorClass *drck =3D SPAPR_DR_CONNECTOR_CLASS(k); + + drck->typeshift =3D SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB; + drck->typename =3D "PHB"; + drck->drc_name_prefix =3D "PHB "; +} + static const TypeInfo spapr_dr_connector_info =3D { .name =3D TYPE_SPAPR_DR_CONNECTOR, .parent =3D TYPE_DEVICE, @@ -739,6 +748,13 @@ static const TypeInfo spapr_drc_lmb_info =3D { .class_init =3D spapr_drc_lmb_class_init, }; =20 +static const TypeInfo spapr_drc_phb_info =3D { + .name =3D TYPE_SPAPR_DRC_PHB, + .parent =3D TYPE_SPAPR_DRC_LOGICAL, + .instance_size =3D sizeof(sPAPRDRConnector), + .class_init =3D spapr_drc_phb_class_init, +}; + /* helper functions for external users */ =20 sPAPRDRConnector *spapr_drc_by_index(uint32_t index) @@ -1189,6 +1205,7 @@ static void spapr_drc_register_types(void) type_register_static(&spapr_drc_cpu_info); type_register_static(&spapr_drc_pci_info); type_register_static(&spapr_drc_lmb_info); + type_register_static(&spapr_drc_phb_info); =20 spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator", rtas_set_indicator); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index cbd276ed2b6a..a3074e7fea37 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -104,6 +104,7 @@ struct sPAPRMachineClass { =20 /*< public >*/ bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs = */ + bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs = */ bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ bool pre_2_10_has_unused_icps; diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h index f6ff32e7e2f2..56bba36ad4da 100644 --- a/include/hw/ppc/spapr_drc.h +++ b/include/hw/ppc/spapr_drc.h @@ -70,6 +70,14 @@ #define SPAPR_DRC_LMB(obj) OBJECT_CHECK(sPAPRDRConnector, (obj), \ TYPE_SPAPR_DRC_LMB) =20 +#define TYPE_SPAPR_DRC_PHB "spapr-drc-phb" +#define SPAPR_DRC_PHB_GET_CLASS(obj) \ + OBJECT_GET_CLASS(sPAPRDRConnectorClass, obj, TYPE_SPAPR_DRC_PHB) +#define SPAPR_DRC_PHB_CLASS(klass) \ + OBJECT_CLASS_CHECK(sPAPRDRConnectorClass, klass, TYPE_SPAPR_DRC_PH= B) +#define SPAPR_DRC_PHB(obj) OBJECT_CHECK(sPAPRDRConnector, (obj), \ + TYPE_SPAPR_DRC_PHB) + /* * Various hotplug types managed by sPAPRDRConnector * From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:48 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOl266291812 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:47 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B691C52051; Tue, 12 Feb 2019 18:24:47 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id A20605204F; Tue, 12 Feb 2019 18:24:47 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 7C53D220182; Tue, 12 Feb 2019 19:24:46 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:46 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0012-0000-0000-000002F4E976 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0013-0000-0000-0000212C5FAC Message-Id: <154999588607.690774.16985912319318117218.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 08/15] spapr: populate PHB DRC entries for root DT node X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Nathan Fontenot This add entries to the root OF node to advertise our PHBs as being DR-capable in accordance with PAPR specification. Signed-off-by: Nathan Fontenot Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: Greg Kurz --- hw/ppc/spapr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 590c67805e52..03183c52f57b 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1348,6 +1348,14 @@ static void *spapr_build_fdt(sPAPRMachineState *spap= r) exit(1); } =20 + if (smc->dr_phb_enabled) { + ret =3D spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYP= E_PHB); + if (ret < 0) { + error_report("Couldn't set up PHB DR device tree properties"); + exit(1); + } + } + return fdt; } =20 From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996699814906.6537551246004; Tue, 12 Feb 2019 10:38:19 -0800 (PST) Received: from localhost ([127.0.0.1]:44153 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcwi-00036z-Qq for importer@patchew.org; Tue, 12 Feb 2019 13:38:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38836) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtck2-0001RI-4U for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtck0-0004IU-6e for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:10 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:54976 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtcjy-0004CC-5x for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:06 -0500 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJSGE084762 for ; Tue, 12 Feb 2019 13:25:02 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0b-001b2d01.pphosted.com with ESMTP id 2qm1y44595-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:01 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:24:55 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIOsr57864596 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:24:54 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A50F4C040; Tue, 12 Feb 2019 18:24:54 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 43C5D4C04A; Tue, 12 Feb 2019 18:24:54 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:24:54 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 138D0220182; Tue, 12 Feb 2019 19:24:53 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:52 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3C2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC745 Message-Id: <154999589263.690774.17038884580100888729.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 09/15] spapr_events: add support for phb hotplug events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth Extend the existing EPOW event format we use for PCI devices to emit PHB plug/unplug events. Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: Greg Kurz --- hw/ppc/spapr_events.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 559026d0981c..6d5a925d03cb 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -526,6 +526,9 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint= 8_t hp_action, case SPAPR_DR_CONNECTOR_TYPE_CPU: hp->hotplug_type =3D RTAS_LOG_V6_HP_TYPE_CPU; break; + case SPAPR_DR_CONNECTOR_TYPE_PHB: + hp->hotplug_type =3D RTAS_LOG_V6_HP_TYPE_PHB; + break; default: /* we shouldn't be signaling hotplug events for resources * that don't support them From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549996854139576.3333325705695; Tue, 12 Feb 2019 10:40:54 -0800 (PST) Received: from localhost ([127.0.0.1]:44212 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcz9-00050K-Km for importer@patchew.org; Tue, 12 Feb 2019 13:40:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38931) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtck6-0001a7-QT for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtck5-0004OY-1Z for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:14 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:52448 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtck4-0004Ng-RI for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:12 -0500 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJZBO100858 for ; Tue, 12 Feb 2019 13:25:12 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2qm14tetqt-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:12 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 12 Feb 2019 18:25:06 -0000 Received: from b06cxnps3075.portsmouth.uk.ibm.com (9.149.109.195) by e06smtp05.uk.ibm.com (192.168.101.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:02 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIP1uA57802980 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:01 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F065D11C052; Tue, 12 Feb 2019 18:25:00 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF64C11C050; Tue, 12 Feb 2019 18:25:00 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:00 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id A03A8220182; Tue, 12 Feb 2019 19:24:59 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:24:59 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0020-0000-0000-00000315FD81 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0021-0000-0000-000021671E4A Message-Id: <154999589921.690774.3640149277362188566.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=753 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 10/15] qdev: pass an Object * to qbus_set_hotplug_handler() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth Certain devices types, like memory/CPU, are now being handled using a hotplug interface provided by a top-level MachineClass. Hotpluggable host bridges are another such device where it makes sense to use a machine-level hotplug handler. However, unlike those devices, host-bridges have a parent bus (the main system bus), and devices with a parent bus use a different mechanism for registering their hotplug handlers: qbus_set_hotplug_handler(). This interface currently expects a handler to be a subclass of DeviceClass, but this is not the case for MachineClass, which derives directly from ObjectClass. Internally, the interface only requires an ObjectClass, so expose that in qbus_set_hotplug_handler(). Cc: Michael S. Tsirkin Cc: Eduardo Habkost Signed-off-by: Michael Roth Signed-off-by: Greg Kurz Reviewed-by: David Gibson Reviewed-by: Cornelia Huck Acked-by: Halil Pasic Reviewed-by: Michael S. Tsirkin --- hw/acpi/pcihp.c | 2 +- hw/acpi/piix4.c | 2 +- hw/char/virtio-serial-bus.c | 2 +- hw/core/bus.c | 11 ++--------- hw/pci/pcie.c | 2 +- hw/pci/shpc.c | 2 +- hw/ppc/spapr_pci.c | 2 +- hw/s390x/css-bridge.c | 2 +- hw/s390x/s390-pci-bus.c | 6 +++--- hw/scsi/virtio-scsi.c | 2 +- hw/scsi/vmw_pvscsi.c | 2 +- hw/usb/dev-smartcard-reader.c | 2 +- include/hw/qdev-core.h | 3 +-- 13 files changed, 16 insertions(+), 24 deletions(-) diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 7bc7a723407b..942918132376 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -251,7 +251,7 @@ void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_= dev, AcpiPciHpState *s, object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { PCIBus *sec =3D pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); =20 - qbus_set_hotplug_handler(BUS(sec), DEVICE(hotplug_dev), + qbus_set_hotplug_handler(BUS(sec), OBJECT(hotplug_dev), &error_abort); /* We don't have to overwrite any other hotplug handler yet */ assert(QLIST_EMPTY(&sec->child)); diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 88f9a9ec0912..df8c0db909ce 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -536,7 +536,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **er= rp) =20 piix4_acpi_system_hot_add_init(pci_address_space_io(dev), pci_get_bus(dev), s); - qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), DEVICE(s), &error_abor= t); + qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abor= t); =20 piix4_pm_add_propeties(s); } diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index d76351d7487d..bdd917bbb83c 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -1052,7 +1052,7 @@ static void virtio_serial_device_realize(DeviceState = *dev, Error **errp) /* Spawn a new virtio-serial bus on which the ports will ride as devic= es */ qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_= BUS, dev, vdev->bus_name); - qbus_set_hotplug_handler(BUS(&vser->bus), DEVICE(vser), errp); + qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser), errp); vser->bus.vser =3D vser; QTAILQ_INIT(&vser->ports); =20 diff --git a/hw/core/bus.c b/hw/core/bus.c index 4651f244864c..e09843f6abea 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -22,22 +22,15 @@ #include "hw/qdev.h" #include "qapi/error.h" =20 -static void qbus_set_hotplug_handler_internal(BusState *bus, Object *handl= er, - Error **errp) +void qbus_set_hotplug_handler(BusState *bus, Object *handler, Error **errp) { - object_property_set_link(OBJECT(bus), OBJECT(handler), QDEV_HOTPLUG_HANDLER_PROPERTY, errp); } =20 -void qbus_set_hotplug_handler(BusState *bus, DeviceState *handler, Error *= *errp) -{ - qbus_set_hotplug_handler_internal(bus, OBJECT(handler), errp); -} - void qbus_set_bus_hotplug_handler(BusState *bus, Error **errp) { - qbus_set_hotplug_handler_internal(bus, OBJECT(bus), errp); + qbus_set_hotplug_handler(bus, OBJECT(bus), errp); } =20 int qbus_walk_children(BusState *bus, diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 230478faab12..3f7c36609313 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -543,7 +543,7 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) dev->exp.hpev_notified =3D false; =20 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))), - DEVICE(dev), NULL); + OBJECT(dev), NULL); } =20 void pcie_cap_slot_reset(PCIDevice *dev) diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 45053b39b92c..52ccdc5ae3b9 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -648,7 +648,7 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegi= on *bar, shpc_cap_update_dword(d); memory_region_add_subregion(bar, offset, &shpc->mmio); =20 - qbus_set_hotplug_handler(BUS(sec_bus), DEVICE(d), NULL); + qbus_set_hotplug_handler(BUS(sec_bus), OBJECT(d), NULL); =20 d->cap_present |=3D QEMU_PCI_CAP_SHPC; return 0; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index e3781dd110b2..0d4bad7bbe73 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1743,7 +1743,7 @@ static void spapr_phb_realize(DeviceState *dev, Error= **errp) &sphb->memspace, &sphb->iospace, PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BU= S); phb->bus =3D bus; - qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL); + qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); =20 /* * Initialize PHB address space. diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 1bd6c8b45860..7573c40badbd 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -108,7 +108,7 @@ VirtualCssBus *virtual_css_bus_init(void) cbus =3D VIRTUAL_CSS_BUS(bus); =20 /* Enable hotplugging */ - qbus_set_hotplug_handler(bus, dev, &error_abort); + qbus_set_hotplug_handler(bus, OBJECT(dev), &error_abort); =20 css_register_io_adapters(CSS_IO_ADAPTER_VIRTIO, true, false, 0, &error_abort); diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 80ff1ce33f72..5998942b4c15 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -742,7 +742,7 @@ static void s390_pcihost_realize(DeviceState *dev, Erro= r **errp) pci_setup_iommu(b, s390_pci_dma_iommu, s); =20 bus =3D BUS(b); - qbus_set_hotplug_handler(bus, dev, &local_err); + qbus_set_hotplug_handler(bus, OBJECT(dev), &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -750,7 +750,7 @@ static void s390_pcihost_realize(DeviceState *dev, Erro= r **errp) phb->bus =3D b; =20 s->bus =3D S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL)); - qbus_set_hotplug_handler(BUS(s->bus), dev, &local_err); + qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev), &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -912,7 +912,7 @@ static void s390_pcihost_plug(HotplugHandler *hotplug_d= ev, DeviceState *dev, pci_bridge_map_irq(pb, dev->id, s390_pci_map_irq); pci_setup_iommu(&pb->sec_bus, s390_pci_dma_iommu, s); =20 - qbus_set_hotplug_handler(BUS(&pb->sec_bus), DEVICE(s), errp); + qbus_set_hotplug_handler(BUS(&pb->sec_bus), OBJECT(s), errp); =20 if (dev->hotplugged) { pci_default_write_config(pdev, PCI_PRIMARY_BUS, diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c index eb90288f4741..ce99d288b035 100644 --- a/hw/scsi/virtio-scsi.c +++ b/hw/scsi/virtio-scsi.c @@ -906,7 +906,7 @@ static void virtio_scsi_device_realize(DeviceState *dev= , Error **errp) scsi_bus_new(&s->bus, sizeof(s->bus), dev, &virtio_scsi_scsi_info, vdev->bus_name); /* override default SCSI bus hotplug-handler, with virtio-scsi's one */ - qbus_set_hotplug_handler(BUS(&s->bus), dev, &error_abort); + qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev), &error_abort); =20 virtio_scsi_dataplane_setup(s, errp); } diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index a3a019e30a74..584b4be07e79 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1142,7 +1142,7 @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info, NULL); /* override default SCSI bus hotplug-handler, with pvscsi's one */ - qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort); + qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s), &error_abort); pvscsi_reset_state(s); } =20 diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index 8f716fc165a3..6b0137bb7699 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1322,7 +1322,7 @@ static void ccid_realize(USBDevice *dev, Error **errp) usb_desc_init(dev); qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev= ), NULL); - qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(dev), &error_abort); + qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev), &error_abort); s->intr =3D usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP); s->bulk =3D usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP); s->card =3D NULL; diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 0a84c427561c..e70a4bfa498f 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -430,8 +430,7 @@ char *qdev_get_dev_path(DeviceState *dev); =20 GSList *qdev_build_hotpluggable_device_list(Object *peripheral); =20 -void qbus_set_hotplug_handler(BusState *bus, DeviceState *handler, - Error **errp); +void qbus_set_hotplug_handler(BusState *bus, Object *handler, Error **errp= ); =20 void qbus_set_bus_hotplug_handler(BusState *bus, Error **errp); =20 From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:08 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIP78x5046566 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:07 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B495AE051; Tue, 12 Feb 2019 18:25:07 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 658B0AE045; Tue, 12 Feb 2019 18:25:07 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:07 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 3425C220182; Tue, 12 Feb 2019 19:25:06 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:05 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3C6 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC749 Message-Id: <154999590577.690774.2666353651182347178.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 11/15] spapr_pci: provide node start offset via spapr_populate_pci_dt() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth PHB hotplug re-uses PHB device tree generation code and passes it to a guest via RTAS. Doing this requires knowledge of where exactly in the device tree the node describing the PHB begins. Provide this via a new optional pointer that can be used to store the PHB node's start offset. Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: Greg Kurz --- hw/ppc/spapr.c | 2 +- hw/ppc/spapr_pci.c | 5 ++++- include/hw/pci-host/spapr.h | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 03183c52f57b..021758825b7e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1295,7 +1295,7 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr) =20 QLIST_FOREACH(phb, &spapr->phbs, list) { ret =3D spapr_populate_pci_dt(phb, PHANDLE_INTC, fdt, - spapr->irq->nr_msis); + spapr->irq->nr_msis, NULL); if (ret < 0) { error_report("couldn't setup PCI devices in fdt"); exit(1); diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 0d4bad7bbe73..4f184a80df5d 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2139,7 +2139,7 @@ static void spapr_phb_pci_enumerate(sPAPRPHBState *ph= b) } =20 int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void = *fdt, - uint32_t nr_msis) + uint32_t nr_msis, int *node_offset) { int bus_off, i, j, ret; gchar *nodename; @@ -2194,6 +2194,9 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_= t intc_phandle, void *fdt, nodename =3D g_strdup_printf("pci@%" PRIx64, phb->buid); _FDT(bus_off =3D fdt_add_subnode(fdt, 0, nodename)); g_free(nodename); + if (node_offset) { + *node_offset =3D bus_off; + } =20 /* Write PHB properties */ _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 7cfce54a9449..c05cdaec481f 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -113,7 +113,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRP= HBState *phb, int pin) } =20 int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t intc_phandle, void = *fdt, - uint32_t nr_msis); + uint32_t nr_msis, int *node_offset); =20 void spapr_pci_rtas_init(void); =20 From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549997037943382.81849545265663; Tue, 12 Feb 2019 10:43:57 -0800 (PST) Received: from localhost ([127.0.0.1]:44247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd25-0007EA-PM for importer@patchew.org; Tue, 12 Feb 2019 13:43:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38987) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtckM-0001ox-Cl for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtckK-0004fP-BQ for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:30 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:59604 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtckE-0004a5-Qs for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:24 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIK07V003170 for ; Tue, 12 Feb 2019 13:25:21 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0rc7xbn-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:20 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:15 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIPEq63539240 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:14 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 095A75205A; Tue, 12 Feb 2019 18:25:14 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id E8DAC52054; Tue, 12 Feb 2019 18:25:13 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C0068220182; Tue, 12 Feb 2019 19:25:12 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:12 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3CC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC74E Message-Id: <154999591235.690774.7699147177061084209.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 12/15] spapr_pci: add ibm, my-drc-index property for PHB hotplug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth This is needed to denote a boot-time PHB as being hot-pluggable. Signed-off-by: Michael Roth Reviewed-by: David Gibson Signed-off-by: Greg Kurz --- hw/ppc/spapr_pci.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 4f184a80df5d..7df7f6502f93 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2189,6 +2189,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_= t intc_phandle, void *fdt, sPAPRTCETable *tcet; PCIBus *bus =3D PCI_HOST_BRIDGE(phb)->bus; sPAPRFDT s_fdt; + sPAPRDRConnector *drc; =20 /* Start populating the FDT */ nodename =3D g_strdup_printf("pci@%" PRIx64, phb->buid); @@ -2255,6 +2256,14 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32= _t intc_phandle, void *fdt, tcet->liobn, tcet->bus_offset, tcet->nb_table << tcet->page_shift); =20 + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); + if (drc) { + uint32_t drc_index =3D cpu_to_be32(spapr_drc_index(drc)); + + _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, + sizeof(drc_index))); + } + /* Walk the bridges and program the bus numbers*/ spapr_phb_pci_enumerate(phb); _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549997301263318.0681002700861; Tue, 12 Feb 2019 10:48:21 -0800 (PST) Received: from localhost ([127.0.0.1]:44337 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd6L-0002Bk-4d for importer@patchew.org; Tue, 12 Feb 2019 13:48:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39114) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcko-0002Dg-9M for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtckm-00056K-I8 for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:58 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:52354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtckm-0004gr-3r for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:25:56 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIJqJI136994 for ; Tue, 12 Feb 2019 13:25:29 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0m78cee-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:28 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:21 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIPKJc57475152 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:20 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9B6C2AE056; Tue, 12 Feb 2019 18:25:20 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89C10AE053; Tue, 12 Feb 2019 18:25:20 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:20 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 5A476220182; Tue, 12 Feb 2019 19:25:19 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:19 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-4275-0000-0000-0000030EAC69 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-4276-0000-0000-0000381CC2CE Message-Id: <154999591892.690774.10674853078354564704.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 13/15] spapr_drc: Allow FDT fragment to be added later X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The current logic is to provide the FDT fragment when attaching a device to a DRC. This works perfectly fine for our current hotplug support, but soon we will add support for PHB hotplug which has some constraints, that CPU, PCI and LMB devices don't seem to have. The first constraint is that the "ibm,dma-window" property of the PHB node requires the IOMMU to be configured, ie, spapr_tce_table_enable() has been called, which happens during PHB reset. It is okay in the case of hotplug since the device is reset before the hotplug handler is called. On the contrary with coldplug, the hotplug handler is called first and device is only reset during the initial system reset. Trying to create the FDT fragment on the hotplug path in this case, would result in somthing like this: ibm,dma-window =3D < 0x80000000 0x00 0x00 0x00 0x00 >; This will cause linux in the guest to panic, by simply removing and re-adding the PHB using the drmgr command: page =3D alloc_pages_node(nid, GFP_KERNEL, get_order(sz)); if (!page) panic("iommu_init_table: Can't allocate %ld bytes\n", sz); The second and maybe more problematic constraint is that the "interrupt-map" property needs to reference the interrupt controller node using the very same phandle that SLOF has already exposed to the guest. QEMU requires SLOF to call the private KVMPPC_H_UPDATE_DT hcall at some point to know about this phandle. With the latest QEMU and SLOF, this happens when SLOF gets quiesced. This means that if the PHB gets hotplugged after CAS but before SLOF quiesce, then we're sure that the phandle is not known when the hotplug handler is called. The FDT is only needed when the guest first invokes RTAS to configure the connector actually, long after SLOF quiesce. Let's postpone the creation of FDT fragments for PHBs to rtas_ibm_configure_connector(). Since we only need this for PHBs, introduce a new method in the base DRC class for that. It will implemented for "spapr-drc-phb" DRCs in a subsequent patch. Allow spapr_drc_attach() to be passed a NULL fdt argument if the method is available. Signed-off-by: Greg Kurz --- hw/ppc/spapr_drc.c | 34 +++++++++++++++++++++++++++++----- include/hw/ppc/spapr_drc.h | 6 ++++++ 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 189ee681062a..c5a281915665 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -22,6 +22,7 @@ #include "qemu/error-report.h" #include "hw/ppc/spapr.h" /* for RTAS return codes */ #include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback = */ +#include "sysemu/device_tree.h" #include "trace.h" =20 #define DRC_CONTAINER_PATH "/dr-connector" @@ -376,6 +377,8 @@ static void prop_get_fdt(Object *obj, Visitor *v, const= char *name, void spapr_drc_attach(sPAPRDRConnector *drc, DeviceState *d, void *fdt, int fdt_start_offset, Error **errp) { + sPAPRDRConnectorClass *drck =3D SPAPR_DR_CONNECTOR_GET_CLASS(drc); + trace_spapr_drc_attach(spapr_drc_index(drc)); =20 if (drc->dev) { @@ -384,11 +387,14 @@ void spapr_drc_attach(sPAPRDRConnector *drc, DeviceSt= ate *d, void *fdt, } g_assert((drc->state =3D=3D SPAPR_DRC_STATE_LOGICAL_UNUSABLE) || (drc->state =3D=3D SPAPR_DRC_STATE_PHYSICAL_POWERON)); - g_assert(fdt); + g_assert(fdt || drck->populate_dt); =20 drc->dev =3D d; - drc->fdt =3D fdt; - drc->fdt_start_offset =3D fdt_start_offset; + + if (fdt) { + drc->fdt =3D fdt; + drc->fdt_start_offset =3D fdt_start_offset; + } =20 object_property_add_link(OBJECT(drc), "device", object_get_typename(OBJECT(drc->dev)), @@ -1118,10 +1124,28 @@ static void rtas_ibm_configure_connector(PowerPCCPU= *cpu, goto out; } =20 - g_assert(drc->fdt); - drck =3D SPAPR_DR_CONNECTOR_GET_CLASS(drc); =20 + g_assert(drc->fdt || drck->populate_dt); + + if (!drc->fdt) { + Error *local_err =3D NULL; + void *fdt; + int fdt_size; + + fdt =3D create_device_tree(&fdt_size); + + if (drck->populate_dt(drc->dev, spapr, fdt, &drc->fdt_start_offset, + &local_err)) { + g_free(fdt); + error_free(local_err); + rc =3D SPAPR_DR_CC_RESPONSE_ERROR; + goto out; + } + + drc->fdt =3D fdt; + } + do { uint32_t tag; const char *name; diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h index 56bba36ad4da..e947d6987bf2 100644 --- a/include/hw/ppc/spapr_drc.h +++ b/include/hw/ppc/spapr_drc.h @@ -18,6 +18,7 @@ #include "qom/object.h" #include "sysemu/sysemu.h" #include "hw/qdev.h" +#include "qapi/error.h" =20 #define TYPE_SPAPR_DR_CONNECTOR "spapr-dr-connector" #define SPAPR_DR_CONNECTOR_GET_CLASS(obj) \ @@ -221,6 +222,8 @@ typedef struct sPAPRDRConnector { int fdt_start_offset; } sPAPRDRConnector; =20 +struct sPAPRMachineState; + typedef struct sPAPRDRConnectorClass { /*< private >*/ DeviceClass parent; @@ -236,6 +239,9 @@ typedef struct sPAPRDRConnectorClass { uint32_t (*isolate)(sPAPRDRConnector *drc); uint32_t (*unisolate)(sPAPRDRConnector *drc); void (*release)(DeviceState *dev); + + int (*populate_dt)(DeviceState *dev, struct sPAPRMachineState *spapr, + void *fdt, int *fdt_start_offset, Error **errp); } sPAPRDRConnectorClass; =20 typedef struct sPAPRDRCPhysical { From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549997499673844.9243278942135; Tue, 12 Feb 2019 10:51:39 -0800 (PST) Received: from localhost ([127.0.0.1]:44433 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd9e-0004sp-LD for importer@patchew.org; Tue, 12 Feb 2019 13:51:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtcl0-0002Qj-LN for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtcky-0005Kd-UH for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:10 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:49388) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gtckw-0004p2-OI for qemu-devel@nongnu.org; Tue, 12 Feb 2019 13:26:08 -0500 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1CIKZZJ127937 for ; Tue, 12 Feb 2019 13:25:37 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qm0ns058t-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Feb 2019 13:25:36 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:28 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIPRQ98782120 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:27 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 41074A405C; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 22F8CA405B; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:27 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id E4D84220182; Tue, 12 Feb 2019 19:25:25 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:25 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0016-0000-0000-00000255A3D2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0017-0000-0000-000032AFC754 Message-Id: <154999592549.690774.13071669609040970763.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v4 14/15] spapr: add hotplug hooks for PHB hotplug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Hotplugging PHBs is a machine-level operation, but PHBs reside on the main system bus, so we register spapr machine as the handler for the main system bus. Provide the usual pre-plug, plug and unplug-request handlers. Move the checking of the PHB index to the pre-plug handler. It is okay to do that and assert in the realize function because the pre-plug handler is always called, even for the oldest machine types we support. Unlike with other device types, there are some cases where we cannot provide the FDT fragment of the PHB from the plug handler, eg, before KVMPPC_H_UPDATE_DT was called. Do this from a DRC callback that is called just before the first FDT fragment is exposed to the guest. Signed-off-by: Michael Roth (Fixed interrupt controller phandle in "interrupt-map" and TCE table size in "ibm,dma-window" FDT fragment, Greg Kurz) Signed-off-by: Greg Kurz --- v4: - populate FDT fragment in a DRC callback v3: - reworked phandle handling some more v2: - reworked phandle handling - sync LSIs to KVM --- --- hw/ppc/spapr.c | 121 ++++++++++++++++++++++++++++++++++++++++++++= ++++ hw/ppc/spapr_drc.c | 2 + hw/ppc/spapr_pci.c | 16 ------ include/hw/ppc/spapr.h | 5 ++ 4 files changed, 127 insertions(+), 17 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 021758825b7e..06ce0babcb54 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2930,6 +2930,11 @@ static void spapr_machine_init(MachineState *machine) register_savevm_live(NULL, "spapr/htab", -1, 1, &savevm_htab_handlers, spapr); =20 + if (smc->dr_phb_enabled) { + qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), + &error_fatal); + } + qemu_register_boot_set(spapr_boot_set, spapr); =20 if (kvm_enabled()) { @@ -3733,6 +3738,108 @@ out: error_propagate(errp, local_err); } =20 +int spapr_dt_phb(DeviceState *dev, sPAPRMachineState *spapr, void *fdt, + int *fdt_start_offset, Error **errp) +{ + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + uint32_t intc_phandle; + + if (spapr_irq_get_phandle(spapr, spapr->fdt_blob, &intc_phandle, errp)= ) { + return -1; + } + + if (spapr_populate_pci_dt(sphb, intc_phandle, fdt, spapr->irq->nr_msis, + fdt_start_offset)) { + error_setg(errp, "unable to create FDT node for PHB %d", sphb->ind= ex); + return -1; + } + + /* generally SLOF creates these, for hotplug it's up to QEMU */ + _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); + + return 0; +} + +static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *d= ev, + Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + const unsigned windows_supported =3D spapr_phb_windows_supported(sphb); + + if (sphb->index =3D=3D (uint32_t)-1) { + error_setg(errp, "\"index\" for PAPR PHB is mandatory"); + return; + } + + /* + * This will check that sphb->index doesn't exceed the maximum number = of + * PHBs for the current machine type. + */ + smc->phb_placement(spapr, sphb->index, + &sphb->buid, &sphb->io_win_addr, + &sphb->mem_win_addr, &sphb->mem64_win_addr, + windows_supported, sphb->dma_liobn, errp); +} + +static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev, + Error **errp) +{ + sPAPRMachineState *spapr =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRDRConnector *drc; + bool hotplugged =3D spapr_drc_hotplugged(dev); + Error *local_err =3D NULL; + + if (!smc->dr_phb_enabled) { + return; + } + + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); + /* hotplug hooks should check it's enabled before getting this far */ + assert(drc); + + /* + * The FDT fragment will be added during the first invocation of RTAS + * ibm,client-architecture-support for this device, when we're sure + * that the IOMMU is configured and that QEMU knows the phandle of the + * interrupt controller. + */ + spapr_drc_attach(drc, DEVICE(dev), NULL, 0, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + if (hotplugged) { + spapr_hotplug_req_add_by_index(drc); + } else { + spapr_drc_reset(drc); + } +} + +void spapr_phb_release(DeviceState *dev) +{ + object_unparent(OBJECT(dev)); +} + +static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + sPAPRPHBState *sphb =3D SPAPR_PCI_HOST_BRIDGE(dev); + sPAPRDRConnector *drc; + + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); + assert(drc); + + if (!spapr_drc_unplug_requested(drc)) { + spapr_drc_detach(drc); + spapr_hotplug_req_remove_by_index(drc); + } +} + static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { @@ -3740,6 +3847,8 @@ static void spapr_machine_device_plug(HotplugHandler = *hotplug_dev, spapr_memory_plug(hotplug_dev, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { spapr_core_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + spapr_phb_plug(hotplug_dev, dev, errp); } } =20 @@ -3758,6 +3867,7 @@ static void spapr_machine_device_unplug_request(Hotpl= ugHandler *hotplug_dev, { sPAPRMachineState *sms =3D SPAPR_MACHINE(OBJECT(hotplug_dev)); MachineClass *mc =3D MACHINE_GET_CLASS(sms); + sPAPRMachineClass *smc =3D SPAPR_MACHINE_CLASS(mc); =20 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { @@ -3777,6 +3887,12 @@ static void spapr_machine_device_unplug_request(Hotp= lugHandler *hotplug_dev, return; } spapr_core_unplug_request(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + if (!smc->dr_phb_enabled) { + error_setg(errp, "PHB hot unplug not supported on this machine= "); + return; + } + spapr_phb_unplug_request(hotplug_dev, dev, errp); } } =20 @@ -3787,6 +3903,8 @@ static void spapr_machine_device_pre_plug(HotplugHand= ler *hotplug_dev, spapr_memory_pre_plug(hotplug_dev, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { spapr_core_pre_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE= )) { + spapr_phb_pre_plug(hotplug_dev, dev, errp); } } =20 @@ -3794,7 +3912,8 @@ static HotplugHandler *spapr_get_hotplug_handler(Mach= ineState *machine, DeviceState *dev) { if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || - object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { + object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || + object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { return HOTPLUG_HANDLER(machine); } return NULL; diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index c5a281915665..22563a381a37 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -709,6 +709,8 @@ static void spapr_drc_phb_class_init(ObjectClass *k, vo= id *data) drck->typeshift =3D SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB; drck->typename =3D "PHB"; drck->drc_name_prefix =3D "PHB "; + drck->release =3D spapr_phb_release; + drck->populate_dt =3D spapr_dt_phb; } =20 static const TypeInfo spapr_dr_connector_info =3D { diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7df7f6502f93..d0caca627455 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1647,21 +1647,7 @@ static void spapr_phb_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (sphb->index !=3D (uint32_t)-1) { - Error *local_err =3D NULL; - - smc->phb_placement(spapr, sphb->index, - &sphb->buid, &sphb->io_win_addr, - &sphb->mem_win_addr, &sphb->mem64_win_addr, - windows_supported, sphb->dma_liobn, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - } else { - error_setg(errp, "\"index\" for PAPR PHB is mandatory"); - return; - } + assert(sphb->index !=3D (uint32_t)-1); /* checked in spapr_phb_pre_plu= g() */ =20 if (sphb->mem64_win_size !=3D 0) { if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a3074e7fea37..69d9c2196ca2 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -764,9 +764,12 @@ void spapr_reallocate_hpt(sPAPRMachineState *spapr, in= t shift, void spapr_clear_pending_events(sPAPRMachineState *spapr); int spapr_max_server_number(sPAPRMachineState *spapr); =20 -/* CPU and LMB DRC release callbacks. */ +/* DRC callbacks. */ void spapr_core_release(DeviceState *dev); void spapr_lmb_release(DeviceState *dev); +void spapr_phb_release(DeviceState *dev); +int spapr_dt_phb(DeviceState *dev, sPAPRMachineState *spapr, void *fdt, + int *fdt_start_offset, Error **errp); =20 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns); int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset); From nobody Sat Nov 8 06:07:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549997042687153.9027553378163; Tue, 12 Feb 2019 10:44:02 -0800 (PST) Received: from localhost ([127.0.0.1]:44249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtd2C-0007L6-Ip for importer@patchew.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Feb 2019 18:25:34 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1CIPX2B36831250 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 18:25:33 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C5572AE055; Tue, 12 Feb 2019 18:25:33 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B03B1AE04D; Tue, 12 Feb 2019 18:25:33 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Feb 2019 18:25:33 +0000 (GMT) Received: from bahia.lan (sig-9-145-185-96.de.ibm.com [9.145.185.96]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 7F5E3220182; Tue, 12 Feb 2019 19:25:32 +0100 (CET) From: Greg Kurz To: David Gibson Date: Tue, 12 Feb 2019 19:25:32 +0100 In-Reply-To: <154999583316.690774.15072605479770041782.stgit@bahia.lan> References: <154999583316.690774.15072605479770041782.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19021218-0028-0000-0000-00000347C308 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021218-0029-0000-0000-00002405E40F Message-Id: <154999593208.690774.9057564435432736364.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-12_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=918 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902120129 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 15/15] spapr: enable PHB hotplug for default pseries machine type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , Cornelia Huck , Gerd Hoffmann , Michael Roth , "Michael S. Tsirkin" , Alexey Kardashevskiy , David Hildenbrand , qemu-devel@nongnu.org, Greg Kurz , qemu-s390x@nongnu.org, Dmitry Fleytman , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth The 'dr_phb_enabled' field of that class can be set as part of machine-specific init code. It will be used to conditionally enable creation of DRC objects and device-tree description to facilitate hotplug of PHBs. Since we can't migrate this state to older machine types, default the option to true and disable it for older machine types. Signed-off-by: Michael Roth Signed-off-by: Greg Kurz --- hw/ppc/spapr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 06ce0babcb54..4a6b2f7f3f62 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4166,6 +4166,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; spapr_caps_add_properties(smc, &error_abort); smc->irq =3D &spapr_irq_xics; + smc->dr_phb_enabled =3D true; } =20 static const TypeInfo spapr_machine_info =3D { @@ -4231,6 +4232,7 @@ static void spapr_machine_3_1_class_options(MachineCl= ass *mc) compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); smc->update_dt_enabled =3D false; + smc->dr_phb_enabled =3D false; } =20 DEFINE_SPAPR_MACHINE(3_1, "3.1", false);