From nobody Thu May 2 07:46:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1549372408089655.8088182018522; Tue, 5 Feb 2019 05:13:28 -0800 (PST) Received: from localhost ([127.0.0.1]:60119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr0XS-0004Sa-IN for importer@patchew.org; Tue, 05 Feb 2019 08:13:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr0V8-0002sS-J3 for qemu-devel@nongnu.org; Tue, 05 Feb 2019 08:10:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gr0S9-0003FI-HK for qemu-devel@nongnu.org; Tue, 05 Feb 2019 08:07:55 -0500 Received: from mail.ispras.ru ([83.149.199.45]:33642) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gr0S8-00033W-9n for qemu-devel@nongnu.org; Tue, 05 Feb 2019 08:07:53 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id CB460540089; Tue, 5 Feb 2019 16:07:34 +0300 (MSK) From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Date: Tue, 05 Feb 2019 16:07:35 +0300 Message-ID: <154937205518.29984.9188603364499998604.stgit@pasha-VirtualBox> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH] mips: implement qmp query-cpu-definitions command X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pavel.dovgaluk@ispras.ru, arikalo@wavecomp.com, mdroth@linux.vnet.ibm.com, armbru@redhat.com, dovgaluk@ispras.ru, natalia.fursova@ispras.ru, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" This patch enables QMP-based querying of the available CPU types for MIPS and MIPS64 platforms. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- monitor.c | 2 +- target/mips/helper.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/monitor.c b/monitor.c index c09fa63940..25d3b141ad 100644 --- a/monitor.c +++ b/monitor.c @@ -1165,7 +1165,7 @@ static void qmp_unregister_commands_hack(void) qmp_unregister_command(&qmp_commands, "query-cpu-model-comparison"); #endif #if !defined(TARGET_PPC) && !defined(TARGET_ARM) && !defined(TARGET_I386) \ - && !defined(TARGET_S390X) + && !defined(TARGET_S390X) && !defined(TARGET_MIPS) qmp_unregister_command(&qmp_commands, "query-cpu-definitions"); #endif } diff --git a/target/mips/helper.c b/target/mips/helper.c index 8988452dbd..c84d056c09 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -24,6 +24,7 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "sysemu/arch_init.h" =20 enum { TLBRET_XI =3D -6, @@ -1472,3 +1473,35 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSSta= te *env, =20 cpu_loop_exit_restore(cs, pc); } + +static void mips_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + const char *typename; + + typename =3D object_class_get_name(oc); + info =3D g_malloc0(sizeof(*info)); + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_MIPS_CPU)); + info->q_typename =3D g_strdup(typename); + + entry =3D g_malloc0(sizeof(*entry)); + entry->value =3D info; + entry->next =3D *cpu_list; + *cpu_list =3D entry; +} + +CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list; + + list =3D object_class_get_list(TYPE_MIPS_CPU, false); + g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +}