From nobody Fri Nov 7 19:47:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548858737243205.43990410089384; Wed, 30 Jan 2019 06:32:17 -0800 (PST) Received: from localhost ([127.0.0.1]:39098 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goquU-0002tu-3U for importer@patchew.org; Wed, 30 Jan 2019 09:32:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:56233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goqtO-0002Tc-KM for qemu-devel@nongnu.org; Wed, 30 Jan 2019 09:31:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goqtN-0006Uc-KF for qemu-devel@nongnu.org; Wed, 30 Jan 2019 09:31:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:35188) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1goqtM-0006Sk-37; Wed, 30 Jan 2019 09:31:05 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0562DC05D3F2; Wed, 30 Jan 2019 14:30:58 +0000 (UTC) Received: from thuth.com (ovpn-116-210.ams2.redhat.com [10.36.116.210]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9712060C6E; Wed, 30 Jan 2019 14:30:53 +0000 (UTC) From: Thomas Huth To: David Gibson , qemu-devel@nongnu.org Date: Wed, 30 Jan 2019 15:30:49 +0100 Message-Id: <1548858649-26208-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Wed, 30 Jan 2019 14:30:58 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] hw/ppc: Move ppc40x_*reset() functions from ppc405_uc.c to ppc.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, Paolo Bonzini , qemu-ppc@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, it is not possible to build a QEMU binary without the ppc405_uc.c file, even if you do not want to have the embedded machines in the binary. This is bad since it's quite a bit of code and this code pulls in some more dependencies (e.g. via the usage of serial_mm_init()) which would not be needed otherwise - especially with the upcoming Kconfig-style configuration system for QEMU. The only functions from this file which are really always required for linking are the ppc40x_*reset() functions, so move these functions to ppc.c, close to the ppc40x_set_irq() function that calls them. Now we can flag ppc405_uc.c and ppc4xx_devs.c with the CONFIG_PPC4XX config switch, too. And while we're at it, replace the printf()s in these ppc40x_*reset() functions with proper calls to qemu_log_mask(). Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/Makefile.objs | 3 +-- hw/ppc/ppc.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ hw/ppc/ppc405_uc.c | 58 ------------------------------------------------= ---- 3 files changed, 57 insertions(+), 60 deletions(-) diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs index 4e0c1c0..1e753de 100644 --- a/hw/ppc/Makefile.objs +++ b/hw/ppc/Makefile.objs @@ -13,8 +13,7 @@ obj-y +=3D spapr_pci_vfio.o endif obj-$(CONFIG_PSERIES) +=3D spapr_rtas_ddw.o # PowerPC 4xx boards -obj-y +=3D ppc4xx_devs.o ppc405_uc.o -obj-$(CONFIG_PPC4XX) +=3D ppc4xx_pci.o ppc405_boards.o +obj-$(CONFIG_PPC4XX) +=3D ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_bo= ards.o obj-$(CONFIG_PPC4XX) +=3D ppc440_bamboo.o ppc440_pcix.o ppc440_uc.o obj-$(CONFIG_SAM460EX) +=3D sam460ex.o # PReP diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index ec4be25..98b409f 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -310,6 +310,62 @@ void ppcPOWER7_irq_init(PowerPCCPU *cpu) } #endif /* defined(TARGET_PPC64) */ =20 +void ppc40x_core_reset(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong dbsr; + + qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); + dbsr =3D env->spr[SPR_40x_DBSR]; + dbsr &=3D ~0x00000300; + dbsr |=3D 0x00000100; + env->spr[SPR_40x_DBSR] =3D dbsr; +} + +void ppc40x_chip_reset(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong dbsr; + + qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); + /* XXX: TODO reset all internal peripherals */ + dbsr =3D env->spr[SPR_40x_DBSR]; + dbsr &=3D ~0x00000300; + dbsr |=3D 0x00000200; + env->spr[SPR_40x_DBSR] =3D dbsr; +} + +void ppc40x_system_reset(PowerPCCPU *cpu) +{ + qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); +} + +void store_40x_dbcr0(CPUPPCState *env, uint32_t val) +{ + PowerPCCPU *cpu =3D ppc_env_get_cpu(env); + + switch ((val >> 28) & 0x3) { + case 0x0: + /* No action */ + break; + case 0x1: + /* Core reset */ + ppc40x_core_reset(cpu); + break; + case 0x2: + /* Chip reset */ + ppc40x_chip_reset(cpu); + break; + case 0x3: + /* System reset */ + ppc40x_system_reset(cpu); + break; + } +} + /* PowerPC 40x internal IRQ controller */ static void ppc40x_set_irq(void *opaque, int pin, int level) { diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 8d3a797..3ae7f6d 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1156,64 +1156,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq ir= qs[5]) } =20 /*************************************************************************= ****/ -/* SPR */ -void ppc40x_core_reset(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - target_ulong dbsr; - - printf("Reset PowerPC core\n"); - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); - dbsr =3D env->spr[SPR_40x_DBSR]; - dbsr &=3D ~0x00000300; - dbsr |=3D 0x00000100; - env->spr[SPR_40x_DBSR] =3D dbsr; -} - -void ppc40x_chip_reset(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - target_ulong dbsr; - - printf("Reset PowerPC chip\n"); - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); - /* XXX: TODO reset all internal peripherals */ - dbsr =3D env->spr[SPR_40x_DBSR]; - dbsr &=3D ~0x00000300; - dbsr |=3D 0x00000200; - env->spr[SPR_40x_DBSR] =3D dbsr; -} - -void ppc40x_system_reset(PowerPCCPU *cpu) -{ - printf("Reset PowerPC system\n"); - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); -} - -void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) -{ - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); - - switch ((val >> 28) & 0x3) { - case 0x0: - /* No action */ - break; - case 0x1: - /* Core reset */ - ppc40x_core_reset(cpu); - break; - case 0x2: - /* Chip reset */ - ppc40x_chip_reset(cpu); - break; - case 0x3: - /* System reset */ - ppc40x_system_reset(cpu); - break; - } -} - -/*************************************************************************= ****/ /* PowerPC 405CR */ enum { PPC405CR_CPC0_PLLMR =3D 0x0B0, --=20 1.8.3.1