From nobody Fri Nov 7 18:50:29 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548423430113776.8939768776075; Fri, 25 Jan 2019 05:37:10 -0800 (PST) Received: from localhost ([127.0.0.1]:44731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gn1fJ-0006WS-3y for importer@patchew.org; Fri, 25 Jan 2019 08:37:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gn1aK-0002m7-W8 for qemu-devel@nongnu.org; Fri, 25 Jan 2019 08:31:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gn1aI-0002Xw-QC for qemu-devel@nongnu.org; Fri, 25 Jan 2019 08:31:52 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:36393 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gn1aI-0002W9-Cc for qemu-devel@nongnu.org; Fri, 25 Jan 2019 08:31:50 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 1AA021A23E7; Fri, 25 Jan 2019 14:31:48 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id DBAB31A229E; Fri, 25 Jan 2019 14:31:47 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 25 Jan 2019 14:31:35 +0100 Message-Id: <1548423098-31864-12-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548423098-31864-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1548423098-31864-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 11/14] tests: tcg: mips: Add two new Makefiles X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add Makefiles for two new direcitories. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic --- tests/tcg/mips/user/ase/dsp/Makefile | 184 +++++++++++++++++++++++++++++= ++++ tests/tcg/mips/user/isa/r5900/Makefile | 32 ++++++ 2 files changed, 216 insertions(+) create mode 100644 tests/tcg/mips/user/ase/dsp/Makefile create mode 100644 tests/tcg/mips/user/isa/r5900/Makefile diff --git a/tests/tcg/mips/user/ase/dsp/Makefile b/tests/tcg/mips/user/ase= /dsp/Makefile new file mode 100644 index 0000000..5c6da96 --- /dev/null +++ b/tests/tcg/mips/user/ase/dsp/Makefile @@ -0,0 +1,184 @@ +-include ../../../../config-host.mak + +CROSS=3Dmips64el-unknown-linux-gnu- + +SIM=3Dqemu-mipsel +SIM_FLAGS=3D-cpu 74Kf + +CC =3D $(CROSS)gcc +CFLAGS =3D -EL -mabi=3D32 -march=3Dmips32r2 -mgp32 -mdsp -mdspr2 -static + +TESTCASES =3D test_dsp_r1_absq_s_ph.tst +TESTCASES +=3D test_dsp_r1_absq_s_w.tst +TESTCASES +=3D test_dsp_r1_addq_ph.tst +TESTCASES +=3D test_dsp_r1_addq_s_ph.tst +TESTCASES +=3D test_dsp_r1_addq_s_w.tst +TESTCASES +=3D test_dsp_r1_addsc.tst +TESTCASES +=3D test_dsp_r1_addu_qb.tst +TESTCASES +=3D test_dsp_r1_addu_s_qb.tst +TESTCASES +=3D test_dsp_r1_addwc.tst +TESTCASES +=3D test_dsp_r1_bitrev.tst +TESTCASES +=3D test_dsp_r1_bposge32.tst +TESTCASES +=3D test_dsp_r1_cmp_eq_ph.tst +TESTCASES +=3D test_dsp_r1_cmpgu_eq_qb.tst +TESTCASES +=3D test_dsp_r1_cmpgu_le_qb.tst +TESTCASES +=3D test_dsp_r1_cmpgu_lt_qb.tst +TESTCASES +=3D test_dsp_r1_cmp_le_ph.tst +TESTCASES +=3D test_dsp_r1_cmp_lt_ph.tst +TESTCASES +=3D test_dsp_r1_cmpu_eq_qb.tst +TESTCASES +=3D test_dsp_r1_cmpu_le_qb.tst +TESTCASES +=3D test_dsp_r1_cmpu_lt_qb.tst +TESTCASES +=3D test_dsp_r1_dpaq_sa_l_w.tst +TESTCASES +=3D test_dsp_r1_dpaq_s_w_ph.tst +TESTCASES +=3D test_dsp_r1_dpau_h_qbl.tst +TESTCASES +=3D test_dsp_r1_dpau_h_qbr.tst +TESTCASES +=3D test_dsp_r1_dpsq_sa_l_w.tst +TESTCASES +=3D test_dsp_r1_dpsq_s_w_ph.tst +TESTCASES +=3D test_dsp_r1_dpsu_h_qbl.tst +TESTCASES +=3D test_dsp_r1_dpsu_h_qbr.tst +TESTCASES +=3D test_dsp_r1_extp.tst +TESTCASES +=3D test_dsp_r1_extpdp.tst +TESTCASES +=3D test_dsp_r1_extpdpv.tst +TESTCASES +=3D test_dsp_r1_extpv.tst +TESTCASES +=3D test_dsp_r1_extr_rs_w.tst +TESTCASES +=3D test_dsp_r1_extr_r_w.tst +TESTCASES +=3D test_dsp_r1_extr_s_h.tst +TESTCASES +=3D test_dsp_r1_extrv_rs_w.tst +TESTCASES +=3D test_dsp_r1_extrv_r_w.tst +TESTCASES +=3D test_dsp_r1_extrv_s_h.tst +TESTCASES +=3D test_dsp_r1_extrv_w.tst +TESTCASES +=3D test_dsp_r1_extr_w.tst +TESTCASES +=3D test_dsp_r1_insv.tst +TESTCASES +=3D test_dsp_r1_lbux.tst +TESTCASES +=3D test_dsp_r1_lhx.tst +TESTCASES +=3D test_dsp_r1_lwx.tst +TESTCASES +=3D test_dsp_r1_madd.tst +TESTCASES +=3D test_dsp_r1_maddu.tst +TESTCASES +=3D test_dsp_r1_maq_sa_w_phl.tst +TESTCASES +=3D test_dsp_r1_maq_sa_w_phr.tst +TESTCASES +=3D test_dsp_r1_maq_s_w_phl.tst +TESTCASES +=3D test_dsp_r1_maq_s_w_phr.tst +TESTCASES +=3D test_dsp_r1_mfhi.tst +TESTCASES +=3D test_dsp_r1_mflo.tst +TESTCASES +=3D test_dsp_r1_modsub.tst +TESTCASES +=3D test_dsp_r1_msub.tst +TESTCASES +=3D test_dsp_r1_msubu.tst +TESTCASES +=3D test_dsp_r1_mthi.tst +TESTCASES +=3D test_dsp_r1_mthlip.tst +TESTCASES +=3D test_dsp_r1_mtlo.tst +TESTCASES +=3D test_dsp_r1_muleq_s_w_phl.tst +TESTCASES +=3D test_dsp_r1_muleq_s_w_phr.tst +TESTCASES +=3D test_dsp_r1_muleu_s_ph_qbl.tst +TESTCASES +=3D test_dsp_r1_muleu_s_ph_qbr.tst +TESTCASES +=3D test_dsp_r1_mulq_rs_ph.tst +TESTCASES +=3D test_dsp_r1_mult.tst +TESTCASES +=3D test_dsp_r1_multu.tst +TESTCASES +=3D test_dsp_r1_packrl_ph.tst +TESTCASES +=3D test_dsp_r1_pick_ph.tst +TESTCASES +=3D test_dsp_r1_pick_qb.tst +TESTCASES +=3D test_dsp_r1_precequ_ph_qbla.tst +TESTCASES +=3D test_dsp_r1_precequ_ph_qbl.tst +TESTCASES +=3D test_dsp_r1_precequ_ph_qbra.tst +TESTCASES +=3D test_dsp_r1_precequ_ph_qbr.tst +TESTCASES +=3D test_dsp_r1_preceq_w_phl.tst +TESTCASES +=3D test_dsp_r1_preceq_w_phr.tst +TESTCASES +=3D test_dsp_r1_preceu_ph_qbla.tst +TESTCASES +=3D test_dsp_r1_preceu_ph_qbl.tst +TESTCASES +=3D test_dsp_r1_preceu_ph_qbra.tst +TESTCASES +=3D test_dsp_r1_preceu_ph_qbr.tst +TESTCASES +=3D test_dsp_r1_precrq_ph_w.tst +TESTCASES +=3D test_dsp_r1_precrq_qb_ph.tst +TESTCASES +=3D test_dsp_r1_precrq_rs_ph_w.tst +TESTCASES +=3D test_dsp_r1_precrqu_s_qb_ph.tst +TESTCASES +=3D test_dsp_r1_raddu_w_qb.tst +TESTCASES +=3D test_dsp_r1_rddsp.tst +TESTCASES +=3D test_dsp_r1_repl_ph.tst +TESTCASES +=3D test_dsp_r1_repl_qb.tst +TESTCASES +=3D test_dsp_r1_replv_ph.tst +TESTCASES +=3D test_dsp_r1_replv_qb.tst +TESTCASES +=3D test_dsp_r1_shilo.tst +TESTCASES +=3D test_dsp_r1_shilov.tst +TESTCASES +=3D test_dsp_r1_shll_ph.tst +TESTCASES +=3D test_dsp_r1_shll_qb.tst +TESTCASES +=3D test_dsp_r1_shll_s_ph.tst +TESTCASES +=3D test_dsp_r1_shll_s_w.tst +TESTCASES +=3D test_dsp_r1_shllv_ph.tst +TESTCASES +=3D test_dsp_r1_shllv_qb.tst +TESTCASES +=3D test_dsp_r1_shllv_s_ph.tst +TESTCASES +=3D test_dsp_r1_shllv_s_w.tst +TESTCASES +=3D test_dsp_r1_shra_ph.tst +TESTCASES +=3D test_dsp_r1_shra_r_ph.tst +TESTCASES +=3D test_dsp_r1_shra_r_w.tst +TESTCASES +=3D test_dsp_r1_shrav_ph.tst +TESTCASES +=3D test_dsp_r1_shrav_r_ph.tst +TESTCASES +=3D test_dsp_r1_shrav_r_w.tst +TESTCASES +=3D test_dsp_r1_shrl_qb.tst +TESTCASES +=3D test_dsp_r1_shrlv_qb.tst +TESTCASES +=3D test_dsp_r1_subq_ph.tst +TESTCASES +=3D test_dsp_r1_subq_s_ph.tst +TESTCASES +=3D test_dsp_r1_subq_s_w.tst +TESTCASES +=3D test_dsp_r1_subu_qb.tst +TESTCASES +=3D test_dsp_r1_subu_s_qb.tst +TESTCASES +=3D test_dsp_r1_wrdsp.tst +TESTCASES +=3D test_dsp_r2_absq_s_qb.tst +TESTCASES +=3D test_dsp_r2_addqh_ph.tst +TESTCASES +=3D test_dsp_r2_addqh_r_ph.tst +TESTCASES +=3D test_dsp_r2_addqh_r_w.tst +TESTCASES +=3D test_dsp_r2_addqh_w.tst +TESTCASES +=3D test_dsp_r2_adduh_qb.tst +TESTCASES +=3D test_dsp_r2_adduh_r_qb.tst +TESTCASES +=3D test_dsp_r2_addu_ph.tst +TESTCASES +=3D test_dsp_r2_addu_s_ph.tst +TESTCASES +=3D test_dsp_r2_append.tst +TESTCASES +=3D test_dsp_r2_balign.tst +TESTCASES +=3D test_dsp_r2_cmpgdu_eq_qb.tst +TESTCASES +=3D test_dsp_r2_cmpgdu_le_qb.tst +TESTCASES +=3D test_dsp_r2_cmpgdu_lt_qb.tst +TESTCASES +=3D test_dsp_r2_dpaqx_sa_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpa_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpax_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpaqx_s_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpsqx_sa_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpsqx_s_w_ph.tst +TESTCASES +=3D test_dsp_r2_dps_w_ph.tst +TESTCASES +=3D test_dsp_r2_dpsx_w_ph.tst +TESTCASES +=3D test_dsp_r2_mul_ph.tst +TESTCASES +=3D test_dsp_r2_mulq_rs_w.tst +TESTCASES +=3D test_dsp_r2_mulq_s_ph.tst +TESTCASES +=3D test_dsp_r2_mulq_s_w.tst +TESTCASES +=3D test_dsp_r2_mulsaq_s_w_ph.tst +TESTCASES +=3D test_dsp_r2_mulsa_w_ph.tst +TESTCASES +=3D test_dsp_r2_mul_s_ph.tst +TESTCASES +=3D test_dsp_r2_precr_qb_ph.tst +TESTCASES +=3D test_dsp_r2_precr_sra_ph_w.tst +TESTCASES +=3D test_dsp_r2_precr_sra_r_ph_w.tst +TESTCASES +=3D test_dsp_r2_prepend.tst +TESTCASES +=3D test_dsp_r2_shra_qb.tst +TESTCASES +=3D test_dsp_r2_shra_r_qb.tst +TESTCASES +=3D test_dsp_r2_shrav_qb.tst +TESTCASES +=3D test_dsp_r2_shrav_r_qb.tst +TESTCASES +=3D test_dsp_r2_shrl_ph.tst +TESTCASES +=3D test_dsp_r2_shrlv_ph.tst +TESTCASES +=3D test_dsp_r2_subqh_ph.tst +TESTCASES +=3D test_dsp_r2_subqh_r_ph.tst +TESTCASES +=3D test_dsp_r2_subqh_r_w.tst +TESTCASES +=3D test_dsp_r2_subqh_w.tst +TESTCASES +=3D test_dsp_r2_subuh_qb.tst +TESTCASES +=3D test_dsp_r2_subuh_r_qb.tst +TESTCASES +=3D test_dsp_r2_subu_ph.tst +TESTCASES +=3D test_dsp_r2_subu_s_ph.tst + + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/mips/user/isa/r5900/Makefile b/tests/tcg/mips/user/i= sa/r5900/Makefile new file mode 100644 index 0000000..bff360d --- /dev/null +++ b/tests/tcg/mips/user/isa/r5900/Makefile @@ -0,0 +1,32 @@ +-include ../../../../config-host.mak + +CROSS=3Dmipsr5900el-unknown-linux-gnu- + +SIM=3Dqemu-mipsel +SIM_FLAGS=3D-cpu R5900 + +CC =3D $(CROSS)gcc +CFLAGS =3D -Wall -mabi=3D32 -march=3Dr5900 -static + +TESTCASES =3D test_r5900_div1.tst +TESTCASES +=3D test_r5900_divu1.tst +TESTCASES +=3D test_r5900_madd.tst +TESTCASES +=3D test_r5900_maddu.tst +TESTCASES +=3D test_r5900_mflohi1.tst +TESTCASES +=3D test_r5900_mtlohi1.tst +TESTCASES +=3D test_r5900_mult.tst +TESTCASES +=3D test_r5900_multu.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) --=20 2.7.4