From nobody Fri Nov 7 14:49:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548242708640772.0631972633757; Wed, 23 Jan 2019 03:25:08 -0800 (PST) Received: from localhost ([127.0.0.1]:60903 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmGeZ-0007iU-Hu for importer@patchew.org; Wed, 23 Jan 2019 06:25:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54294) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmGXQ-00027E-4V for qemu-devel@nongnu.org; Wed, 23 Jan 2019 06:17:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gmGXO-0007hA-83 for qemu-devel@nongnu.org; Wed, 23 Jan 2019 06:17:43 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:56776 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gmGXN-0007d7-UN for qemu-devel@nongnu.org; Wed, 23 Jan 2019 06:17:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6EA821A0F00; Wed, 23 Jan 2019 12:16:29 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 130CF1A20B2; Wed, 23 Jan 2019 12:16:29 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Wed, 23 Jan 2019 12:15:59 +0100 Message-Id: <1548242160-16039-9-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548242160-16039-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1548242160-16039-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 8/9] target/mips: Add I6500 core configuration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Add I6500 core configuration. Note that this configuration is supported only on best-effort basis due to the lack of certain features in QEMU. Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- target/mips/translate_init.inc.c | 40 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index acab097..bf559af 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -722,6 +722,46 @@ const mips_def_t mips_defs[] =3D .mmu_type =3D MMU_TYPE_R4000, }, { + .name =3D "I6500", + .CP0_PRid =3D 0x1B000, + .CP0_Config0 =3D MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_= AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA)= | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA)= | + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 =3D MIPS_CONFIG2, + .CP0_Config3 =3D MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULR= I) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_V= Int), + .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | + (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP)= | + (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI)= | + (1 << CP0C5_FRE) | (1 << CP0C5_UFE), + .CP0_LLAddr_rw_bitmask =3D 0, + .CP0_LLAddr_shift =3D 0, + .SYNCI_Step =3D 64, + .CCRes =3D 2, + .CP0_Status_rw_bitmask =3D 0x30D8FFFF, + .CP0_PageGrain =3D (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + .CP0_PageGrain_rw_bitmask =3D (1 << CP0PG_ELPA), + .CP0_EBaseWG_rw_bitmask =3D (1 << CP0EBase_WG), + .CP1_fcr0 =3D (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_= F64) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV= ), + .CP1_fcr31 =3D (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), + .CP1_fcr31_rw_bitmask =3D 0x0103FFFF, + .MSAIR =3D 0x03 << MSAIR_ProcID, + .SEGBITS =3D 48, + .PABITS =3D 48, + .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .mmu_type =3D MMU_TYPE_R4000, + }, + { .name =3D "Loongson-2E", .CP0_PRid =3D 0x6302, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ --=20 2.7.4