From nobody Fri Nov 7 14:40:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098773883426.61142464198554; Mon, 21 Jan 2019 11:26:13 -0800 (PST) Received: from localhost ([127.0.0.1]:58620 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfD2-0005bu-Ru for importer@patchew.org; Mon, 21 Jan 2019 14:26:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glexJ-0001ms-EU for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:09:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glexI-0004Le-Iq for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:09:57 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:50418 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glexI-0003uH-5E for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:09:56 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 594A21A2113; Mon, 21 Jan 2019 20:08:52 +0100 (CET) Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 38E781A21C2; Mon, 21 Jan 2019 20:08:52 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 20:08:16 +0100 Message-Id: <1548097698-28951-5-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548097698-28951-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1548097698-28951-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH 4/6] target/mips: Correct the second argument type of cpu_supports_isa() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: smarkovic@wavecomp.com, arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic "insn_flags" bitfield was expanded from 32-bit to 64-bit at one moment. However, this was not reflected at the second argument of the function cpu_supports_isa(). By chance, this did not create a wrong behavior, since the second argument was always with the left-most half zero, but it is still a bug waiting to happen. correct by changint the type of the second argument to be 64-bit always. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 2 +- target/mips/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 03c03fd..fd22bd5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1011,7 +1011,7 @@ int cpu_mips_signal_handler(int host_signum, void *pi= nfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU =20 bool cpu_supports_cps_smp(const char *cpu_type); -bool cpu_supports_isa(const char *cpu_type, unsigned int isa); +bool cpu_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); =20 /* mips_int.c */ diff --git a/target/mips/translate.c b/target/mips/translate.c index ceaa582..b660235 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29803,7 +29803,7 @@ bool cpu_supports_cps_smp(const char *cpu_type) return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) !=3D 0; } =20 -bool cpu_supports_isa(const char *cpu_type, unsigned int isa) +bool cpu_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); return (mcc->cpu_def->insn_flags & isa) !=3D 0; --=20 2.7.4