From nobody Tue Feb 10 10:03:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547831430938354.1885113553175; Fri, 18 Jan 2019 09:10:30 -0800 (PST) Received: from localhost ([127.0.0.1]:43034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkXf3-0004cV-Q0 for importer@patchew.org; Fri, 18 Jan 2019 12:10:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkXV7-0003YC-9J for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkXV5-00076k-9B for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:13 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:52910 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gkXV3-0006pg-4B for qemu-devel@nongnu.org; Fri, 18 Jan 2019 12:00:11 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A83C81A22C7; Fri, 18 Jan 2019 17:59:55 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7C2761A22C9; Fri, 18 Jan 2019 17:59:55 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 17:59:38 +0100 Message-Id: <1547830785-7079-6-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Provide R/W access to SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- target/mips/cpu.h | 1 + target/mips/helper.h | 6 +++++ target/mips/internal.h | 1 + target/mips/op_helper.c | 50 +++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= +--- 5 files changed, 120 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1c2c682..185702d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -901,6 +901,7 @@ struct CPUMIPSState { uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint64_t insn_flags; /* Supported instruction set */ + int saarp; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/mips/helper.h b/target/mips/helper.h index c23e4e5..8872c46 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env) DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ =20 DEF_HELPER_2(mtc0_index, void, env, tl) @@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) diff --git a/target/mips/internal.h b/target/mips/internal.h index 8b1b245..8f6fc91 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -61,6 +61,7 @@ struct mips_def_t { target_ulong CP0_EBaseWG_rw_bitmask; uint64_t insn_flags; enum mips_mmu_types mmu_type; + int32_t SAARP; }; =20 extern const struct mips_def_t mips_defs[]; diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index d1f1d1a..409c136 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return count; } =20 +target_ulong helper_mfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + +target_ulong helper_mfhc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; + } + return 0; +} + target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); @@ -1059,6 +1075,14 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env,= uint32_t sel) { return env->CP0_WatchLo[sel]; } + +target_ulong helper_dmfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} #endif /* TARGET_MIPS64 */ =20 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1598,6 +1622,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulo= ng arg1) qemu_mutex_unlock_iothread(); } =20 +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D arg1 & 0x3f; + if (target <=3D 1) { + env->CP0_SAARI =3D target; + } +} + +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + } +} + +void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D + (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | + (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + } +} + void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; diff --git a/target/mips/translate.c b/target/mips/translate.c index 827d0f7..00cbbf7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2537,6 +2537,7 @@ typedef struct DisasContext { bool mrp; bool nan2008; bool abs2008; + bool saar; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -6592,6 +6593,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfhc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } + break; case CPO_REGISTER_17: switch (sel) { case 0: @@ -6662,6 +6674,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; } break; + case CPO_REGISTER_09: + switch (sel) { + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mthc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; + default: + goto cp0_unimplemented; + } case CPO_REGISTER_17: switch (sel) { case 0: @@ -7048,7 +7070,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -7753,7 +7784,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -8498,7 +8538,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) ctx->base.is_jmp =3D DISAS_EXIT; rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI)); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_dmfc0_saar(arg, cpu_env); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } @@ -9186,7 +9235,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) gen_helper_mtc0_count(cpu_env, arg); rn =3D "Count"; break; - /* 6,7 are implementation dependent */ + case 6: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saari(cpu_env, arg); + rn =3D "SAARI"; + break; + case 7: + CP0_CHECK(ctx->saar); + gen_helper_mtc0_saar(cpu_env, arg); + rn =3D "SAAR"; + break; default: goto cp0_unimplemented; } --=20 2.7.4