From nobody Mon Feb 9 23:39:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547749272066268.6823586356488; Thu, 17 Jan 2019 10:21:12 -0800 (PST) Received: from localhost ([127.0.0.1]:49524 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkCHu-0004ik-SG for importer@patchew.org; Thu, 17 Jan 2019 13:21:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:53172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkCBe-00088Y-8B for qemu-devel@nongnu.org; Thu, 17 Jan 2019 13:14:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkCBZ-0004aa-P5 for qemu-devel@nongnu.org; Thu, 17 Jan 2019 13:14:39 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:51733 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gkCBV-000412-Vh for qemu-devel@nongnu.org; Thu, 17 Jan 2019 13:14:35 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 7EA231A2245; Thu, 17 Jan 2019 19:13:12 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 46F0F1A2101; Thu, 17 Jan 2019 19:13:12 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 17 Jan 2019 19:13:00 +0100 Message-Id: <1547748785-14030-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1547748785-14030-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1547748785-14030-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Yongbok Kim Update ITU to utilize SAARI and SAAR CP0 registers. Reviewed-by: Stefan Markovic Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic --- hw/mips/cps.c | 8 ++++++++ hw/misc/mips_itu.c | 28 ++++++++++++++++++++++------ include/hw/misc/mips_itu.h | 4 ++++ target/mips/cpu.h | 5 +++++ target/mips/op_helper.c | 14 ++++++++++++++ 5 files changed, 53 insertions(+), 6 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 4285d19..fc97f59 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) Error *err =3D NULL; target_ulong gcr_base; bool itu_present =3D false; + bool saar_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { cpu =3D MIPS_CPU(cpu_create(s->cpu_type)); @@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) itu_present =3D true; /* Attach ITC Tag to the VP */ env->itc_tag =3D mips_itu_get_tag_region(&s->itu); + env->itu =3D &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } =20 cpu =3D MIPS_CPU(first_cpu); env =3D &cpu->env; + saar_present =3D (bool)env->saarp; =20 /* Inter-Thread Communication Unit */ if (itu_present) { @@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **e= rrp) =20 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &er= r); + object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-pres= ent", + &err); + if (saar_present) { + qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_S= AAR); + } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 4801958..5c49bdd 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -84,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, u= nsigned size) return tag->ITCAddressMap[index]; } =20 -static void itc_reconfigure(MIPSITUState *tag) +void itc_reconfigure(MIPSITUState *tag) { uint64_t *am =3D &tag->ITCAddressMap[0]; MemoryRegion *mr =3D &tag->storage_io; @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 + if (tag->saar_present) { + address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; + size =3D 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f); + is_enabled =3D *(uint64_t *) tag->saar & 1; + } + memory_region_transaction_begin(); if (!(size & (size - 1))) { memory_region_set_size(mr, size); @@ -150,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + if (s->saar_present) { + return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & + ITC_ICR0_BLK_GRAIN_MASK); + } else { + return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK); + } } =20 static inline ITCStorageCell *get_cell(MIPSITUState *s, @@ -499,10 +510,15 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - s->ITCAddressMap[0] =3D 0; - s->ITCAddressMap[1] =3D - ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | - (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + if (s->saar_present) { + *(uint64_t *) s->saar =3D 0x11 << 1; + s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; + } else { + s->ITCAddressMap[0] =3D 0; + s->ITCAddressMap[1] =3D + ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | + (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + } itc_reconfigure(s); =20 itc_reset_cells(s); diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 45a0c51..c44e767 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -70,6 +70,10 @@ typedef struct MIPSITUState { /* ITU Control Register */ uint64_t icr0; =20 + /* SAAR */ + bool saar_present; + void *saar; + } MIPSITUState; =20 /* Get ITC Configuration Tag memory region. */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 185702d..48e86d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -326,6 +326,7 @@ struct TCState { =20 }; =20 +struct MIPSITUState; typedef struct CPUMIPSState CPUMIPSState; struct CPUMIPSState { TCState active_tc; @@ -917,6 +918,7 @@ struct CPUMIPSState { const mips_def_t *cpu_model; void *irq[8]; QEMUTimer *timer; /* Internal timer */ + struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ }; @@ -1059,6 +1061,9 @@ void cpu_set_exception_base(int vp_index, target_ulon= g address); /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); =20 +/* mips_itu.c */ +void itc_reconfigure(struct MIPSITUState *tag); + /* helper.c */ target_ulong exception_resume_pc (CPUMIPSState *env); =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 409c136..aebad24 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1635,6 +1635,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulon= g arg1) uint32_t target =3D env->CP0_SAARI & 0x3f; if (target < 2) { env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 @@ -1645,6 +1652,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulo= ng arg1) env->CP0_SAAR[target] =3D (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } } } =20 --=20 2.7.4